JPS61257006A - Agc circuit - Google Patents

Agc circuit

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Publication number
JPS61257006A
JPS61257006A JP9771785A JP9771785A JPS61257006A JP S61257006 A JPS61257006 A JP S61257006A JP 9771785 A JP9771785 A JP 9771785A JP 9771785 A JP9771785 A JP 9771785A JP S61257006 A JPS61257006 A JP S61257006A
Authority
JP
Japan
Prior art keywords
circuit
transistor
agc
power
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9771785A
Other languages
Japanese (ja)
Inventor
Kazumi Kuwabara
桑原 一美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9771785A priority Critical patent/JPS61257006A/en
Publication of JPS61257006A publication Critical patent/JPS61257006A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To prevent storage of electric charge in a rectifier capacitor of an AGC circuit by connecting an output of a power supply detecting circuit to an AGC control circuit and using an output of the AGC control circuit so as to control the rectifier circuit in the AGC circuit. CONSTITUTION:Transistors 37, 38 are conducted during a period T when a waveform at application of power detected by the power supply detecting circuit 25 and no electric charge is stored in the rectifier capacitor 19. Thus, in setting the period T longer slightly than the DC voltage fluctuation (leading of amplifier circuit) time of an amplifier circuit 4 at power power application and interruption, the storage of the electric charge into the rectifier capacitor 19 attended with an output DC voltage fluctuation of the amplifier circuit 4 at power application and interruption, and malfunction such that the AGC circuit is operative independently of the input signal level is prevent at application of power.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、AGC回路に係シ、とくに、AGC回路にお
ける電源の切断・投入時の過渡応答に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an AGC circuit, and particularly to a transient response when power is turned off and turned on in an AGC circuit.

〔発明の背景〕[Background of the invention]

従来技術を第6図のAGC回路のブロック図、第7図の
入出力特性図、第8図の従来の具体回路例を用いて説明
する。
The prior art will be explained using a block diagram of an AGC circuit shown in FIG. 6, an input/output characteristic diagram shown in FIG. 7, and an example of a conventional specific circuit shown in FIG.

第6図はAGC回路のブロック図で、信号源1の信号v
1は入力端子2から入力され、抵抗3を経て増幅回路4
に入力され、該増幅回路4で増幅された(あるいは、交
流利得1のバッファ増幅器を経た)後、出力端子5に出
力信号v0として出力される。一方、出力信号v0は一
点鎖線のAGC回路6内の整流回路7にも入力され、該
整流回路7の整流後の直流電圧vDoがある電位以上忙
なると、抵抗値が減少するように設定された可変抵抗素
子8を駆動し、抵抗3と可変抵抗素子8との抵抗分割に
よつて増幅回路4の入力信号レベルをほぼ−定に押える
。これにより、第6図のAGC回路の入出力特性は第7
図に示すようになる。なお、第7図において、横軸は入
力信号V、を、かつ縦軸は出力信号v0を表わしている
FIG. 6 is a block diagram of the AGC circuit, in which the signal v of signal source 1
1 is input from input terminal 2, passes through resistor 3, and goes to amplifier circuit 4.
After being amplified by the amplifier circuit 4 (or passing through a buffer amplifier with an AC gain of 1), it is output to the output terminal 5 as an output signal v0. On the other hand, the output signal v0 is also input to the rectifier circuit 7 in the AGC circuit 6 shown by the dashed line, and the resistance value is set to decrease when the rectified DC voltage vDo of the rectifier circuit 7 exceeds a certain potential. The variable resistance element 8 is driven, and the input signal level of the amplifier circuit 4 is kept at approximately - constant by resistance division between the resistance 3 and the variable resistance element 8. As a result, the input/output characteristics of the AGC circuit in FIG.
The result will be as shown in the figure. In FIG. 7, the horizontal axis represents the input signal V, and the vertical axis represents the output signal v0.

第8図は、従来のAGC回路の具体回路例である。容量
9,12および13は直流阻止用容量、抵抗10はバイ
アス電源11からのバイアス電圧を与えるバイアス抵抗
である。増幅回路4の出力信号v0は、出力端子5に出
力されるとともに、前記容量13を経て、トランジスタ
14のベースに入力される。該トランジスタの14のベ
ースには、さらに電源15との間に抵抗16が、そして
、接地との間に抵抗17が接続され、それKよって抵抗
16と抵抗17とでトランジスタ14のバイアス電圧を
任意に設定することにより、AGCの動作開始レベルを
選択している。トランジスタ14はエミッタの抵抗18
と整流用容量19とにより、エミッタホロワ検波回路を
構成し、増幅回路4にて増幅された交流信号を整流して
直流電圧vDCを得る。抵抗20はトランジスタ14の
過電流保護用である。
FIG. 8 is a specific circuit example of a conventional AGC circuit. Capacitors 9, 12, and 13 are DC blocking capacitors, and resistor 10 is a bias resistor that applies a bias voltage from bias power supply 11. The output signal v0 of the amplifier circuit 4 is output to the output terminal 5, and is also input to the base of the transistor 14 via the capacitor 13. A resistor 16 is further connected between the base of the transistor 14 and a power supply 15, and a resistor 17 is connected between the base of the transistor 14 and the ground. By setting , the AGC operation start level is selected. Transistor 14 has emitter resistor 18
and the rectifying capacitor 19 constitute an emitter follower detection circuit, which rectifies the AC signal amplified by the amplifier circuit 4 to obtain a DC voltage vDC. The resistor 20 is for overcurrent protection of the transistor 14.

さらに、トランジスタ21と抵抗22とで構成するエミ
ッタホロワ回路により、トランジスタ21の入力インピ
ーダンスを高くシ、該トランジスタ21のベース電流を
無視し得る回路とし、整流用容量19の放電時間を抵抗
18との時定数により定め得る構成になつている。
Furthermore, by using an emitter follower circuit composed of the transistor 21 and the resistor 22, the input impedance of the transistor 21 is made high, and the base current of the transistor 21 can be ignored. It has a structure that can be determined by constants.

トランジスタ21のエミッタは、ベース保護用抵抗23
を経て、可変抵抗素子のトランジスタ24のベースに接
続され、該トランジスタ24のオン抵抗と前記抵抗3と
により、増幅回路4の入力信号レベルを一定に保ってA
GC回路を構成する。
The emitter of the transistor 21 is connected to the base protection resistor 23.
The on-resistance of the transistor 24 and the resistor 3 keep the input signal level of the amplifier circuit 4 constant.
Configure the GC circuit.

このよりなAGC回路において、電源の投入・切断の繰
返しを、抵抗18と容量19とによ多構成する放電時定
数よシ短かい時間に行なうと、電源の投入・切断時の増
幅回路4の直流電圧変動のため、容量191C電荷が蓄
積される。そこで、前記電源の投入・切断繰返し後に電
源を投入すると、AGC回路が動作してしまい、かつ前
記放電時定数は通常数十秒程度と長いため、操作者に違
和感を与えるという点について配慮されていなかった。
In this type of AGC circuit, if the power is repeatedly turned on and off in a time shorter than the discharge time constant made up of the resistor 18 and the capacitor 19, the amplifier circuit 4 when the power is turned on and off is Due to the DC voltage fluctuation, a capacitance of 191C charge is accumulated. Therefore, consideration has been given to the fact that if the power is turned on after the power is turned on and off repeatedly, the AGC circuit will be activated and the discharge time constant will be long, usually about several tens of seconds, which may give the operator a sense of discomfort. There wasn't.

なお、上記従来例としては、特開昭59−1915号が
挙げられる。
Incidentally, the above-mentioned conventional example includes Japanese Patent Application Laid-Open No. 1915-1983.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記従来技術の欠点を除き、電源の投
入・切断の繰返し後においても、AGC回路の整流用容
量に電荷の蓄積を生じることのないAGC回路を提供す
るにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an AGC circuit that eliminates the drawbacks of the prior art described above and does not cause charge accumulation in the rectifying capacitor of the AGC circuit even after repeated power-on and power-off.

〔発明の概要〕[Summary of the invention]

この目的を達成するために、本発明は、信号の整流にエ
ミッタホロワ検波回路を用いたAGC回路において、エ
ミッタホロワのトランジスタのベースに設置したトラン
ジスタを動作(ON)非動作(OFF)するとともに、
エミッタホロワのトランジスタのエミッタにもトランジ
スタを設置し、ベースに設置したトランジスタと同期し
て動作/非動作させ、上記設置トランジスタの動作/非
動作制御を、電源の投入・切断時を検出した信号によっ
て行なうことにより、電源の投入・切断時に整流用容量
の電荷を常に放電させて電源の投入・切断繰返し後の電
源投入時のAr0回路の誤動作を防止するようにした点
に特徴がある。
In order to achieve this object, the present invention operates (ON) and deactivates (OFF) a transistor installed at the base of an emitter follower transistor in an AGC circuit that uses an emitter follower detection circuit for signal rectification.
A transistor is also installed at the emitter of the emitter follower transistor, and the transistor is operated/deactivated in synchronization with the transistor installed at the base, and the operation/deactivation of the installed transistor is controlled by a signal detected when the power is turned on or off. As a result, the electric charge of the rectifying capacitor is always discharged when the power is turned on and off, thereby preventing the Ar0 circuit from malfunctioning when the power is turned on after the power is turned on and off repeatedly.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を図でもって説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明によるAGC回路の一実施例を示すブロ
ック図であって、6はAGC回路、15は電源、25は
電源検出回路、26はAGC制御回路である。なお、そ
の他の第6図と同一部分には同一符号が付しである。
FIG. 1 is a block diagram showing an embodiment of an AGC circuit according to the present invention, in which 6 is an AGC circuit, 15 is a power supply, 25 is a power supply detection circuit, and 26 is an AGC control circuit. Note that other parts that are the same as those in FIG. 6 are given the same reference numerals.

第1図においては、第6図の従来のブロック図に対して
、電源15を電源検出回路25に接続し、さらに5その
出力をAGC制御回路26に接続し、該AGC制御回路
の出力によってAGC回路内の整流回路7を制御するよ
うに構成されている。
In FIG. 1, in contrast to the conventional block diagram of FIG. 6, a power supply 15 is connected to a power supply detection circuit 25, and its output is further connected to an AGC control circuit 26, and the output of the AGC control circuit is used to control the AGC control circuit. It is configured to control the rectifier circuit 7 in the circuit.

上記電源検出回路25の具体回路例を第2図に基づいて
説明する。図において、電源15に一端を接続された抵
抗27は、その他端で容量2日とトランジスタ29のベ
ースに接続され、容量28の他端は接地されている。ト
ランジスタ29のコレクタは電源15に、エミッタはN
PNトランジスタ31のエミッタと定電流源50とに各
々接続サレる。NPN )ランジスタロ1のコレクタは
抵抗34およびPNP トランジスタ35のベースに、
また、そのベースは抵抗32およびssK@続され、そ
して抵抗34と32の他端は電源15に、抵抗33の他
端は接地される。さらに、PNP トランジスタ35の
エミッタは電源15に、コレクタは抵抗36を介して接
地されている。
A specific circuit example of the power supply detection circuit 25 will be explained based on FIG. 2. In the figure, a resistor 27 has one end connected to the power supply 15, the other end of which is connected to a capacitor 2 and the base of a transistor 29, and the other end of the capacitor 28 is grounded. The collector of the transistor 29 is connected to the power supply 15, and the emitter is connected to the N
The emitter of the PN transistor 31 and the constant current source 50 are connected to each other. The collector of NPN) transistor 1 is connected to the resistor 34 and the base of PNP transistor 35,
Further, its base is connected to a resistor 32 and ssK@, and the other ends of the resistors 34 and 32 are connected to the power supply 15, and the other end of the resistor 33 is grounded. Further, the emitter of the PNP transistor 35 is connected to the power supply 15, and the collector is connected to ground via a resistor 36.

上記電源検出回路の各部の波形は、第3図に示すごとく
、まず電源が投入されると、NPN)ランジスタ29の
ベースの波形は、イで示すごとく、抵抗27と容量28
とで定まる時定数によって容量28が充電され、この充
電は電源電位vcctで行なわれる。一方、トランジス
タ310ペースの波形は、口に示すごとく、電源が投入
されると、瞬時に抵抗32と抵抗33とによって定まる
電位v1になる。NPNトランジスタ29と31とによ
)構成された差動回路は、イの波形の電位が口の波形の
電位V、に達するまでの期間Tにおいて、NPNトラン
ジスタ31が導通し、抵抗54の電圧降下によ、9、P
NPトランジスタ35は順方向バイアスが与えられて導
通し、トランジスタ35のコレクタの波形ハはほぼ電源
電圧vCcとなる。
As shown in FIG. 3, when the power is first turned on, the waveforms of the base of the NPN transistor 29 are as shown in FIG.
Capacitor 28 is charged with a time constant determined by , and this charging is performed at power supply potential vcct. On the other hand, as shown above, when the power is turned on, the waveform of the transistor 310 instantly becomes the potential v1 determined by the resistors 32 and 33. In the differential circuit configured by the NPN transistors 29 and 31, the NPN transistor 31 becomes conductive and the voltage drop across the resistor 54 occurs during the period T until the potential of the waveform A reaches the potential V of the waveform A. Yo, 9, P
The NP transistor 35 is forward-biased and becomes conductive, and the waveform C at the collector of the transistor 35 becomes approximately the power supply voltage vCc.

さらに、イの電位がV、を越すと、NPNトランジスタ
29が導通し、トランジスタ31は非導通となり、した
がってPNPトランジスタ354非導通となって波形ハ
は接地電位となる。
Furthermore, when the potential of A exceeds V, the NPN transistor 29 becomes conductive and the transistor 31 becomes non-conductive, so the PNP transistor 354 becomes non-conductive and the waveform C becomes the ground potential.

本発明の全体の実施例を示す第4図において、NPN)
ランジスタ14.21のベースには、各々トランジスタ
37と38のコレクタが接続されている。これらのトラ
ンジスタ37と38のベースには、接地間に誤動作防止
用抵抗39およびベース電流保護抵抗40が各々接続さ
れてAGC制御回路26を構成する。さらに、抵抗40
の他端は電源検出回路25のPNP )ランジスタ35
と抵抗36に接続される。
In FIG. 4 showing the overall embodiment of the present invention, NPN)
The bases of transistors 14 and 21 are connected to the collectors of transistors 37 and 38, respectively. A malfunction prevention resistor 39 and a base current protection resistor 40 are connected between the bases of these transistors 37 and 38 and ground, respectively, thereby forming the AGC control circuit 26. Furthermore, resistance 40
The other end is the PNP transistor 35 of the power supply detection circuit 25.
and is connected to the resistor 36.

上記構成により、電源投入時に、電源検出回路25で検
出した電源投入時の第3図のハの波形°が”H#の期間
Tにおいては、トランジスタ37および38が導通され
ておシ、シたがって整流用容量19には電荷が蓄積され
ていない。よって、上記期間Tを電源投入・切断時の増
幅回路4の出力の直流電圧変動(増幅回路の立上り)時
間よシ若干長く設定すれば、電源投入・切断時の増幅回
路4の出力直流電圧変動に伴なう整流用容量19への電
荷の蓄積を防止でき、電源投入時にAGCが動作すると
いうAGC回路の誤動作を防止できる。
With the above configuration, when the power is turned on, the transistors 37 and 38 are conductive during the period T when the waveform C in FIG. 3 detected by the power supply detection circuit 25 is "H#". Therefore, if the period T is set to be slightly longer than the DC voltage fluctuation time (rise of the amplifier circuit) of the output of the amplifier circuit 4 when the power is turned on and off, It is possible to prevent charge from accumulating in the rectifying capacitor 19 due to fluctuations in the output DC voltage of the amplifier circuit 4 when the power is turned on and off, and it is possible to prevent malfunction of the AGC circuit where the AGC operates when the power is turned on.

第5図は本発明によるAGC回路の他の実施例を示す全
体回路図であって、41はPNP トランジスタ、42
はトランジスタ、45.44は抵抗、45は定電流源、
46.47はトランジスタ、48゜49は抵抗、50は
抵抗でおり、第4図に対応する部分に同一符号をつけて
重複する説明を省略する。
FIG. 5 is an overall circuit diagram showing another embodiment of the AGC circuit according to the present invention, in which 41 is a PNP transistor, 42
is a transistor, 45.44 is a resistor, 45 is a constant current source,
46 and 47 are transistors, 48.degree. 49 is a resistor, and 50 is a resistor, and parts corresponding to those in FIG. 4 are given the same reference numerals and redundant explanations will be omitted.

第5図に示す本発明の他の実施例において、出力信号v
0はPNPトランジスタ41に入力され、トランジスタ
42との差動増幅回路により、トランジスタ42のコレ
クタに出力される。出力レベルは抵抗43と抵抗44に
より定まり、AGCの動作開始レベルを決めている。符
号45は差動増幅回路の定電流源である。さらに、本実
施例の回路では、トランジスタ21は電圧・電流変換回
路として動作し、トランジスタ46および47と抵抗4
8および49から成るカレントミラー回路で定電流化さ
れて可変抵抗素子のトランジスタ24を駆動する。抵抗
50はトランジスタ47のリーク防止用である。本回路
においても、AGC制御回路26のトランジスタ37お
よび3Bが電源検出回路25からの信号により導通して
いる期間、整流用容量19には電荷が蓄積されず、第4
図の回路と同様な働きをすることは明白である。さらに
、第5図の回路例においては、電源検出回路25のトラ
ンジスタ29のベースをアノード側とし、かつトランジ
スタ31のベースをカソード側としたダイオード51を
挿入している。このダイオード51はトランジスタ29
のベース電位をトランジスタ31のベース電位よりベー
ス・エミッタ電圧VB1分高い電圧でクランプし、電源
切断時の容量2日の放電時間を早めるのに役立つ。ダイ
オード51を任意の数に選ぶことにより、トランジスタ
29のベースは任意の電位に設定できる。
In another embodiment of the invention shown in FIG.
0 is input to the PNP transistor 41, and is output to the collector of the transistor 42 through a differential amplifier circuit with the transistor 42. The output level is determined by a resistor 43 and a resistor 44, and determines the level at which the AGC starts operating. Reference numeral 45 is a constant current source of the differential amplifier circuit. Furthermore, in the circuit of this embodiment, the transistor 21 operates as a voltage/current conversion circuit, and the transistors 46 and 47 and the resistor 4
The current is made constant by a current mirror circuit consisting of 8 and 49, and drives the transistor 24, which is a variable resistance element. The resistor 50 is for preventing leakage of the transistor 47. In this circuit as well, during the period when the transistors 37 and 3B of the AGC control circuit 26 are conductive due to the signal from the power supply detection circuit 25, no charge is accumulated in the rectifying capacitor 19, and the fourth
It is clear that the circuit works similarly to the circuit shown in the figure. Furthermore, in the circuit example of FIG. 5, a diode 51 is inserted, with the base of the transistor 29 of the power supply detection circuit 25 serving as an anode, and the base of the transistor 31 serving as a cathode. This diode 51 is the transistor 29
The base potential of the transistor 31 is clamped at a voltage higher than the base potential of the transistor 31 by one base-emitter voltage VB, which is useful for accelerating the discharge time of the capacitor by two days when the power is turned off. By selecting an arbitrary number of diodes 51, the base of the transistor 29 can be set to an arbitrary potential.

なお、上記実施例では電源検出回路をトランジスタおよ
び抵抗ならびに容量で構成したが、マイクロコンピユー
タラ用いたシステムコントロール回路により、第3図に
示す期間Tを作成し、AGC制御回路26のトランジス
タ37.38を制御しても同様な動作をすることは明白
である。
In the above embodiment, the power supply detection circuit is composed of transistors, resistors, and capacitors, but a system control circuit using a microcomputer creates the period T shown in FIG. It is clear that the same behavior can be obtained by controlling .

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、電源の投入・切
断の繰返しを行なった後に電源を投入したとき、入力信
号レベルに関係なくAGC回路が動作状態となるような
誤動作を防止でき、上記従来技術の欠点を除いて優れた
機能のAGC回路を提供することができる。
As explained above, according to the present invention, when the power is turned on after repeatedly turning on and off the power, it is possible to prevent the malfunction in which the AGC circuit enters the operating state regardless of the input signal level. An AGC circuit with excellent functionality can be provided without the drawbacks of the prior art.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるAGC回路の一実施例を示すブロ
ック図、第2図は第1図の電源検出回路の一具体例を示
す回路図、第3図はその波形図、第4図は第1図に示し
た本発明によるAGC回路の実施例の全体回路図、第5
図は本発明によるAGC回路の他の実施例を示す全体回
路図、第6図は従来のAGC回路のブロック図、第7図
はその入出力特性図、第8図は第6図のAGC回路の全
体回路図である。 1・・・・・・信号源 3・・・・・・抵抗 4・・・・・・増幅回路 6・・・・・・AGC回路 7・・・・・・整流回路 8・・・・・・可変抵抗素子 19・・・・・・整流用容量 14.21.37.38・・・・・・トランジスタ25
・・・・・・電源検出回路 26・・・・・・AGC制御回路。
FIG. 1 is a block diagram showing an embodiment of the AGC circuit according to the present invention, FIG. 2 is a circuit diagram showing a specific example of the power supply detection circuit of FIG. 1, FIG. 3 is a waveform diagram thereof, and FIG. The overall circuit diagram of the embodiment of the AGC circuit according to the present invention shown in FIG.
6 is a block diagram of a conventional AGC circuit, FIG. 7 is its input/output characteristic diagram, and FIG. 8 is the AGC circuit of FIG. 6. FIG. 1... Signal source 3... Resistor 4... Amplifier circuit 6... AGC circuit 7... Rectifier circuit 8...・Variable resistance element 19... Rectifying capacitor 14.21.37.38... Transistor 25
...Power supply detection circuit 26...AGC control circuit.

Claims (2)

【特許請求の範囲】[Claims] (1)信号源の信号を抵抗を介して増幅回路に入力し、
該増幅回路の出力を出力信号として取り出すとともに、
前記増幅回路の出力を整流用トランジスタと平滑容量を
組み合せた整流回路にも入力し、該整流回路の出力によ
り、可変抵抗素子を駆動し、該可変抵抗素子を前記抵抗
と前記増幅回路との間に接続してなるAGC回路におい
て、電源検出回路と、該電源検出回路により駆動される
AGC制御回路とを備え、該AGC制御回路を前記整流
回路に接続したことを特徴とするAGC回路。
(1) Input the signal from the signal source to the amplifier circuit via the resistor,
While extracting the output of the amplifier circuit as an output signal,
The output of the amplifier circuit is also input to a rectifier circuit that combines a rectifier transistor and a smoothing capacitor, and the output of the rectifier circuit drives a variable resistance element, and the variable resistance element is connected between the resistance and the amplifier circuit. 1. An AGC circuit connected to the rectifier circuit, comprising: a power supply detection circuit; and an AGC control circuit driven by the power supply detection circuit, the AGC control circuit being connected to the rectification circuit.
(2)前記整流用トランジスタのベースにスイッチング
用の第1トランジスタを、エミッタにスイッチング用の
第2トランジスタを各々設け、前記第1および第2トラ
ンジスタを前記電源検出回路により駆動することを特徴
とする特許請求の範囲第1項に記載のAGC回路。
(2) A first transistor for switching is provided at the base of the rectifying transistor, and a second transistor for switching is provided at the emitter, and the first and second transistors are driven by the power supply detection circuit. An AGC circuit according to claim 1.
JP9771785A 1985-05-10 1985-05-10 Agc circuit Pending JPS61257006A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9771785A JPS61257006A (en) 1985-05-10 1985-05-10 Agc circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9771785A JPS61257006A (en) 1985-05-10 1985-05-10 Agc circuit

Publications (1)

Publication Number Publication Date
JPS61257006A true JPS61257006A (en) 1986-11-14

Family

ID=14199640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9771785A Pending JPS61257006A (en) 1985-05-10 1985-05-10 Agc circuit

Country Status (1)

Country Link
JP (1) JPS61257006A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6393208A (en) * 1986-10-07 1988-04-23 Rohm Co Ltd Automatic level control amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6393208A (en) * 1986-10-07 1988-04-23 Rohm Co Ltd Automatic level control amplifier

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