JPS61256671A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS61256671A JPS61256671A JP9855085A JP9855085A JPS61256671A JP S61256671 A JPS61256671 A JP S61256671A JP 9855085 A JP9855085 A JP 9855085A JP 9855085 A JP9855085 A JP 9855085A JP S61256671 A JPS61256671 A JP S61256671A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- gate electrode
- self
- layer
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 2
- 229910052710 silicon Inorganic materials 0.000 claims abstract 2
- 239000010703 silicon Substances 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 19
- 239000010408 film Substances 0.000 claims description 14
- 230000008021 deposition Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 13
- 239000011521 glass Substances 0.000 abstract description 8
- 239000010453 quartz Substances 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 5
- 238000011109 contamination Methods 0.000 abstract description 4
- 239000007769 metal material Substances 0.000 abstract description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 3
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 2
- 229910007264 Si2H6 Inorganic materials 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
液晶パネルの駆動などに用いる逆スタガード型薄膜トラ
ンジスタ（ＴＰＴ）のソース・ドレイン電極を、ゲート
絶縁膜、活性層と同一真空中で光ＣＶＤ法によりゲート
電極をマスクとして自己整合（セルファライン）で形成
することを可能にする。[Detailed Description of the Invention] [Summary] The source and drain electrodes of an inverted staggered thin film transistor (TPT) used for driving a liquid crystal panel, etc. are masked by photo-CVD in the same vacuum as the gate insulating film and active layer. This allows for self-alignment (self-alignment) formation.
本発明は薄膜トランジスタの製造方法に関するもので、
さらに詳しく言えば、真空を破ることなしに自己整合し
た薄膜トランジスタを製造する方法に関するものである
。The present invention relates to a method for manufacturing a thin film transistor,
More specifically, the present invention relates to a method of manufacturing self-aligned thin film transistors without breaking a vacuum.
例えば液晶パネルの駆動のための第３図の断面図に示さ
れる逆スタガード型ＴＰＴは知られたものであり、同図
において、１１はガラス基板、１２はゲート電極、１３
は例えば窒化シリコンのゲート絶縁膜、１４はアモルフ
ァスシリコン（ａ−Ｓｔ）の活性層、１５はソース電極
、１６はドレイン電極を示す。For example, an inverted staggered TPT shown in the cross-sectional view of FIG. 3 for driving a liquid crystal panel is known, and in the same figure, 11 is a glass substrate, 12 is a gate electrode, and 13 is a
14 is an active layer of amorphous silicon (a-St), 15 is a source electrode, and 16 is a drain electrode.
このようなＴＰＴの性能について問題となる点は、ゲー
ト電極とソース・ドレイン電極とが重なるとその重なっ
た部分にリーク電流が流れることと、その部分が容量に
なってトランジスタの特性に影響を与えることである。The problem with the performance of such TPTs is that when the gate electrode overlaps the source/drain electrode, leakage current flows through the overlapped area, and that area becomes capacitance, which affects the characteristics of the transistor. That's true.
そこで、そのような重なり部分を少なくしなければなら
ないのであるが、全く重ならないというのではなく僅か
に重なることが必要である。つまり、ゲート電極とソー
ス・ドレイン電極が少しばかり重なっていることにより
図に符号１７で示す部分に電子が蓄積され、ゲート電極
を十にしてソース・ドレイン電極に電圧をかけたときに
この蓄積した電子が流されるようにしなければならない
からである。かりにゲート電極とソース・ドレイン電極
が重なっていないとすると、符号１７を示した部分は大
なる抵抗となり、・トランジスタの特性を劣化させるこ
とになる。Therefore, it is necessary to reduce such overlapping portions, but it is not necessary that they overlap at all, but that they overlap slightly. In other words, because the gate electrode and the source/drain electrodes overlap a little, electrons are accumulated in the area shown by reference numeral 17 in the figure, and when a voltage is applied to the source/drain electrodes with the gate electrode set to This is because electrons must be allowed to flow. If the gate electrode and the source/drain electrodes do not overlap, the portion indicated by reference numeral 17 will have a large resistance, which will deteriorate the characteristics of the transistor.
本出願人は、第３図に示すＴＰＴをゲート電極をマスク
として自己整合で形成する方法を開発した。The applicant has developed a method for forming the TPT shown in FIG. 3 by self-alignment using the gate electrode as a mask.
この方法を第４図を参照して説明すると、ガラス基板１
１の上にゲート電極１２を形成し、プラズマＣＶＯ法テ
（Ｓｉｈ ＋ＮＨ３）を用いて絶縁膜１３を成長し、そ
の上にＳｉＨ＠ガスを用いてａ−Ｓｔの活性層１４を成
長する。次いで、全面にレジストＩｌ！！１８を塗布形
成する。To explain this method with reference to FIG. 4, the glass substrate 1
A gate electrode 12 is formed on the substrate 1, an insulating film 13 is grown using a plasma CVO method (Sih + NH3), and an a-St active layer 14 is grown thereon using SiH@gas. Next, resist Il! is applied to the entire surface! ! 18 is applied and formed.
次に第４図に矢印で示す如くガラス基板１１の側から光
を照射すると、ゲート電極１２がマスクになってレジス
ト膜の部分１８ａには光が照射されない。Next, when light is irradiated from the glass substrate 11 side as shown by the arrow in FIG. 4, the gate electrode 12 acts as a mask and the resist film portion 18a is not irradiated with light.
次にレジストを現像し、第５図に示される如く全面に金
属膜１９を付着し、リフトオフ法でレジスト膜１８ａと
その上の金属膜を除去して第３図に示したＴＰＴを完成
する。Next, the resist is developed, a metal film 19 is deposited on the entire surface as shown in FIG. 5, and the resist film 18a and the metal film thereon are removed by a lift-off method to complete the TPT shown in FIG.
前記した如く、従来技術としては、プラズマＣｖＯ法で
ゲート絶縁膜、活性層を堆積したのちレジストプロセス
によって自己整合した薄膜トランジスタを製造している
が、これには真空を破ること及びレジストプロセスから
の汚染によってトランジスタの特性が劣化するという欠
点があった。As mentioned above, in the conventional technology, a gate insulating film and an active layer are deposited using a plasma CvO method, and then self-aligned thin film transistors are manufactured using a resist process. However, this involves breaking the vacuum and preventing contamination from the resist process. This has the disadvantage that the characteristics of the transistor deteriorate.
すなわち、レジストの塗布のときに真空を破ること、お
よびレジストプロセスによって活性層が汚染されるため
ＴＰＴ特性が劣化し、またレジストプロセスによって製
造歩留りが低下するという問題がある。That is, there are problems in that the vacuum is broken during resist application, and the active layer is contaminated by the resist process, resulting in deterioration of TPT characteristics, and the resist process reduces manufacturing yield.
本発明はこのような点に鑑みて創作されたもので、光Ｃ
ＶＤ法を用いることにより同一真空中で自己整合した薄
膜トランジスタを製造する方法を提供することを目的と
する。The present invention was created in view of these points, and
It is an object of the present invention to provide a method for manufacturing self-aligned thin film transistors in the same vacuum by using the VD method.
第１図の（ａ）ないしくＣ１は本発明の方法を実施する
工程におけるＴＰＴ要部の断面図である。FIGS. 1A to 1C are cross-sectional views of the main parts of the TPT in the process of carrying out the method of the present invention.
第１図において、ゲート電極１２、ゲート絶縁膜１３、
活性層１４、ソース・ドレイン電極１５からなるＴＰＴ
をガラス基板１１上に形成するにおいて、ゲート絶縁膜
１３、活性層１４の堆積と同一真空中でガラス基板１１
側から光を照射し、ゲート電極１２をマスクとして自己
整合したドープしたａ−３ｔ １４ａおよびソース・ド
レイン電極１５を光ＣＶＤ法によって形成する。In FIG. 1, a gate electrode 12, a gate insulating film 13,
TPT consisting of active layer 14 and source/drain electrodes 15
is formed on the glass substrate 11 in the same vacuum as the deposition of the gate insulating film 13 and the active layer 14.
By irradiating light from the side and using the gate electrode 12 as a mask, self-aligned doped a-3t 14a and source/drain electrodes 15 are formed by photo-CVD.
上記方法は、光ＣＶＤ法において光の照射した部分のみ
に膜が堆積することを利用してゲート絶縁膜・活性層の
堆積と同一真空中で、基板側からの光照射によって自己
整合したソース°・ドレイン電極を光ＣＶＤ法によって
形成するようにしたものである。The method described above takes advantage of the fact that a film is deposited only on the area irradiated with light in the photo-CVD method. - The drain electrode is formed by photo-CVD.
第１図（ａｌないしくＣ）および第２図を参照して本発
明実施例を詳細に説明する。Embodiments of the present invention will be described in detail with reference to FIG. 1 (al to C) and FIG. 2.
先ず、第１図（ａ）に示される如く、ゲート電極（Ｃｒ
） １２をパターニングしたガラス（石英）基板１１上
に、プラズマＣｖＤ法によって窒化シリコンのゲート絶
縁膜１３、ａ−３ｔの活性層１４を従来例の場合と同様
に堆積する。First, as shown in FIG. 1(a), a gate electrode (Cr
) A gate insulating film 13 of silicon nitride and an active layer 14 of a-3t are deposited on a glass (quartz) substrate 11 patterned with 12 by the plasma CVD method in the same manner as in the conventional example.
前記した光ＣＶＤ法は第２図の断面図に示される装置を
用いて行うもので、同図において、２１はチャンバ（０
，Ｉ Ｔｏｒｒの真空に保たれる）、２２は放電電極、
２３は高周波電波、２４は石英窓を示し、この石英窓を
通して後述するＡｒＦエキシマレーザ２５が照射される
。The photo-CVD method described above is carried out using the apparatus shown in the cross-sectional view of FIG. 2, in which 21 is a chamber (0
, I Torr), 22 is a discharge electrode,
Reference numeral 23 indicates a high frequency radio wave, and 24 indicates a quartz window, through which an ArF excimer laser 25, which will be described later, is irradiated.
ガラス基板１１を図示の位置に配置してゲート絶縁Ｉ！
ｌ！！１３を堆積し、次にシラン（Ｓｉｈ ）ガスを導
入してａ−Ｓｔの活性層１４を堆積する。The glass substrate 11 is placed in the illustrated position and the gate insulation I!
l! ! 13 is deposited, and then silane (Sih) gas is introduced to deposit an active layer 14 of a-St.
次に同一真空中でジシラン（ＳｉｚＨ６）とＰＨ３をチ
ャンバ２１内に導入し、石英基板側１１からＡｒＦエキ
シマレーザ２５を照射してゲート電極１２によってマス
クされた上部を除いたａ−３ｔ上に第１図世）に示され
る如く光ＣＶＤ法によってｎ”−Ｓｔ層１４ａを形成す
る。ジシランガスを用いる理由は、それがシランに比べ
て分子が大であるので分解エネルギーが小であり、かつ
、光エネルギーの吸収係数が大であるからである。なお
、ドープされたｎ”ａ−５ｔ層１４ａを形成する理由は
、その上に形成される電極金属材料とのコンタクトをと
り易くするためである（ドープされないｎ型のａ−３ｔ
と金属材料とのコンタクトは良くない）。Next, disilane (SizH6) and PH3 are introduced into the chamber 21 in the same vacuum, and ArF excimer laser 25 is irradiated from the quartz substrate side 11 to form a layer on a-3t excluding the upper part masked by the gate electrode 12. As shown in Figure 1), the n''-St layer 14a is formed by the photo-CVD method.The reason for using disilane gas is that its molecules are larger than silane, so the decomposition energy is small, and it is resistant to light. This is because the energy absorption coefficient is large.The reason for forming the doped n''a-5t layer 14a is to facilitate contact with the electrode metal material formed thereon ( undoped n-type a-3t
contact with metal materials is not good).
一度排気した後、有機金属材料ガス、例えばトリメチル
アルミニウム（ＴＭＡＩｌ）を導入し、同様に石英基板
側から＾ｒＦエキシマレーザ２５を照射すると、同ガス
は光で分解し、光の当ったところにＡＩが堆積するから
、ゲート電極１２をマスクとした自己整合したソース・
ドレイン電極（Ａｌ） １５が形成される（第１図（Ｃ
））。Once exhausted, an organometallic material gas such as trimethylaluminum (TMAIl) is introduced, and when the ^rF excimer laser 25 is irradiated from the quartz substrate side, the gas is decomposed by the light and an AI is formed where the light hits. is deposited, so a self-aligned source electrode using the gate electrode 12 as a mask is formed.
A drain electrode (Al) 15 is formed (Fig. 1(C)
)).
このようにして、本実施例によれば、同一真空中で自己
整合した薄膜トランジスタを製造できるので不純物等に
よる汚染の影響が減少し、特性を向上させることができ
るのである。In this way, according to this embodiment, self-aligned thin film transistors can be manufactured in the same vacuum, so that the influence of contamination due to impurities etc. can be reduced and the characteristics can be improved.
以上述べてきたように、本発明によれば同一真空中で自
己整合した薄膜トランジスタを製造することができるの
で、不純物等による汚染の影響が減少でき、トランジス
タの特性の向上が図れ、また製造歩留りが向上する効果
がある。As described above, according to the present invention, self-aligned thin film transistors can be manufactured in the same vacuum, so the influence of contamination due to impurities etc. can be reduced, the characteristics of the transistor can be improved, and the manufacturing yield can be improved. It has an improving effect.
第１図（ａ）ないしくＣ）は本発明方法を実施する工程
における半導体装置要部の断面図、
第２図は第１図の工程を実施する装置の断面図である。
第３図は逆スタガード型ＴＰＴの断面図、第４図と第５
図は第３図のＴＰＴを作る従来工程を示す断面図、
第１図ないし第５図において、
１１はガラス（石英）基板、
１２はゲート電極、
１３はゲート絶縁膜、
１４は活性層、
１４ａはドープされたｎ”ａ−５ｔ層、１５はソース・
ドレイン電極、
２１は真空チャンバ、
２２は放電電極、
２３は高周波電源、
２４は石英窓、
２５はＡｒＦエキシマレーザである。
枦トＲ喫恍例断面団
第１図
丸ＣＶＯ覧１
第２図
従来例跡面図
第３図
↑↑ ↑↑
従来例跡面図
第４図
従来例＃面図
第５図FIGS. 1A to 1C are cross-sectional views of essential parts of a semiconductor device in steps of carrying out the method of the present invention, and FIG. 2 is a cross-sectional view of an apparatus carrying out the steps of FIG. 1. Figure 3 is a cross-sectional view of an inverted staggered TPT, Figures 4 and 5
The figure is a cross-sectional view showing the conventional process for making the TPT shown in Figure 3. In Figures 1 to 5, 11 is a glass (quartz) substrate, 12 is a gate electrode, 13 is a gate insulating film, 14 is an active layer, 14a 15 is the doped n”a-5t layer, and 15 is the source layer.
21 is a vacuum chamber, 22 is a discharge electrode, 23 is a high frequency power source, 24 is a quartz window, and 25 is an ArF excimer laser. Figure 1 Circle CVO view 1 Figure 2 Remains of conventional example Figure 3 ↑↑ ↑↑ Remains of conventional example Figure 4 View of conventional example # View 5
Claims (1)
１４）、ソース・ドレイン電極（１５）から成る逆スタ
ガード型薄膜トランジスタの製造において、ゲート絶縁
膜（１３）、活性層（１４）の堆積と同一真空中で、 ゲート電極（１２）をマスクとして光ＣＶＤ法によって
自己整合したドープされたシリコン層（１４＿ａ）およ
びソース・ドレイン電極（１５）を形成することを特徴
とする薄膜トランジスタの製造方法。[Claims] Gate electrode (12), gate insulating film (13), active layer (
14) In the production of an inverted staggered thin film transistor consisting of source and drain electrodes (15), photo-CVD is performed using the gate electrode (12) as a mask in the same vacuum as the deposition of the gate insulating film (13) and the active layer (14). A method for manufacturing a thin film transistor, characterized in that a self-aligned doped silicon layer (14_a) and a source/drain electrode (15) are formed by a method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9855085A JPS61256671A (en) | 1985-05-09 | 1985-05-09 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9855085A JPS61256671A (en) | 1985-05-09 | 1985-05-09 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61256671A true JPS61256671A (en) | 1986-11-14 |
Family
ID=14222796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9855085A Pending JPS61256671A (en) | 1985-05-09 | 1985-05-09 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61256671A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63187620A (en) * | 1987-01-30 | 1988-08-03 | Sony Corp | Manufacture of semiconductor device |
| KR100271897B1 (en) * | 1991-05-13 | 2000-11-15 | 이데이 노부유끼 | Semiconductor device and method for manufacturing thereof |
| KR100397875B1 (en) * | 2000-05-18 | 2003-09-13 | 엘지.필립스 엘시디 주식회사 | Thin Film Transistor and method for fabricating the same |
| US20090236593A1 (en) * | 2005-10-10 | 2009-09-24 | Stmicroelectronics S.R.L. | Organic thin film transistor and process for manufacturing same |
| RU2606248C2 (en) * | 2015-05-14 | 2017-01-10 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) | Method of making a semiconductor device |
-
1985
- 1985-05-09 JP JP9855085A patent/JPS61256671A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63187620A (en) * | 1987-01-30 | 1988-08-03 | Sony Corp | Manufacture of semiconductor device |
| KR100271897B1 (en) * | 1991-05-13 | 2000-11-15 | 이데이 노부유끼 | Semiconductor device and method for manufacturing thereof |
| KR100397875B1 (en) * | 2000-05-18 | 2003-09-13 | 엘지.필립스 엘시디 주식회사 | Thin Film Transistor and method for fabricating the same |
| US20090236593A1 (en) * | 2005-10-10 | 2009-09-24 | Stmicroelectronics S.R.L. | Organic thin film transistor and process for manufacturing same |
| US8653505B2 (en) * | 2005-10-10 | 2014-02-18 | Stmicroelectronics S.R.L. | Organic thin film transistor and process for manufacturing same |
| RU2606248C2 (en) * | 2015-05-14 | 2017-01-10 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) | Method of making a semiconductor device |
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