JPS61255111A - Offset elimination circuit - Google Patents
Offset elimination circuitInfo
- Publication number
- JPS61255111A JPS61255111A JP9717785A JP9717785A JPS61255111A JP S61255111 A JPS61255111 A JP S61255111A JP 9717785 A JP9717785 A JP 9717785A JP 9717785 A JP9717785 A JP 9717785A JP S61255111 A JPS61255111 A JP S61255111A
- Authority
- JP
- Japan
- Prior art keywords
- offset
- signal
- output
- lpf
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
１１立１
本発明はオフセット除去回路に関し、特に信号処理回路
において発生したオフセットを回路出力信号から除去す
るオフセット除去回路に関する。DETAILED DESCRIPTION OF THE INVENTION 1. Field of the Invention The present invention relates to an offset removal circuit, and more particularly to an offset removal circuit that removes an offset generated in a signal processing circuit from a circuit output signal.
１米且ｌ
従来この種の回路は、第３図に示す様に除去すべきオフ
セットを発生する信号処理器１２の信号入力側に入力切
替器１１を有し、出力側にオフセット量検出１１３．反
転増幅器１４及び加算ｌ１１５を有する構成となってい
る。Conventionally, this type of circuit has an input switch 11 on the signal input side of a signal processor 12 that generates an offset to be removed, as shown in FIG. 3, and an offset amount detection unit 113 on the output side. The configuration includes an inverting amplifier 14 and an adder l115.
かかる構成において、入力切替器１１により回路の入力
熾号を断としてオフセットの量を検出してこの量を反転
増幅器１４にて反転増幅し、更に加算器１５で信号処理
器１２の出力と加算することにより、オフセット除去を
行っている。In this configuration, the input switch 11 turns off the input signal of the circuit to detect the amount of offset, the inverting amplifier 14 inverts and amplifies this amount, and the adder 15 adds it to the output of the signal processor 12. By doing this, offset is removed.
上述の従来のオフセット除去回路では、回路入力信号が
ない状態でオフセット量を検出する構成であるので、オ
フセット除去のために一定時間が必要となる欠点がある
。更に、オフセット検出が無信号時になされるので、発
生するオフセットが入力信号によって変化する場合には
使用できないという欠点がある。The conventional offset removal circuit described above is configured to detect the amount of offset in the absence of a circuit input signal, and therefore has the disadvantage that a certain amount of time is required for offset removal. Furthermore, since the offset detection is performed when there is no signal, there is a drawback that it cannot be used when the generated offset changes depending on the input signal.
及ｔｍ造
本発明の目的は、信号処理部の動作を中断することなく
連続信号のオフセット除去が可能なオフセット除去回路
を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide an offset removal circuit that can remove offsets from continuous signals without interrupting the operation of a signal processing section.
及」１口１處
本発明によるオフセット除去回路は、入力出力の直流成
分を検出する検出手段と、この検出手段の出力を反転す
る反転増幅器と、この反転増幅器の出力を入力信号と加
算する加算器とを有讐ることを特徴とする。The offset removal circuit according to the present invention includes a detection means for detecting a DC component of an input output, an inverting amplifier for inverting the output of the detecting means, and an addition circuit for adding the output of the inverting amplifier to the input signal. It is characterized by having an enmity with the vessel.
実施例 以下、図面を用いて本発明の詳細な説明する。Example Hereinafter, the present invention will be explained in detail using the drawings.
第１図は本発明の実施例の構成図であり、１はローパス
フィルタ（ＬＰＦ）、、２は反転増幅器。FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is a low-pass filter (LPF), and 2 is an inverting amplifier.
３は加算器をそれぞれ示す。第２図（ａ）に示す様なオ
フセットを含んだ信号がＬＰＦ３に入力された場合につ
き説明する。しＰＦＩの遮断周波数を信号周波数よりも
十分低く設定すれば、第２図（ｂ）に示すように、ＬＰ
ＦＩの出力には入力信号のうちの直流成分のみが出力さ
れる。これが除去すべきＤＣ（直流）オフセットに相当
する。よって、この直流成分を反転増幅器２で反転し、
加算器３にて入力信号に加算することでオフセットの除
去が可能となるのである。3 indicates an adder, respectively. The case where a signal including an offset as shown in FIG. 2(a) is input to the LPF 3 will be explained. If the PFI cutoff frequency is set sufficiently lower than the signal frequency, the LP
Only the DC component of the input signal is outputted from the FI. This corresponds to the DC (direct current) offset to be removed. Therefore, this DC component is inverted by the inverting amplifier 2,
The offset can be removed by adding it to the input signal in the adder 3.
発明の詳細
な説明した如く、本発明によれば、従来例では困難であ
った連続信号のオフセット除去を可能とし得る効果があ
る。As described in detail, the present invention has the effect of making it possible to remove the offset of a continuous signal, which was difficult in the conventional example.
第１図は本発明の実施例のブロック図、第２図（ａ）は
除去すべきオフセットを含んだ入力信号及び第２図（ｂ
）はＬＰＦ出力信号を夫々示す波形図、第３図は従来例
を示すブロック図である。
主要部分の符号の説明
１・・・・・・ＬＰＦ
２・・・・・・反転増幅器
３・・・・・・加算器FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2(a) shows an input signal including an offset to be removed, and FIG. 2(b)
) are waveform diagrams showing the LPF output signals, and FIG. 3 is a block diagram showing a conventional example. Explanation of symbols of main parts 1...LPF 2...Inverting amplifier 3...Adder
Claims (1)
段の出力を反転する反転増幅器と、前記反転増幅器の出
力を前記入力信号と加算する加算器とを有することを特
徴とするオフセット除去回路。An offset removal circuit comprising: detection means for detecting a DC component of an input signal; an inverting amplifier for inverting the output of the detection means; and an adder for adding the output of the inverting amplifier to the input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9717785A JPS61255111A (en) | 1985-05-08 | 1985-05-08 | Offset elimination circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9717785A JPS61255111A (en) | 1985-05-08 | 1985-05-08 | Offset elimination circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61255111A true JPS61255111A (en) | 1986-11-12 |
Family
ID=14185299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9717785A Pending JPS61255111A (en) | 1985-05-08 | 1985-05-08 | Offset elimination circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61255111A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01172934A (en) * | 1987-12-28 | 1989-07-07 | Matsushita Electric Ind Co Ltd | Non-linear optical element |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS538181A (en) * | 1976-07-12 | 1978-01-25 | Nippon Steel Corp | Local iron loss measuring instrument |
| JPS5460544A (en) * | 1977-10-24 | 1979-05-16 | Nippon Steel Corp | Correcting method for electric signal distortion |
-
1985
- 1985-05-08 JP JP9717785A patent/JPS61255111A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS538181A (en) * | 1976-07-12 | 1978-01-25 | Nippon Steel Corp | Local iron loss measuring instrument |
| JPS5460544A (en) * | 1977-10-24 | 1979-05-16 | Nippon Steel Corp | Correcting method for electric signal distortion |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01172934A (en) * | 1987-12-28 | 1989-07-07 | Matsushita Electric Ind Co Ltd | Non-linear optical element |
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