CN110199475B

CN110199475B - Signal processing device

Info

Publication number: CN110199475B
Application number: CN201880008217.3A
Authority: CN
Inventors: 小川贵之
Original assignee: KYB Corp
Current assignee: KYB Corp
Priority date: 2017-01-30
Filing date: 2018-01-15
Publication date: 2023-07-14
Anticipated expiration: 2038-01-15
Also published as: JP2018125600A; WO2018139225A1; CN110199475A; JP6792467B2

Abstract

The present invention discloses a signal processing apparatus capable of canceling a phase shift of an output signal with respect to a signal. Accordingly, the signal processing device of the present invention is provided with: a filter (1) that filters the signal (IS); and an output unit (2) that outputs an Output Signal (OS) based on the phase of the signal (IS) and the processed signal (TS) processed by the filter (1).

Description

Signal processing device

Technical Field

The present invention relates to a signal processing apparatus.

Background

Such a signal processing device is used in, for example, a control device, etc., and processes a signal output from a sensor and inputs the processed signal to the control device. The signal processing device removes noise contained in the output of the sensor, and extracts only a frequency band component necessary for the control device from the output signal of the sensor, so that the signal processing device is widely used in various devices.

For example, the signal processing device is configured as a bandpass filter as disclosed in JP2013-1304A, which is an example of application to a railway vehicle damping device. Specifically, the signal processing device is configured to process a signal output from the acceleration sensor, remove noise and a stable acceleration component during curved running, and extract only a vibration component in a frequency band that deteriorates riding comfort in the vehicle.

In this way, the signal processing apparatus extracts only the component to be extracted from various signals, but the output signal obtained by processing the signal is always shifted in phase from the original signal.

In this way, in a control system using an output signal processed by a signal processing device, if the control gain is increased, the system becomes unstable, and therefore, there is a limit even if the control performance is to be improved.

In addition, if the order of the filter is set to a high order, the gain attenuation rate is improved, but the phase angle is increased, so that the problem is not solved.

Disclosure of Invention

It is therefore an object of the present invention to provide a signal processing apparatus capable of eliminating phase shift.

The signal processing device of the present invention comprises: a filter that filters a signal; and an output unit that outputs an output signal based on the phase of the signal and the processed signal processed by the filter, thereby obtaining an output signal that is not phase-shifted from the original signal.

Drawings

Fig. 1 is a diagram showing the structure of a signal processing apparatus in the first embodiment.

Fig. 2 is a diagram showing waveforms of an original signal and a signal after a high-pass filtering process.

Fig. 3 is a diagram showing waveforms of output signals output when the original signals are processed by the signal processing apparatus in the first embodiment.

Fig. 4 is a diagram showing waveforms of original signals whose amplitude center value is not 0.

Fig. 5 is a diagram showing waveforms of output signals output when the signal processing apparatus in the first embodiment processes an original signal whose amplitude center value is not 0.

Fig. 6 is a diagram showing the structure of a signal processing device in the second embodiment.

Fig. 7 is a diagram showing waveforms of an original signal and a signal after the low-pass filtering process.

Fig. 8 is a diagram showing waveforms of output signals output when the signal processing apparatus in the second embodiment processes an original signal.

Fig. 9 is a diagram showing the structure of a signal processing device in the third embodiment.

Fig. 10 is a diagram showing waveforms of output signals output when the signal processing apparatus in the third embodiment processes an original signal.

Detailed Description

< first embodiment >, first embodiment

The present invention will be described below based on the illustrated embodiments. As shown in fig. 1, a signal processing device S1 according to a first embodiment includes: a filter 1 and an output section 2. In this example, the signal processing device S1 performs a high-pass filtering process on the original signal IS.

The filter 1 IS set to a high-pass filter, and in this example, a signal IS output by the acceleration sensor a detecting acceleration IS used as an original signal, and the signal IS subjected to a high-pass filter process to output a processed signal TS. The processed signal TS is input to the output unit 2. The processed signal TS IS input to the output unit 2 as well as the signal IS. The filter 1 may be set as an analog filter or a filter implemented by the arithmetic processing device through execution of software. The cut-off frequency of the filter 1 may be set so as to be suitable for extracting components in a frequency band required by the control device of the output signal OS outputted by the signal processing device S1.

The output unit 2 outputs the output signal OS based on the phase of the signal IS and the processed signal TS processed by the filter 1. First, for the sake of understanding, a process in which the output unit 2 outputs the output signal OS will be described, taking as an example a case where the signal IS a waveform vibrating with 0 as the center and the amplitude center value IS 0. In order to further normalize the output process of the output signal OS by the output unit 2, the output process of the output signal OS in the case where the signal IS a waveform that vibrates around the amplitude center value α will be described.

As shown in fig. 2, if the signal IS a signal shown by a solid line in fig. 2 vibrating around 0, when the high-pass filtering process IS performed by the filter 1, the processed signal TS IS advanced in phase as the amplitude decays as shown by a broken line in fig. 2.

The output unit 2 compares the signal IS with the processed signal TS to determine whether it IS in phase or in antiphase. The case where the signal IS and the processed signal TS are in phase refers to the case where both the signal IS and the processed signal TS are 0 or more and are located in a range above the time axis in fig. 2, or the case where both the signal IS and the processed signal TS are smaller than 0 and are located in a range below the time axis in fig. 2. The case where the signal IS and the processed signal TS are in opposite phases refers to the case where one of the signal IS and the processed signal TS IS in a range above the time axis in fig. 2 and the other of the signal IS and the processed signal TS IS less than 0 and in a range below the time axis in fig. 2 with the amplitude center 0 as a reference.

The case where the signal IS and the processed signal TS are in phase means that even if the processed signal TS output from the filter 1 IS used as the output signal OS, the output signal OS does not become a signal having an opposite phase to the signal IS, but when the signal IS and the processed signal TS are in opposite phase, the output signal OS IS a signal having an opposite phase to the signal IS.

Thus, when the signal IS and the processed signal TS are in opposite phases, the output unit 2 outputs 0 as the output signal OS. In addition, when the signal IS and the processed signal TS are in phase, the absolute value of the signal IS and the absolute value of the processed signal TS are always compared, and a signal having a smaller absolute value IS selected and outputted as the output signal OS.

More specifically, the output unit 2 determines whether the signal IS and the processed signal TS are in phase or in antiphase by using a value obtained by multiplying the value U1 of the signal IS and the value U2 of the processed signal TS. If the value obtained by multiplying the value U1 of the signal IS and the value U2 of the processed signal TS IS 0 or more, that IS, if u1×u2 IS equal to or greater than 0, the output unit 2 determines that the signal IS and the processed signal TS are in phase. In contrast, if the value obtained by multiplying the value U1 of the signal IS and the value U2 of the processed signal TS IS smaller than 0, that IS, if u1×u2 < 0, the output unit 2 determines that the signal IS and the processed signal TS are in the opposite phase. In short, in the determination of whether or not the signal IS and the processed signal TS are in phase, it IS determined whether or not the signs of both are identical. When it IS determined that the signal IS and the processed signal TS are in phase, the output unit 2 compares the absolute value |u1| of the signal IS with the absolute value |u2| of the processed signal TS, and uses a signal having a smaller absolute value as the output signal OS. Thus, the output unit 2 selects the processed signal TS to output the value U2 of the processed signal TS as the value of the output signal OS when |u1|μΜ or |u2|, and selects the signal IS to output the value U1 of the signal IS as the value of the output signal OS when |u1| < |u2|. In contrast, when it IS determined that the signal IS and the processed signal TS are in the opposite phase, the output unit 2 outputs 0 as the value of the output signal OS.

In this way, when the signal processing device S1 processes the signal IS and outputs the output signal OS, as shown by the solid line in fig. 3, the output signal OS becomes a signal having an in-phase waveform without a phase shift from the signal IS shown by the broken line in fig. 3. Thus, the output signal OS IS output as a signal having no phase shift with respect to the original signal IS output from the acceleration sensor a. Therefore, in the control device using the output signal OS processed by the signal processing device S1, the phase margin can be ensured at the time of performing control, and the control is not unstable even if the control gain is set to be high, so that the control performance is improved.

In addition, as described above, the filter 1 is set as a high-pass filter, but a low-pass filter may be used. When the filter 1 IS set as a low-pass filter, the processed signal TS IS phase-delayed with respect to the signal IS. In this case, if the signal IS and the processed signal TS are in phase, the signal having the smaller absolute value of the signal IS and the absolute value of the processed signal TS IS used as the output signal OS, and if the signal IS and the processed signal TS are in opposite phase, the output IS set to 0, so that the phase shift between the signal IS and the output signal OS can be prevented.

As described above, the signal IS a waveform that vibrates with 0 as the amplitude center, but the amplitude center value may not be 0. In this case, the following configuration is sufficient.

First, if the signal processing device S1 performs the high-pass filtering processing on the signal IS to vibrate around the amplitude center value α other than 0 of the signal IS, the signal TS after processing loses the information of the amplitude center value α when the signal IS processed by the filter 1, and becomes a waveform having the amplitude center of 0. In this case, the offset value IS set as the amplitude center value α, the signal IS offset, the offset signal IS converted into a waveform having 0 as the amplitude center, the offset signal IS and the processed signal TS are compared, and it IS determined whether the signals are in phase or not, and the processing as described above IS performed.

In contrast, when the filter 1 IS a low-pass filter and the signal processing device S1 performs the low-pass filtering process on the signal IS, it IS sufficient to determine whether or not the signal IS and the processed signal TS are in phase with respect to the amplitude center value α. Therefore, as shown in fig. 4, when the signal IS a waveform that vibrates about the amplitude center value α that IS offset from 0, the processed signal TS after the low-pass filtering processing also vibrates about the amplitude center value α. Thus, the amplitude center value α IS set as a bias value, and the signal IS and the processed signal TS are biased by the bias value α, and it IS sufficient to determine whether or not the signals are in phase.

Specifically, assume that the values of the signal IS and the processed signal TS are U1 and U2, respectively, and the value of the offset signal IS U1 _off The value of the offset processed signal TS is set to U2 _off Then the output unit 2 calculates U1 _off ＝U1-α、U2 _off =u2- α. The output unit 2 performs the above-described operation to offset the signal IS and the processed signal TS by the offset value α, thereby obtaining the value U1 of the offset signal IS _off And the value U2 of the offset processed signal TS _off 。

Then, the output unit 2 outputs the value U1 of the offset signal IS _off And the value U2 of the offset processed signal TS _off The comparison IS performed to determine if the signal IS and the processed signal TS are in phase in the manner described above. The output unit 2 uses the value U1 of the offset signal IS _off And the value U2 of the offset processed signal TS _off The resulting values are multiplied to determine if they are in phase. If the value U1 of the offset signal IS _off And the value U2 of the offset processed signal TS _off Multiplication resultThe value of (1) is 0 or more, i.e. if U1 _off ×U2 _off If not less than 0, the output unit 2 determines that the signal IS and the processed signal TS are in phase. Conversely, if the value U1 of the biased signal IS _off And the value U2 of the offset processed signal TS _off The value obtained by multiplication is less than 0, i.e. if U1 _off ×U2 _off If < 0, the output unit 2 determines that the signal IS and the processed signal TS are in the opposite phase.

Then, when the output unit 2 determines that the signal IS and the processed signal TS are in phase, the absolute value |u1 of the offset signal IS _off Absolute value of the post-offset processed signal TS U2 _off The comparison takes place using a signal with a smaller absolute value, which is taken as the output signal OS. Thus, the output unit 2 outputs |u1 _off |≥|U2 _off When the value of the output signal OS is equal to the value of the processed signal TS, U2, is selected, and the value is equal to the value of the output signal OS, at |U1 _off |＜|U2 _off When i IS selected, the value U1 of the signal IS outputted as the value of the output signal OS. In contrast, when it IS determined that the signal IS and the processed signal TS are in the opposite phase, the output unit 2 outputs the offset value α as the value of the output signal OS.

In this way, when the signal IS processed and the output signal OS IS outputted, the signal processing device S1 outputs a signal having a waveform with the same phase, without shifting the phase of the output signal OS with respect to the signal IS, as shown in fig. 5. In this way, when the signal IS a waveform that vibrates with a value other than 0 as the amplitude center value, the signal processing device S1 compares the offset signal IS with the offset processed signal TS with the amplitude center value as the offset value α, determines whether or not the signals are in phase, and generates the output signal OS. In this way, even if the signal IS a waveform that vibrates with a value other than 0 as the amplitude center value, the signal processing device S1 can output the output signal OS in phase with the signal IS. In addition, in the case where the amplitude center value IS 0, the offset value α IS set to 0, so that the signal processing device S1 performing the offset processing can also cope with the processing in which the signal IS a waveform having the amplitude center of 0.

Thus, even if the signal IS a waveform that vibrates with a value other than 0 as the amplitude center value, the output signal OS can be output as a signal that IS not shifted in phase from the original signal IS output by the acceleration sensor a. Therefore, in the control device using the output signal OS processed by the signal processing device S1, the phase margin can be ensured at the time of performing control, and the control is not unstable even if the control gain is set to be high, so that the control performance is improved.

As described above, the larger the phase shift between the signal IS and the processed signal TS, the shorter the time the signal IS and the processed signal TS take the same phase, and therefore the waveform of the processed signal TS tends to be dissimilar to the waveform of the signal IS. Thus, if the filter 1 IS a first-order low-pass filter or a first-order high-pass filter, the phase shift between the signal IS and the processed signal TS becomes smaller than in the case of using a high-order low-pass filter or a high-pass filter, and the distortion of the output signal OS can be reduced.

< second embodiment >

As shown in fig. 6, a signal processing device S2 according to the second embodiment includes: a low pass filter 3 and an output 4. In this example, the signal processing device S2 uses the low-pass filter 3 to perform processing of extracting the high-frequency component contained in the original signal IS.

In this example, the low-pass filter 3 performs a low-pass filtering process on the signal IS output from the acceleration sensor a as an original signal, and outputs a processed signal TS. The processed signal TS is input to the output unit 4. The processed signal TS IS input to the output unit 4 as well as the signal IS. The low-pass filter 3 may be set as an analog filter or a filter implemented by the arithmetic processing device through execution of software. The cut-off frequency of the low-pass filter 3 may be set so as to be suitable for extracting components in a frequency band required by the control device of the output signal OS outputted by the signal processing device S2. As shown in fig. 7, the processed signal TS processed by the low-pass filter 3 becomes a signal of a waveform (a broken line in fig. 7) phase-delayed from the signal IS shown by a solid line in fig. 7.

The output unit 4 outputs the output signal OS based on the phase of the signal IS and the processed signal TS processed by the low-pass filter 3. In this example, the output unit 4 is configured to include: an insensitive area amount calculating unit 41 that obtains an insensitive area amount based on the signal IS and the processed signal TS; and a signal processing unit 42 that outputs the output signal OS based on the signal IS and the dead zone amount obtained by the dead zone amount calculation unit 41.

Assuming that the value of the signal IS U1 and the value of the processed signal TS IS Uref, the dead zone amount calculation unit 41 sets the positive dead zone amount Dp to Uref if Uref > 0 and sets the positive dead zone amount Dp to 0 if Uref IS equal to or less than 0, provided that U1 > 0. The positive dead zone amount Dp IS the dead zone amount used in the case where the value U1 of the signal IS positive. The dead zone amount calculation unit 41 sets the negative dead zone amount Dm to Uref if Uref < 0 and sets the negative dead zone amount Dm to 0 if Uref is equal to or greater than 0, provided that U1 < 0. The negative dead zone amount Dm IS an dead zone amount used in the case where the value U1 of the signal IS negative.

The signal processing unit 42 calculates u=u1 to Dp to obtain the value U of the output signal OS when the value U1 of the signal IS exceeds 0 and the value U1 of the signal IS exceeds the positive dead zone amount Dp, that IS, when U1 > 0 and U1 > Dp. The positive dead zone Dp in this case is 0 when Uref is equal to or less than 0; in case Uref > 0, the value Uref of the processed signal TS is the value Uref. Thus, when the signal IS exceeds 0 and the signal IS and the processed signal TS are in opposite phases, the signal processing unit 42 sets the signal IS as the output signal OS. In addition, in the case where the signal IS exceeds 0, the signal IS and the processed signal TS are in phase, and the signal IS exceeds the processed signal TS, the signal processing section 42 removes the processed signal TS from the signal IS to generate the output signal OS. That IS, when U1 > 0 and Uref IS equal to or less than 0, the signal processing unit 42 uses the signal IS as the output signal OS; in the case where U1 > 0, uref > 0, and U1 > Uref, the processed signal TS IS removed from the signal IS to generate the output signal OS.

The signal processing unit 42 sets the value U of the output signal OS to 0 when the value U1 of the signal IS exceeds 0, the value Uref of the processed signal TS exceeds 0, and the value U1 of the signal IS equal to or less than the dead zone Dp, that IS, when U1 > 0, uref > 0, and U1 IS equal to or less than Dp. The positive dead zone amount Dp in this case is the value Uref of the processed signal TS. Thus, when the value U1 of the signal IS exceeds 0, the processed signal TS exceeds 0, and the signal IS equal to or less than the processed signal TS, that IS, when U1 > 0, uref > 0, and U1. Ltoreq.uref, the signal processing unit 42 takes 0 as the output signal OS.

In the above case, the signal processing unit 42 uses the positive dead zone amount Dp when the signal IS positive, and uses a signal obtained by removing the positive dead zone amount Dp from the signal IS as the output signal OS when the signal IS greater than the positive dead zone amount Dp. In addition, when the signal IS positive and the value Uref of the processed signal TS IS positive, the signal processing unit 42 takes 0 as the output signal OS because the signal IS in the dead band when the signal IS smaller than the positive dead band amount Dp.

Further, the signal processing unit 42 calculates u=u1-Dm to obtain the value U of the output signal OS when the value U1 of the signal IS smaller than 0 and the value U1 of the signal IS smaller than the negative dead zone amount Dm, that IS, when U1 < 0 and U1 < Dm. The negative dead zone amount Dp in this case is 0 when Uref. Gtoreq.0; when Uref < 0, the value Uref of the processed signal TS is the value Uref. Thus, when the signal IS less than 0 and the signal IS and the processed signal TS are in the opposite phase, the signal processing unit 42 takes the signal IS as the output signal OS. And, in the case where the signal IS less than 0, the signal IS and the processed signal TS are in phase, and the signal IS less than the processed signal TS, the signal processing section 42 removes the processed signal TS from the signal IS to generate the output signal OS. That IS, when U1 < 0 and Uref IS not less than 0, the signal processing unit 42 uses the signal IS as the output signal OS; in the case of U1 < 0, U1 < 0 and U1 < Uref, the processed signal TS IS removed from the signal IS to generate the output signal OS.

The signal processing unit 42 sets the value U of the output signal OS to 0 when the value U1 of the signal IS smaller than 0, the value Uref of the processed signal TS IS smaller than 0, and the value U1 of the signal IS equal to or larger than the negative dead zone amount Dm, that IS, when U1 < 0, uref < 0, and U1 IS equal to or larger than Dm. The negative dead zone amount Dm in this case is the value Uref of the processed signal TS. Thus, when the value U1 of the signal IS less than 0, the processed signal TS IS less than 0, and the signal IS equal to or greater than the processed signal TS, that IS, when U1 < 0, uref < 0, and U1 IS equal to or greater than Uref, the signal processing unit 42 takes 0 as the output signal OS.

As described above, when the signal IS negative, the signal processing unit 42 uses the negative dead zone amount Dm; in the case where the signal IS smaller than the negative dead zone amount Dm, a signal obtained by removing the negative dead zone amount Dm from the signal IS taken as the output signal OS. In addition, when the signal IS negative and the value Uref of the processed signal TS IS negative, the signal processing unit 42 takes 0 as the output signal OS because the signal IS in the dead band when the signal IS greater than the negative dead band amount Dm.

As described above, the signal processing unit 42 sets the signal IS as the output signal OS when the signal IS and the processed signal TS are in the opposite phase. In addition, the signal processing unit 42 takes, as the output signal OS, a signal obtained by removing the processed signal TS from the signal IS when the signal IS and the processed signal TS are in phase and the absolute value of the signal IS exceeds the absolute value of the processed signal TS. Further, the signal processing unit 42 sets 0 as the output signal OS when the signal IS and the processed signal TS are in phase and the absolute value of the signal IS equal to or less than the absolute value of the processed signal TS.

In this way, when the signal processing device S2 processes the signal IS and generates the output signal OS, the output signal OS IS output as a signal of the waveform shown in fig. 8. As shown in fig. 8, the output signal OS becomes the signal IS when the signal IS and the processed signal TS are in opposite phases, and becomes a signal obtained by removing the processed signal TS after the low-pass filtering process from the signal IS when the conditions are the same as those described above, and thus becomes a signal of a waveform of a high-frequency component contained in the signal IS. When the signal IS and the processed signal TS are in the opposite phase, the output signal OS becomes the signal IS; when the signal IS and the processed signal TS are in phase and the absolute value of the signal IS smaller than the absolute value of the processed signal TS, the signal IS 0, and thus the signal IS prevented from being in the opposite phase to the signal IS.

Thus, when the signal IS processed and the output signal OS IS generated, the signal processing device S2 obtains the output signal OS which IS a high-frequency component contained in the signal IS and IS in phase with the signal IS. Therefore, the signal processing device S2 can perform processing of extracting a high frequency component from the original signal IS output from the acceleration sensor a, and can output the output signal OS without a phase shift. Therefore, in the control device using the output signal OS processed by the signal processing device S2, the phase margin can be ensured at the time of performing control, and the control is not unstable even if the control gain is set to be high, so that the control performance is improved.

< third embodiment >

As shown in fig. 9, a signal processing device S3 according to a third embodiment includes: a high pass filter 5 and an output 6. In this example, the signal processing means S3 performs a high-pass filtering process on the original signal IS.

In this example, the high-pass filter 5 performs a high-pass filtering process on the signal IS output from the acceleration sensor a as the original signal, and outputs the processed signal TS. The processed signal TS is input to the output unit 6. The processed signal TS IS input to the output unit 6 as well as the signal IS. The high-pass filter 5 may be set as an analog filter or a filter implemented by the arithmetic processing device through execution of software. The cut-off frequency of the high-pass filter 5 may be set so as to be suitable for extracting components of a frequency band required by the control device of the output signal OS outputted by the signal processing device S3. As shown in fig. 2, the processed signal TS processed by the high-pass filter 5 becomes a signal of a waveform (a broken line in fig. 2) whose phase IS advanced with respect to the signal IS shown by the solid line in fig. 2.

The output unit 6 outputs the output signal OS based on the phase of the signal IS and the processed signal TS processed by the high-pass filter 5. In this example, the output unit 6 is configured to include: a saturation upper limit value calculation unit 61 that obtains a saturation upper limit value based on the signal IS and the processed signal TS; and a signal processing unit 62 that generates an output signal OS based on the signal IS and the saturation upper limit value obtained by the saturation upper limit value calculating unit 61.

Assuming that the value of the signal IS U1 and the value of the processed signal TS IS Uref, the saturation upper limit value calculation unit 61 sets the positive saturation upper limit value Lp to Uref if Uref > 0, provided that U1 > 0; when Uref is equal to or less than 0, the positive saturation upper limit Lp is set to 0. The positive saturation upper limit value Lp IS a saturation upper limit value used when the value U1 of the signal IS positive. The saturation upper limit value calculation unit 61 sets the negative saturation upper limit value Lm to Uref when Uref < 0, on the condition that U1 < 0; when Uref is not less than 0, the negative saturation upper limit Lm is set to 0. The negative saturation upper limit Lm IS a saturation upper limit used when the value U1 of the signal IS negative.

The signal processing unit 62 takes the signal IS as the output signal OS when the signal IS exceeds 0, the value Uref of the processed signal TS exceeds 0, and the value U1 of the signal IS equal to or less than the positive saturation upper limit value Lp, that IS, when U1 > 0, uref > 0, and U1+.lp. The positive saturation upper limit value Lp in this case is the value Uref of the processed signal TS. Thus, when the signal IS exceeds 0, the processed signal TS exceeds 0, and the signal IS equal to or less than the processed signal TS, that IS, when U1 > 0, uref > 0, and U1+.uref, the signal processor 62 takes the signal IS as the output signal OS.

The signal processing unit 62 sets the value U of the output signal OS to the positive saturation upper limit value Lp when the signal IS exceeds 0, the value Uref of the processed signal TS exceeds 0, and the value U1 of the signal IS exceeds the positive saturation upper limit value Lp, that IS, when Uref > 0 and U1 > Lp. Since the positive saturation upper limit value Lp in this case IS the value Uref of the processed signal TS, the signal processing unit 62 sets the processed signal TS to the output signal OS when the processed signal TS exceeds 0 and the signal IS exceeds the processed signal TS. That is, the signal processing unit 62 uses the processed signal TS as the output signal OS when U1 > 0, uref > 0, and U1 > Uref.

Further, the signal processing unit 62 sets the output signal OS to the positive saturation upper limit value Lp when the value U1 of the signal IS exceeds 0, the value Uref of the processed signal TS IS less than 0, and the value U1 of the signal IS exceeds the positive saturation upper limit value Lp, that IS, when U1 > 0, uref IS equal to or less than 0, and U1 > Lp. The positive saturation upper limit Lp in this case is 0 when Uref is equal to or less than 0. Thus, when the signal IS exceeds 0 and the signal IS and the processed signal TS are in opposite phases, the signal processing unit 62 sets the output signal OS to 0. That is, the signal processing unit 62 sets the output signal OS to 0 when U1 > 0 and Uref is equal to or smaller than 0.

In the above case, the signal processing unit 62 uses the positive saturation upper limit value Lp when the signal IS positive, uses the signal IS as the output signal OS when the signal IS equal to or lower than the positive saturation upper limit value Lp, and uses the positive saturation upper limit value Lp as the output signal OS when the signal IS greater than the positive saturation upper limit value Lp.

Further, the signal processing unit 62 sets the signal IS as the output signal OS when the signal IS less than 0, the value Uref of the processed signal TS IS less than 0, and the value U1 of the signal IS equal to or greater than the negative saturation upper limit Lm, that IS, when U1 < 0, uref < 0, and U1 IS equal to or greater than Lm. The negative saturation upper limit Lm in this case is the value Uref of the processed signal TS. Thus, when the signal IS less than 0, the processed signal TS IS less than 0, and the signal IS equal to or greater than the processed signal TS, that IS, when U1 < 0, uref < 0, and U1 IS equal to or greater than Uref, the signal processing unit 62 takes the signal IS as the output signal OS.

The signal processing unit 62 sets the value U of the output signal OS to the negative saturation upper limit value Lm when the signal IS smaller than 0, the value Uref of the processed signal TS IS smaller than 0, and the value U1 of the signal IS smaller than the negative saturation upper limit value Lm, that IS, when U1 < 0, uref < 0, and U1 < Lm. The negative saturation upper limit value Lp in this case is the value Uref of the processed signal TS. Thus, when the signal IS less than 0, the processed signal TS IS less than 0, and the signal IS less than the processed signal TS, the signal processing section 62 takes the processed signal TS as the output signal OS. That IS, the signal processing unit 62 takes the signal IS as the output signal OS when U1 < 0, uref < 0, and U1 < Uref.

Further, the signal processing unit 62 sets the output signal OS to the negative saturation upper limit value Lm when the value U1 of the signal IS less than 0, the value Uref of the processed signal TS IS 0 or more, and the value U1 of the signal IS less than the negative saturation upper limit value Lm, that IS, when U1 < 0, uref IS equal to or greater than 0, and U1 < Lp. The negative saturation upper limit Lm in this case is 0 when Uref is equal to or greater than 0. Thus, when the signal IS less than 0 and the signal IS and the processed signal TS are in the opposite phase, the signal processing unit 62 sets the output signal OS to 0. That is, the signal processing unit 62 sets the output signal OS to 0 when U1 < 0 and Uref is equal to or greater than 0.

As described above, the signal processing unit 62 takes the signal IS as the output signal OS when the signal IS and the processed signal TS are in phase and the absolute value of the signal IS equal to or less than the absolute value of the processed signal TS. The signal processing unit 62 uses the processed signal TS as the output signal OS when the signal IS and the processed signal TS are in phase and the absolute value of the signal IS exceeds the absolute value of the processed signal TS. Further, the signal processing unit 62 sets 0 as the output signal OS when the signal IS and the processed signal TS are in the opposite phase.

In this way, when the signal processing device S3 processes the signal IS and generates the output signal OS, the output signal OS IS output as a signal of the waveform shown in fig. 10. As shown in fig. 10, the output signal OS IS a signal having an in-phase waveform without a phase shift with respect to the signal IS. Thus, the output signal OS IS output as a signal that IS not phase-shifted with respect to the original signal IS output by the acceleration sensor a. Thus, the signal processing device S3 can perform high-pass filtering processing on the original signal IS output from the acceleration sensor a, and can output the output signal OS without phase shift. Therefore, in the control device using the output signal OS processed by the signal processing device S3, the phase margin can be ensured at the time of performing control, and the control is not unstable even if the control gain is set to be high, so that the control performance is improved.

In this example, the signal processing devices S1, S2, S3 process the signal IS output from the acceleration sensor a, but the original signal IS not limited to this, and signals other than the sensor may be processed.

While the preferred embodiments of the present invention have been described in detail, modifications, variations and alterations can be made without departing from the scope of the claims.

The present application claims priority to japanese patent application 2017-014307, filed on the japanese franchise on 1 month 30 of 2017, and the entire contents of this application are incorporated herein by reference.

Claims

1. A signal processing device is characterized by comprising:

a filter that filters a signal; and

an output unit that outputs an output signal based on the phase of the signal and the processed signal obtained by processing the signal by the filter;

the filter is a high-pass filter,

the output unit biases the signal by a bias value with an amplitude center value of the signal as a bias value, and when the signal after the bias and the signal after the processing are in phase, uses a signal having a smaller value of the absolute value of the signal after the bias and the absolute value of the signal after the processing as an output signal,

and when the offset signal and the processed signal are in the opposite phase, taking 0 as an output signal.

2. A signal processing device is characterized by comprising:

a filter that filters a signal; and

the filter is a low-pass filter,

the output unit biases the signal and the processed signal by using an amplitude center value of the signal as a bias value, and when the biased signal and the biased processed signal are in phase, uses a signal having a smaller value out of an absolute value of the biased signal and an absolute value of the biased processed signal as an output signal,

and when the offset signal and the offset processed signal are in the opposite phase, taking the offset value as an output signal.

3. A signal processing device is characterized by comprising:

a filter that filters a signal; and

the filter is a low-pass filter,

the output unit uses the signal as an output signal when the signal and the processed signal are in opposite phases,

in the case where the signal and the processed signal are in phase and the absolute value of the signal exceeds the absolute value of the processed signal, subtracting the processed signal from the signal to generate the output signal,

and when the signal and the processed signal are in phase and the absolute value of the signal is less than or equal to the absolute value of the processed signal, 0 is taken as an output signal.

4. A signal processing device is characterized by comprising:

a filter that filters a signal; and

the filter is a high-pass filter,

the output section takes the signal as an output signal in a case where the signal and the processed signal are in phase and an absolute value of the signal is equal to or less than an absolute value of the processed signal,

in the case where the signal and the processed signal are in phase and the absolute value of the signal exceeds the absolute value of the processed signal, the processed signal is taken as an output signal,

and when the signal and the processed signal are in opposite phases, taking 0 as an output signal.

5. The signal processing device according to any one of claims 1 to 4, wherein,

the filter is a first order low pass filter or a first order high pass filter.