CN110199475B - signal processing device - Google Patents

Abstract

The invention discloses a signal processing device capable of eliminating the phase shift of an output signal for a signal. Therefore, the signal processing device of the present invention is constituted to include: a filter (1), which filters the signal (IS); and an output unit (2), which is based on the signal (IS) and processed by the filter (1). After the phase of the processed signal (TS), the output signal (OS) is output.

Description

signal processing device

technical field

The invention relates to a signal processing device.

Background technique

Such a signal processing device is used, for example, in a control device or the like, and processes a signal output from a sensor to input it to the control device. Signal processing devices remove noise contained in sensor output and extract only frequency band components required for control devices from sensor output signals, so they are widely used in various equipment.

For example, taking the case of applying to a shock absorber for railway vehicles as an example, as disclosed in JP2013-1304A, the signal processing device is set as a band-pass filter. Specifically, the signal processing device is used to process the signal output by the acceleration sensor, remove noise and stable acceleration components during curve driving, and only extract vibration components in frequency bands that deteriorate the ride comfort of the vehicle.

In this way, although the signal processing device is used to extract only desired components from various signals, the phase of the output signal obtained by processing the signal is always shifted relative to the original signal.

Thus, in a control system using an output signal processed by a signal processing device, if the control gain is increased, the system becomes unstable, and therefore there is a limit to improving the control performance.

Also, if the order of the filter is increased, the gain attenuation rate becomes better, but the problem cannot be solved because the phase angle increases.

Contents of the invention

Therefore, an object of the present invention is to provide a signal processing device capable of eliminating phase shift.

Since the signal processing device of the present invention includes: a filter for filtering a signal; and an output unit for outputting an output signal based on the phase of the signal and the processed signal processed by the filter, it is possible to obtain a relative The output signal without the phase shift of the original signal.

Description of drawings

FIG. 1 is a diagram showing the configuration of a signal processing device in the first embodiment.

FIG. 2 is a diagram showing waveforms of an original signal and a high-pass filter-processed signal.

3 is a diagram showing a waveform of an output signal output when an original signal is processed by the signal processing device in the first embodiment.

FIG. 4 is a diagram showing a waveform of an original signal whose amplitude central value is not zero.

5 is a diagram showing a waveform of an output signal output when the signal processing device in the first embodiment processes an original signal whose amplitude center value is not zero.

FIG. 6 is a diagram showing the configuration of a signal processing device in a second embodiment.

FIG. 7 is a diagram showing waveforms of an original signal and a low-pass filtered signal.

8 is a diagram showing a waveform of an output signal output when the signal processing device in the second embodiment processes the original signal.

FIG. 9 is a diagram showing the configuration of a signal processing device in a third embodiment.

10 is a diagram showing a waveform of an output signal output when the signal processing device in the third embodiment processes the original signal.

Detailed ways

<First Embodiment>

Hereinafter, the present invention will be described based on the illustrated embodiments. As shown in FIG. 1 , a signal processing device S1 according to the first embodiment includes a filter 1 and an output unit 2 . In this example, the signal processing device S1 performs high-pass filter processing on the original signal IS.

The filter 1 is set as a high-pass filter. In this example, the signal IS output by the acceleration sensor A is used as an original signal, and the signal IS is subjected to high-pass filter processing to output a processed signal TS. The processed signal TS is input to the output unit 2 . The signal IS is directly input to the output unit 2 in addition to the processed signal TS. In addition, the filter 1 may be set as an analog filter, or may be set as a filter realized by execution of software by an arithmetic processing device. The cutoff frequency of the filter 1 may be set so as to be suitable for extracting components in a frequency band required by the control device of the output signal OS output by the signal processing device S1.

The output unit 2 outputs the output signal OS based on the phase of the signal IS and the processed signal TS processed by the filter 1 . First, for easy understanding, a process in which the output unit 2 outputs the output signal OS will be described by taking the case where the signal IS is a waveform that vibrates around 0 and the center value of the amplitude is 0 as an example. Next, in order to normalize the output process of the output signal OS by the output unit 2 , the output process of the output signal OS when the signal IS is a waveform that vibrates around the amplitude center value α will be described.

As shown in Figure 2, if the signal IS is the signal shown by the solid line in Figure 2 vibrating around 0, then when the high-pass filtering process is performed by the filter 1, as shown by the dotted line in Figure 2, the processed signal TS As the amplitude decays, the phase advances.

The output unit 2 compares the signal IS and the processed signal TS to determine whether they are in phase or out of phase. The case where the signal IS and the processed signal TS are in the same phase refers to the case where both the signal IS and the processed signal TS are equal to or greater than 0 and are within the range above the time axis in FIG. Refers to the situation where both the signal IS and the processed signal TS are less than 0 and are within the range below the time axis in FIG. 2 . The case where the signal IS and the processed signal TS are in opposite phases means that one of the signal IS and the processed signal TS is in the range above the time axis in FIG. The other one of the signals TS is less than 0 and is in the case of the range below the time axis in FIG. 2 .

The fact that the signal IS and the processed signal TS are in the same phase means that even if the processed signal TS output by the filter 1 is used as the output signal OS, the output signal OS will not become a signal with an opposite phase to the signal IS, but the signal IS When the phase is opposite to that of the processed signal TS, the output signal OS is a signal whose phase is opposite to that of the signal IS.

Therefore, when the signal IS and the processed signal TS are in opposite phases, the output unit 2 outputs 0 as the output signal OS. In addition, when the signal IS and the processed signal TS are in the same phase, the absolute value of the signal IS is always compared with the absolute value of the processed signal TS, and the signal with a smaller absolute value is selected as the output signal OS. output.

More specifically, the output unit 2 uses a value obtained by multiplying the value U1 of the signal IS and the value U2 of the processed signal TS to determine whether the signal IS and the processed signal TS are in phase or out of phase. If the value obtained by multiplying the value U1 of the signal IS by the value U2 of the processed signal TS is 0 or more, that is, if U1×U2≧0, the output unit 2 determines that the signal IS and the processed signal TS are in phase. On the contrary, if the value obtained by multiplying the value U1 of the signal IS and the value U2 of the processed signal TS is less than 0, that is, if U1×U2<0, the output unit 2 determines that the signal IS and the processed signal TS are in opposite phases. In short, in determining whether or not the signal IS and the processed signal TS are in phase, it is determined whether or not the signs of the two match. Furthermore, when the output unit 2 determines that the signal IS and the processed signal TS are in the same phase, it compares the absolute value |U1| of the signal IS with the absolute value |U2| The value of the signal, the signal as the output signal OS. Thus, the output unit 2 selects the processed signal TS when |U1|≥|U2|, outputs the value U2 of the processed signal TS as the value of the output signal OS, and selects the signal OS when |U1|<|U2| IS outputs the value U1 of the signal IS as the value of the output signal OS. On the other hand, when the output unit 2 determines that the signal IS and the processed signal TS are in opposite phases, it outputs 0 as the value of the output signal OS.

In this way, when the signal processing device S1 processes the signal IS and outputs the output signal OS, as shown by the solid line in FIG. become a signal with the same phase waveform. Thus, the output signal OS is output as a signal with no phase shift with respect to the original signal IS output from the acceleration sensor A. As shown in FIG. Therefore, in the control device using the output signal OS processed by the signal processing device S1, the phase margin can be ensured when the control is executed, and the control will not be unstable even if the control gain is set high. Therefore, the control performance is improved.

In addition, as described above, the filter 1 is set as a high-pass filter, but a low-pass filter may also be used. When the filter 1 is set as a low-pass filter, the processed signal TS is phase-lag with respect to the signal IS. In this case, as long as the signal IS and the processed signal TS are in the same phase, the signal with the smaller absolute value of the absolute value of the signal IS and the processed signal TS is used as the output signal OS. In the case of inverse phase, setting the output to 0 can prevent the phase shift between the signal IS and the output signal OS.

In addition, as described above, the signal IS is a signal of a waveform that vibrates with the amplitude centered at 0, but there are cases where the amplitude center value is not 0. In this case, it is only necessary to set as follows.

First, assuming that when the signal processing device S1 performs high-pass filter processing on the signal IS, the vibration is centered on the amplitude center value α other than 0 of the signal IS, then when the signal IS is processed by the filter 1, the processed The signal TS loses the information of the amplitude center value α, and becomes a waveform whose amplitude center is 0. Therefore, in this case, as long as the offset value is used as the amplitude center value α, the signal IS is offset, and the offset signal IS is converted into a waveform whose amplitude center is 0, and the offset signal IS Compare it with the processed signal TS to determine whether it is in phase and perform the processing as described above.

In contrast, when the filter 1 is set as a low-pass filter and the signal processing device S1 performs low-pass filter processing on the signal IS, it is only necessary to judge the signal IS and the processed signal TS based on the amplitude central value α. Whether it is the same phase or not. Therefore, as shown in FIG. 4 , when the signal IS is a waveform that vibrates around an amplitude center value α deviated from 0, the processed signal TS after low-pass filtering is also centered on an amplitude center value α Vibrate at the center. Therefore, it is only necessary to use the amplitude center value α as an offset value, offset the signal IS and the processed signal TS by the offset value α, and determine whether or not they are in phase.

Specifically, assume that the values of the signal IS and the processed signal TS are respectively U1 and U2, the value of the biased signal IS is U1 _off , and the value of the biased processed signal TS is U2 _off , then the output unit 2 calculates U1 _off =U1-α, U2 _off =U2-α. The output unit 2 implements the aforementioned calculations to offset the signal IS and the processed signal TS with the offset value α, thereby obtaining the value U1 _off of the offset signal IS and the value U2 _off of the offset processed signal TS .

Then, the output unit 2 compares the value U1 _off of the offset signal IS with the value U2 _off of the offset processed signal TS, and determines whether the signal IS and the processed signal TS have the same phase as described above. The output unit 2 determines whether or not they are in-phase using a value obtained by multiplying the value U1 _off of the offset signal IS by the value U2 _off of the offset processed signal TS. If the value obtained by multiplying the value U1 _off of the biased signal IS by the value U2 _off of the biased processed signal TS is 0 or more, that is, if U1 _off × U2 _off ≥ 0, the output unit 2 determines that it is a signal IS and the processed signal TS are in phase. Conversely, if the value obtained by multiplying the value U1 _off of the biased signal IS by the value U2 _off of the biased processed signal TS is less than 0, that is, if U1 _off × U2 _off <0, the output unit 2 determines that The signal IS and the processed signal TS are in opposite phases.

Then, when the output unit 2 determines that the signal IS and the processed signal TS have the same phase, the absolute value |U1 _off | of the offset signal IS and the absolute value |U2 _off | of the offset processed signal TS For comparison, a signal having a smaller absolute value is used as the output signal OS. Thus, the output unit 2 selects the processed signal TS when |U1 _off |≥|U2 _off |, and outputs the value U2 of the processed signal TS as the value of the output signal OS, and when |U1 _off |<|U2 _off | When , the signal IS is selected, and the value U1 of the signal IS is output as the value of the output signal OS. On the other hand, when the output unit 2 determines that the signal IS and the processed signal TS are in opposite phases, it outputs the offset value α as the value of the output signal OS.

In this way, when the signal processing device S1 processes the signal IS and outputs the output signal OS, as shown in FIG. 5 , the output signal OS has no phase shift with respect to the signal IS, and becomes a signal having the same phase waveform. In this way, when the signal IS is a waveform in which the center value of the amplitude vibrates with a value other than 0, the signal processing device S1 uses the center value of the amplitude as the offset value α, and processes the biased signal IS and the biased After the signal TS is compared, it is judged whether they are in the same phase, and an output signal OS is generated. In this way, even if the signal IS is a waveform vibrating with a value other than 0 as the center value of the amplitude, the signal processing device S1 can output the output signal OS having the same phase as the signal IS. In addition, when the center value of the amplitude is 0, it is only necessary to set the offset value α to 0, so the signal processing device S1 that performs offset processing can also handle the processing in which the signal IS has an amplitude centered at 0. .

Therefore, even if the signal IS is a waveform in which the center value of the amplitude vibrates with a value other than 0, the output signal OS can be output as a signal with no phase shift with respect to the original signal IS output from the acceleration sensor A. Therefore, in the control device using the output signal OS processed by the signal processing device S1, the phase margin can be ensured when the control is executed, and the control will not be unstable even if the control gain is set high. Therefore, the control performance is improved.

As mentioned above, it can be seen that the greater the phase shift between the signal IS and the processed signal TS, the shorter the time for the signal IS and the processed signal TS to be in phase, so the waveform of the processed signal TS becomes the same as the signal IS The waveforms have a tendency not to approximate. Therefore, if the filter 1 is a first-order low-pass filter or a first-order high-pass filter, compared with the case of using a high-order low-pass filter or a high-pass filter, the difference between the signal IS and the processed signal TS The phase shift is reduced, and the distortion of the output signal OS can be reduced.

<Second Embodiment>

As shown in FIG. 6 , the signal processing device S2 of the second embodiment includes a low-pass filter 3 and an output unit 4 . In this example, the signal processing device S2 uses the low-pass filter 3 to perform processing for extracting high-frequency components contained in the original signal IS.

In this example, the low-pass filter 3 performs low-pass filter processing on the signal IS output by the acceleration sensor A as an original signal, and outputs a processed signal TS. The processed signal TS is input to the output unit 4 . The signal IS is directly input to the output unit 4 in addition to the processed signal TS. In addition, the low-pass filter 3 may be set as an analog filter, or may be set as a filter realized by execution of software by an arithmetic processing device. The cutoff frequency of the low-pass filter 3 may be set so as to be suitable for extracting components in a frequency band required by the control device of the output signal OS output by the signal processing device S2. As shown in FIG. 7 , the processed signal TS processed by the low-pass filter 3 is a signal of a waveform (dotted line in FIG. 7 ) whose phase is delayed with respect to the signal IS shown by the solid line in FIG. 7 .

The output unit 4 outputs the output signal OS based on the signal IS and the phase of the processed signal TS processed by the low-pass filter 3 . In this example, the output unit 4 is configured to include: a dead zone amount calculating unit 41 for calculating the dead zone amount based on the signal IS and the processed signal TS; and a signal processing unit 42 for calculating the dead zone amount based on the signal IS and The dead zone amount calculated by the sensitive zone amount computing unit 41 is output as an output signal OS.

Assuming that the value of the signal IS is U1, and the value of the processed signal TS is Uref, then the dead zone amount calculation unit 41 takes U1>0 as a condition, and in the case of Uref>0, the positive dead zone The amount Dp is Uref, and when Uref≦0, the positive dead zone amount Dp is set to zero. The positive deadband amount Dp is the deadband amount used when the value U1 of the signal IS is positive. In addition, the dead zone amount calculation unit 41 is based on the condition of U1<0, and in the case of Uref<0, the negative dead zone amount Dm is set to Uref, and in the case of Uref≥0, the negative dead zone amount Dm is set to Uref. The amount Dm is set to zero. The negative deadband amount Dm is the deadband amount used when the value U1 of the signal IS is negative.

The signal processing unit 42 calculates U=U1−Dp when the value U1 of the signal IS exceeds 0 and the value U1 of the signal IS exceeds the positive dead zone amount Dp, that is, when U1>0 and U1>Dp, To obtain the value U of the output signal OS. The positive dead zone amount Dp in this case is 0 when Uref≦0, and is the value Uref of the processed signal TS when Uref>0. Accordingly, when the signal IS exceeds 0 and the signal IS and the processed signal TS are in opposite phases, the signal processing unit 42 sets the signal IS as the output signal OS. Also, when the signal IS exceeds 0, the signal IS and the processed signal TS have the same phase, and the signal IS exceeds the processed signal TS, the signal processing unit 42 removes the processed signal TS from the signal IS to generate an output signal OS. That is, in the case of U1>0, Uref≤0, the signal processing unit 42 uses the signal IS as the output signal OS; in the case of U1>0, Uref>0, and U1>Uref, the processed signal is removed from the signal IS. TS to generate the output signal OS.

In addition, when the value U1 of the signal IS exceeds 0, the value Uref of the processed signal TS exceeds 0, and the value U1 of the signal IS is equal to or less than the positive dead zone amount Dp, that is, U1>0, Uref In the case of >0 and U1 ≤ Dp, the value U of the output signal OS is set to 0. The positive dead zone amount Dp in this case is the value Uref of the processed signal TS. Thus, when the value U1 of the signal IS exceeds 0, the processed signal TS exceeds 0, and the signal IS is equal to or smaller than the processed signal TS, that is, when U1>0, Uref>0, and U1≤Uref, the signal processing The section 42 uses 0 as the output signal OS.

Based on the above, when the signal IS is positive, the signal processing unit 42 adopts the positive dead zone amount Dp, and removes the positive dead zone amount Dp from the signal IS when the signal IS is greater than the positive dead zone amount Dp. The signal obtained by the sensitive area amount Dp is used as the output signal OS. In addition, when the signal IS is positive and the value Uref of the processed signal TS is positive, since the signal IS is located in the insensitive frequency band when the signal IS is smaller than the positive dead zone amount Dp, the signal processing unit 42 regards 0 as output signal OS.

Furthermore, the signal processing unit 42 calculates U=U1- Dm to obtain the value U of the output signal OS. In this case, the negative dead zone amount Dp is 0 when Uref≧0; and is the value Uref of the processed signal TS when Uref<0. Accordingly, when the signal IS is less than 0 and the signal IS and the processed signal TS are in opposite phases, the signal processing unit 42 outputs the signal IS as the output signal OS. Furthermore, when the signal IS is less than 0, the signal IS and the processed signal TS are in phase, and the signal IS is smaller than the processed signal TS, the signal processing unit 42 removes the processed signal TS from the signal IS to generate an output signal OS. That is, in the case of U1<0 and Uref≥0, the signal processing unit 42 uses the signal IS as the output signal OS; in the case of U1<0, Uref<0 and U1<Uref, the processed signal TS is removed from the signal IS. to generate the output signal OS.

In addition, when the value U1 of the signal IS is less than 0, the value Uref of the processed signal TS is less than 0, and the value U1 of the signal IS is greater than or equal to the negative dead zone amount Dm, that is, when U1<0, Uref In the case of <0 and U1≥Dm, the value U of the output signal OS is set to 0. The negative dead zone amount Dm in this case is the value Uref of the processed signal TS. Therefore, when the value U1 of the signal IS is less than 0, the processed signal TS is less than 0, and the signal IS is greater than or equal to the processed signal TS, that is, in the case of U1<0, Uref<0, and U1≥Uref, the signal processing The section 42 uses 0 as the output signal OS.

As can be seen from the above, when the signal IS is negative, the signal processing unit 42 adopts the negative dead zone amount Dm; when the signal IS is smaller than the negative dead zone amount Dm, the negative dead zone amount Dm is removed from the signal IS. The signal obtained by the sensitive area Dm is used as the output signal OS. In addition, when the signal IS is negative and the value Uref of the processed signal TS is negative, since the signal IS is located in the insensitive frequency band when the signal IS is greater than the negative dead zone amount Dm, the signal processing unit 42 regards 0 as output signal OS.

As can be seen from the above, when the signal IS and the processed signal TS are in opposite phases, the signal processing unit 42 uses the signal IS as the output signal OS. In addition, when the signal IS and the processed signal TS are in the same phase and the absolute value of the signal IS exceeds the absolute value of the processed signal TS, the signal processing unit 42 outputs a signal obtained by subtracting the processed signal TS from the signal IS. Signal OS. Furthermore, the signal processing unit 42 sets 0 as the output signal OS when the signal IS and the processed signal TS have the same phase and the absolute value of the signal IS is equal to or smaller than the absolute value of the processed signal TS.

In this way, when the signal processing device S2 processes the signal IS to generate the output signal OS, the output signal OS is output as a signal having a waveform as shown in FIG. 8 . As shown in Figure 8, when the signal IS and the processed signal TS are in opposite phases, the output signal OS becomes the signal IS. The signal obtained by processing the processed signal TS thus becomes a signal having a waveform of a high-frequency component contained in the signal IS. In addition, when the signal IS and the processed signal TS are in opposite phases, the output signal OS becomes the signal IS; when the signal IS and the processed signal TS are in the same phase and the absolute value of the signal IS is smaller than the absolute value of the processed signal TS In the case of , it becomes 0, so it is prevented from becoming a signal with an opposite phase to the signal IS.

Thus, when the signal processing device S2 processes the signal IS to generate the output signal OS, it obtains the output signal OS which is a high-frequency component contained in the signal IS and has the same phase as the signal IS. Therefore, the signal processing device S2 can perform a process of extracting high-frequency components from the raw signal IS output from the acceleration sensor A, and can output an output signal OS without a phase shift. Therefore, in the control device using the output signal OS processed by the signal processing device S2, the phase margin can be ensured when the control is executed, and the control will not be unstable even if the control gain is set high. Therefore, the control performance is improved.

<Third Embodiment>

As shown in FIG. 9 , the signal processing device S3 of the third embodiment includes a high-pass filter 5 and an output unit 6 . In this example, the signal processing device S3 performs high-pass filter processing on the original signal IS.

In this example, the high-pass filter 5 takes the signal IS output by the acceleration sensor A as an original signal, performs high-pass filter processing, and outputs a processed signal TS. The processed signal TS is input to the output unit 6 . The signal IS is directly input to the output unit 6 in addition to the processed signal TS. In addition, the high-pass filter 5 may be set as an analog filter, or may be set as a filter realized by execution of software by an arithmetic processing device. The cutoff frequency of the high-pass filter 5 may be set so as to be suitable for extracting components in a frequency band required by the control device of the output signal OS output by the signal processing device S3. As shown in FIG. 2 , the processed signal TS processed by the high-pass filter 5 is a signal having a waveform (dotted line in FIG. 2 ) phase-advanced with respect to the signal IS shown by the solid line in FIG. 2 .

The output unit 6 outputs the output signal OS based on the phase of the signal IS and the processed signal TS processed by the high-pass filter 5 . In this example, the output unit 6 is configured to include: a saturation upper limit calculation unit 61 for obtaining a saturation upper limit based on the signal IS and the processed signal TS; The upper limit calculation unit 61 calculates the saturated upper limit value to generate an output signal OS.

Assuming that the value of the signal IS is U1, and the value of the processed signal TS is Uref, then the saturation upper limit calculation unit 61 is based on the condition of U1>0, and in the case of Uref>0, the positive saturation upper limit The value Lp is set to Uref; in the case of Uref≦0, the positive saturation upper limit value Lp is set to 0. The positive saturation upper limit Lp is the saturation upper limit used when the value U1 of the signal IS is positive. In addition, the saturation upper limit calculation unit 61 is based on the condition of U1<0, and when Uref<0, sets the negative saturation upper limit Lm as Uref; when Uref≥0, sets the negative saturation upper limit The value Lm is set to 0. The negative saturation upper limit Lm is a saturation upper limit used when the value U1 of the signal IS is negative.

The signal processing unit 62 is when the signal IS exceeds 0, the value Uref of the processed signal TS exceeds 0, and the value U1 of the signal IS is equal to or less than the positive saturation upper limit value Lp, that is, when U1>0, Uref>0, and U1≤ In the case of Lp, the signal IS is used as the output signal OS. The positive saturation upper limit value Lp in this case is the value Uref of the processed signal TS. Thus, when the signal IS exceeds 0, the processed signal TS exceeds 0, and the signal IS is equal to or smaller than the processed signal TS, that is, when U1>0, Uref>0, and U1≤Uref, the signal processing unit 62 sets Signal IS serves as output signal OS.

In addition, when the signal IS exceeds 0, the value Uref of the processed signal TS exceeds 0, and the value U1 of the signal IS exceeds the positive saturation upper limit Lp, that is, when Uref>0 and U1>Lp Next, the value U of the output signal OS is set to a positive saturation upper limit value Lp. Since the positive saturation upper limit Lp in this case is the value Uref of the processed signal TS, when the processed signal TS exceeds 0 and the signal IS exceeds the processed signal TS, the signal processing unit 62 converts the processed signal TS to Set to output signal OS. That is, the signal processing unit 62 makes the processed signal TS the output signal OS when U1>0, Uref>0, and U1>Uref.

Furthermore, the signal processing unit 62 is when the value U1 of the signal IS exceeds 0, the value Uref of the processed signal TS is less than 0, and the value U1 of the signal IS exceeds the positive saturation upper limit value Lp, that is, U1>0, Uref≤ In the case of 0 and U1>Lp, the output signal OS is set to a positive saturation upper limit value Lp. The positive saturation upper limit Lp in this case is 0 when Uref≦0. Accordingly, when the signal IS exceeds 0 and the signal IS and the processed signal TS are in opposite phases, the signal processing unit 62 sets the output signal OS to 0. That is, the signal processing unit 62 sets the output signal OS to 0 when U1>0 and Uref≦0.

According to the above, when the signal IS is positive, the signal processing unit 62 adopts the positive saturation upper limit Lp, and when the signal IS is below the positive saturation upper limit Lp, the signal IS is used as the output signal OS, when the signal When IS is greater than the positive saturation upper limit Lp, the positive saturation upper limit Lp is used as the output signal OS.

Furthermore, when the signal IS is less than 0, the value Uref of the processed signal TS is less than 0, and the value U1 of the signal IS is greater than or equal to the negative saturation upper limit value Lm, that is, U1<0, Uref<0 and In the case of U1≧Lm, the signal IS is used as the output signal OS. The negative saturation upper limit value Lm in this case is the value Uref of the processed signal TS. Therefore, when the signal IS is less than 0, the processed signal TS is less than 0, and the signal IS is greater than or equal to the processed signal TS, that is, when U1<0, Uref<0, and U1≥Uref, the signal processing unit 62 converts the signal to IS as the output signal OS.

In addition, when the signal IS is less than 0, the value Uref of the processed signal TS is less than 0, and the value U1 of the signal IS is less than the negative saturation upper limit value Lm, that is, when U1<0, Uref<0 and When U1<Lm, the value U of the output signal OS is set to the negative saturation upper limit value Lm. The negative saturation upper limit value Lp in this case is the value Uref of the processed signal TS. Accordingly, when the signal IS is smaller than 0, the processed signal TS is smaller than 0, and the signal IS is smaller than the processed signal TS, the signal processing unit 62 outputs the processed signal TS as the output signal OS. That is, the signal processing unit 62 makes the signal IS the output signal OS when U1<0, Uref<0, and U1<Uref.

Furthermore, the signal processing unit 62 is when the value U1 of the signal IS is less than 0, the value Uref of the processed signal TS is 0 or more, and the value U1 of the signal IS is less than the negative saturation upper limit value Lm, that is, U1<0, Uref≥ In the case of 0 and U1<Lp, the output signal OS is set to a negative saturation upper limit value Lm. The negative saturation upper limit value Lm in this case is 0 when Uref≧0. Accordingly, when the signal IS is less than 0 and the signal IS and the processed signal TS are in opposite phases, the signal processing unit 62 sets the output signal OS to 0. That is, the signal processing unit 62 sets the output signal OS to 0 when U1<0 and Uref≧0.

As can be seen from the above, the signal processing unit 62 outputs the signal IS as the output signal OS when the signal IS and the processed signal TS are in phase and the absolute value of the signal IS is equal to or smaller than the absolute value of the processed signal TS. In addition, the signal processing unit 62 outputs the processed signal TS as the output signal OS when the signal IS and the processed signal TS are in the same phase and the absolute value of the signal IS exceeds the absolute value of the processed signal TS. Furthermore, the signal processing unit 62 sets 0 as the output signal OS when the signal IS and the processed signal TS are in opposite phases.

In this way, when the signal processing device S3 processes the signal IS to generate the output signal OS, the output signal OS is output as a signal having a waveform shown in FIG. 10 . As shown in FIG. 10 , the output signal OS has no phase shift with respect to the signal IS, and becomes a signal having the same phase waveform. Thus, the output signal OS is output as a signal with no phase shift with respect to the original signal IS output from the acceleration sensor A. As shown in FIG. Thus, the signal processing device S3 can perform high-pass filter processing on the original signal IS output by the acceleration sensor A, and can output an output signal OS without phase shift. Therefore, in the control device using the output signal OS processed by the signal processing device S3, the phase margin can be ensured when the control is executed, and the control will not be unstable even if the control gain is set high. Therefore, the control performance is improved.

In addition, in this example, the signal processing devices S1 , S2 , S3 process the signal IS output by the acceleration sensor A, but the original signal IS is not limited thereto, and of course, signals other than sensors can also be processed.

As mentioned above, although preferred embodiment of this invention was demonstrated in detail, unless it deviates from the protective scope of a claim, modification, deformation|transformation, and a change are possible.

This application claims priority based on Japanese Patent Application No. 2017-014307 filed with the Japan Patent Office on January 30, 2017, and the entire contents of this application are incorporated herein by reference.

Claims (5)

1. A signal processing device is characterized by comprising:

a filter that filters a signal; and

an output unit that outputs an output signal based on the phase of the signal and the processed signal obtained by processing the signal by the filter;

the filter is a high-pass filter,

the output unit biases the signal by a bias value with an amplitude center value of the signal as a bias value, and when the signal after the bias and the signal after the processing are in phase, uses a signal having a smaller value of the absolute value of the signal after the bias and the absolute value of the signal after the processing as an output signal,

and when the offset signal and the processed signal are in the opposite phase, taking 0 as an output signal.

2. A signal processing device is characterized by comprising:

a filter that filters a signal; and

an output unit that outputs an output signal based on the phase of the signal and the processed signal obtained by processing the signal by the filter;

the filter is a low-pass filter,

the output unit biases the signal and the processed signal by using an amplitude center value of the signal as a bias value, and when the biased signal and the biased processed signal are in phase, uses a signal having a smaller value out of an absolute value of the biased signal and an absolute value of the biased processed signal as an output signal,

and when the offset signal and the offset processed signal are in the opposite phase, taking the offset value as an output signal.

3. A signal processing device is characterized by comprising:

a filter that filters a signal; and

an output unit that outputs an output signal based on the phase of the signal and the processed signal obtained by processing the signal by the filter;

the filter is a low-pass filter,

the output unit uses the signal as an output signal when the signal and the processed signal are in opposite phases,

in the case where the signal and the processed signal are in phase and the absolute value of the signal exceeds the absolute value of the processed signal, subtracting the processed signal from the signal to generate the output signal,

and when the signal and the processed signal are in phase and the absolute value of the signal is less than or equal to the absolute value of the processed signal, 0 is taken as an output signal.

4. A signal processing device is characterized by comprising:

a filter that filters a signal; and

an output unit that outputs an output signal based on the phase of the signal and the processed signal obtained by processing the signal by the filter;

the filter is a high-pass filter,

the output section takes the signal as an output signal in a case where the signal and the processed signal are in phase and an absolute value of the signal is equal to or less than an absolute value of the processed signal,

in the case where the signal and the processed signal are in phase and the absolute value of the signal exceeds the absolute value of the processed signal, the processed signal is taken as an output signal,

and when the signal and the processed signal are in opposite phases, taking 0 as an output signal.

5. The signal processing device according to any one of claims 1 to 4, wherein,

the filter is a first order low pass filter or a first order high pass filter.

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