JPS61252715A - Mビツト2進カウンタ - Google Patents

Mビツト2進カウンタ

Info

Publication number
JPS61252715A
JPS61252715A JP61015984A JP1598486A JPS61252715A JP S61252715 A JPS61252715 A JP S61252715A JP 61015984 A JP61015984 A JP 61015984A JP 1598486 A JP1598486 A JP 1598486A JP S61252715 A JPS61252715 A JP S61252715A
Authority
JP
Japan
Prior art keywords
gate
output
input
latch
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61015984A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0332246B2 (enExample
Inventor
デービツト・エイチ・ボイル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS61252715A publication Critical patent/JPS61252715A/ja
Publication of JPH0332246B2 publication Critical patent/JPH0332246B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/56Reversible counters
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits

Landscapes

  • Logic Circuits (AREA)
  • Error Detection And Correction (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
JP61015984A 1985-04-30 1986-01-29 Mビツト2進カウンタ Granted JPS61252715A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US728964 1985-04-30
US06/728,964 US4637038A (en) 1985-04-30 1985-04-30 High speed counter

Publications (2)

Publication Number Publication Date
JPS61252715A true JPS61252715A (ja) 1986-11-10
JPH0332246B2 JPH0332246B2 (enExample) 1991-05-10

Family

ID=24928990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61015984A Granted JPS61252715A (ja) 1985-04-30 1986-01-29 Mビツト2進カウンタ

Country Status (5)

Country Link
US (1) US4637038A (enExample)
EP (1) EP0199988B1 (enExample)
JP (1) JPS61252715A (enExample)
CA (1) CA1250908A (enExample)
DE (1) DE3685905T2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2595520B1 (fr) * 1986-03-07 1993-09-10 Thomson Csf Compteur binaire elementaire, compteur binaire synchrone et diviseur de frequence mettant en oeuvre ce compteur elementaire
US4845728A (en) * 1988-01-13 1989-07-04 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration VLSI binary updown counter
KR100609543B1 (ko) * 1999-06-29 2006-08-04 주식회사 하이닉스반도체 카운터
DE19930179C2 (de) * 1999-06-30 2001-07-05 Infineon Technologies Ag Hochgeschwindigkeitszähler
US7587020B2 (en) * 2007-04-25 2009-09-08 International Business Machines Corporation High performance, low power, dynamically latched up/down counter

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3564218A (en) * 1968-04-17 1971-02-16 Atomic Energy Commission Bidirectional counting system
US3657557A (en) * 1970-10-19 1972-04-18 Gen Instrument Corp Synchronous binary counter
JPS5222505B2 (enExample) * 1973-02-09 1977-06-17
US3943378A (en) * 1974-08-01 1976-03-09 Motorola, Inc. CMOS synchronous binary counter
JPS5158056A (en) * 1974-11-18 1976-05-21 Tokyo Shibaura Electric Co N shinkauntakairo
JPS5227348A (en) * 1975-08-27 1977-03-01 Hitachi Ltd Counter
US4464774A (en) * 1982-03-15 1984-08-07 Sperry Corporation High speed counter circuit
US4587665A (en) * 1982-10-15 1986-05-06 Matsushita Electric Industrial Co., Ltd. Binary counter having buffer and coincidence circuits for the switched bistable stages thereof
US4502014A (en) * 1982-11-24 1985-02-26 Rca Corporation Coincident pulse cancelling circuit

Also Published As

Publication number Publication date
DE3685905D1 (de) 1992-08-13
EP0199988A3 (en) 1988-08-17
DE3685905T2 (de) 1993-02-04
US4637038A (en) 1987-01-13
JPH0332246B2 (enExample) 1991-05-10
EP0199988B1 (en) 1992-07-08
EP0199988A2 (en) 1986-11-05
CA1250908A (en) 1989-03-07

Similar Documents

Publication Publication Date Title
US4710650A (en) Dual domino CMOS logic circuit, including complementary vectorization and integration
EP0147598B1 (en) Clocked differential cascode voltage switch logic circuit
JP3253347B2 (ja) 機能的に完全なセルフタイミング機能付き論理回路群
US5329176A (en) Self-timed clocking system and method for self-timed dynamic logic circuits
KR100294997B1 (ko) 스태틱다이나믹논리회로
US6201415B1 (en) Latched time borrowing domino circuit
US6037829A (en) Look-up table using multi-level decode
US5867049A (en) Zero setup time flip flop
US4323982A (en) Logic circuit arrangement in the integrated MOS-circuitry technique
US6052008A (en) Generation of true and complement signals in dynamic circuits
WO1993019529A1 (en) Asynchronous-to-synchronous synchronizers, particularly cmos synchronizers
JPH0440894B2 (enExample)
US4749886A (en) Reduced parallel EXCLUSIVE or and EXCLUSIVE NOR gate
US6420905B1 (en) Vented CMOS dynamic logic system
US5281946A (en) High-speed magnitude comparator circuit
US3900742A (en) Threshold logic using complementary mos device
JPH10105378A (ja) 並列加算器
US6222404B1 (en) Edge-triggered dual-rail dynamic flip-flop with an enhanced self-shut-off mechanism
JPS61252715A (ja) Mビツト2進カウンタ
EP0178419B1 (en) Dynamically selectable polarity latch
US7940087B1 (en) Clockless return to state domino logic gate
US6509772B1 (en) Flip-flop circuit with transmission-gate sampling
US5250855A (en) Fast logic circuits
US6731138B2 (en) Circuits and methods for selectively latching the output of an adder
US7936185B1 (en) Clockless return to state domino logic gate