JPS61252706A - Comparator - Google Patents

Abstract

PURPOSE:To attain high circuit integration and low power consumption by using a circuit where a bipolar transistor (TR) and a MOS TR are composed, the coincidence logic is constituted by the MOS TR and the bipolar TR is used as a sense amplifier. CONSTITUTION:n-Set of one bit comparison cells 401 are connected in parallel with a coincident line 301 of a comparator detecting the coincidence between n-bit data a1-an and n-bit data b1-bn. The cells 401 are constituted by NMOSes, to which signals am, bm and their inversion signals am', bm' are inputted, and when the am, bb are dissident, the 1-bit comparison cells 401 draw a current from the coincident line and when they are coincident, no current is drawn. Since the n-set of 1-bit comparison cells are connected in parallel with the coincident line 301, the current is not drawn only when all the bits are coincident. When at least one bit among the bits a1-an and b1-bn is dissident, a corresponding comparison cell draws a current from the line 301. Thus, high circuit integration and low power consumption are attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a comparator, and particularly to a comparator suitable for realizing a large-capacity, high-speed associative memory.

[Background of the invention]

FIG. 4 shows the logic of an 8-bit comparator. When inputs 101-108 and inputs 109-116 match, output 117 becomes 1. 118-125 is EN
It is an OR (exclusive N0R) gate. , an example in which the ENOR gate is configured with 0MO8 is shown in FIG. Output 203
typically takes a logic amplitude of 0 to 5V. The circuit shown in FIG. 4 has a drawback that the logic amplitude is large and the AND gate 126 has multiple inputs, so the delay time from input to output is large. On the other hand, if a bipolar gate such as ECL is used, it is possible to increase the speed, but the power consumption is large and the element size is large, so it is not suitable for highly integrated circuits.

[Purpose of the invention]

An object of the present invention is to provide a comparator that is high speed, consumes little power, and has a small size.

[Summary of the invention]

The feature of the present invention is that it uses a circuit that combines bipolar transistors and MOS transistors.
Configure matching logic with Tongister.

A bipolar transistor is used as a sense amplifier.

With this configuration, the logic amplitude of the matching logic circuit can be kept low, resulting in high-speed operation. Furthermore, since most of the circuit is composed of MOS, high integration and low power consumption are possible.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a comparator that detects a match between n-bit data a-all and n-bit data b1-bn. 301 is a match line. - n one-bit comparison cells 401 are connected in parallel to the line 301 as shown in the figure. 501 is a sense amplifier for the match line 301, and 302 is a sense amplifier output.

The one-bit comparison cell 401 is NM
Assume that saw is composed of O8 and receives signals a, tb+m and their inverted signal alffljb1m,
If they do not match, the one-bit comparison cell 401 extracts current from the line, and conversely, if it matches allI, it does not draw current. Since the one-bit comparison cells are connected in parallel, current is not drawn out only when all bits match, a1 to a.
If at least one bit among II and b1 to bn does not match, the corresponding comparison cell draws current from the - line 301.

FIG. 3 shows the configuration of the sense amplifier 501. 502 is a resistance element that supplies collector current. 503 is a resistance element that supplies pace current. −
When at least one comparison cell draws current through line 301, bipolar transistor 504 turns off and output 505 goes high. On the other hand, a1 to aII and b2
When ~b- matches and there is no comparison cell from which to draw current, bipolar transistor 504 turns on and output 5
05 is a low level.

The voltage amplitude of the match line 301 is suppressed to the base-emitter voltage (about 0.8V) of a bipolar transistor,
High-speed operation is possible. That is, the current drawn by the comparison cell constituted by a MOS is detected by a bipolar transistor with a high mutual inductance g.

FIG. 6 shows a modification of the comparator shown in FIG. The configurations of the sense amplifier 501 and the negative line 301 are the same, but a memory cell is built in the comparison cell 01, and the data of the memory cell and the data lines D□ to D. This is a comparator that compares input data.

FIG. 7 shows an example of the configuration of a comparison cell.

PMO8702,703 and NMO8704°705.7
06,707 constitute a memory cell. To write data to a memory cell, put the data on the data lines D, and set the write line 601 to a high potential.Next, return the write line to a low potential and write the data you want to compare. If you input from the line, NMO8708, 709, 71
By 0°711, a matching logic between the data line and the memory cell is established. The operation of drawing current from the match line when there is a mismatch is as described above. Data line, ,D
- is used for both writing to the storage cell and inputting to the comparison cell.

According to the comparator shown in FIG. 6, a comparator that matches the stored data can be realized.

This is very useful for realizing the associative memory described below.

Next, an embodiment in which an associative memory is constructed using the comparators shown in FIGS. 1 and 6 will be described. Associative memory is used in computer systems as Gash memory for speeding up data access and T memory for speeding up address conversion.
LB (TranslationLookasi
de Buffer), and its speedup is.

Important for increasing system performance. Here, explanation will be given using a cache memory as an example.

FIG. 8 is a block diagram of a set associative type cache memory system. 801 is an address bus, 802
is an address register, 803 is a directory storage unit, 8
04 is a data storage unit, 805 is a comparator, 806 is a data register, and 807 is a data bus. 809 is a signal indicating that the cache has been hit.

The lower bits of address register 802 are sent to data storage and directory storage. Meanwhile, the upper bits are sent to the comparator. The data read from the data storage section 804 is stored in the data register 806. On the other hand, the comparator compares the address read from the directory storage section with the upper bits of the address register, and if they match, sends the contents of the data register to the data bus 807.

The cache memory access time is the sum of the directory read time and the time required for the comparator. If the comparator shown in FIG. 1 of the present invention is used as a comparator, a high-speed access cache memory becomes possible.

FIG. 9 shows an example of the configuration of a cache memory in which a directory storage section and a comparator are integrated to further speed up access. Reference numeral 808 denotes a directory storage section with a built-in comparator, which receives both upper and lower addresses from the address register and sends a signal 809 indicating whether or not the data read from the data storage section is correct to the data register.

FIG. 10 shows the configuration of the directory storage section 808 with a built-in comparator. 1003 is a lower address, 1001 is a decoder that decodes the lower address, D
1 to D are upper addresses, 1o O2s* are comparators built into the memory cells shown in FIG. 1004 is a write signal; 1005 is a signal line indicating address matching;
501 is the sense amplifier explained in FIG.

D- to D- are compared in parallel with all data stored in the memory cells. The circuit that performs this is 1002, and its operation is as explained in FIG. The lower address 1003 is decoded by the decoder 1001 and one corresponding word is selected. A signal line 1005 is a signal line for taking out the output signal of the comparator 1002 with a built-in storage cell of the selected word. As a sense amplifier for this signal line, 501 in FIG. 3 is used to increase the speed. The word selected by the lower address and D1 to D11
If they match, the signal 809 becomes a low potential; if they do not match, a signal 809 becomes a high potential. That is, the signal 809 is a signal that becomes low potential if the cache memory is hit.

In the circuit shown in FIG. 10, comparison is performed in parallel with address decoding, so high-speed access is possible.

The circuit of FIG. 11 is a modification of the circuit of FIG. 10, that is, the sense-up of each word is removed.

The configuration is such that the sense amplifier 501 of the signal line 1005 directly senses the match line of the word selected by the decoder.

In the circuit of FIG. 1O, the current is extracted from the signal line 1005 by two stages of NMO8, but in the circuit of FIG.

Therefore, current is extracted from the signal line 1005 by the selected 8MO8 in one stage, a total of three stages. but.

The sense amplifier for each word is omitted, and the match line for each word is connected to the signal line 1005 with a low amplitude. Therefore, the overall speed is increased. This effect is particularly remarkable when the number of words is small. Furthermore, since there is no sense up of each word, there is an effect that the area is also reduced.

8 and 9 (!l) show an embodiment of a set-associative type cache memory system, whereas FIG. 12 shows an example of a fully associative type cache memory system.

A storage unit 1200 stores pairs of addresses and data, and sends data corresponding to an address that matches the address 802 to a data register 806 through 1201. 801, 809° and 807 are as described above.

FIG. 13 shows the configuration of 1200.

1002 is the memory cell built-in comparator explained in FIG. 6, and D1 to D are address input lines.

1303 is a word driver, W□~WK are word lines 13
02 is a data storage cell, 1301 is a read/write control circuit for the data storage cell 1302, and 1300 is a
This is a write control circuit for memory cells in comparison cell 01.

The addresses input to D1 to [)+ are compared by the comparator 1002 with the addresses stored in the memory cells in all the words. If there is a matching word, the corresponding word driver 1303 drives the word line.

As a result, the selected data is sent out via 1201. The operation of signal 1005 and signal 809 is as explained in FIG.

FIG. 14 shows a comparator in which a masking function is added to the comparator with a built-in memory cell shown in FIG. The mask function only applies to the bits specified by the mask register out of the n-bit input data.

Refers to the function of matching data stored in memory cells. Reference numeral 1500 is a comparison cell containing a storage cell and a mask.

FIG. 15 shows the circuit of comparison cell 1500. 702 to 707 are memory cells that store data to be compared, 1502 to 1507 are memory cells that store mask data, and 1400 is a mask data write line.

708,709°710.711.1501 is the matching logic.

The mask function is realized by NMO81501.

In other words, if 1501 is turned off, even if the data line of that bit and the contents of the data stored in memory cells 02 to 707 do not match, the comparison cell 1501
does not draw current from the match line 301, and writes mask data.

The comparison cell 1500 having a mask function is used in the associative memory described in FIGS. 8 to 13 above.
If it is replaced with 1, an associative memory with a masking function can be obtained.

According to the embodiment, a content addressable memory with high speed, high integration, and low power consumption can be realized.

〔Effect of the invention〕

According to the present invention, since the voltage amplitude of the coincidence line can be lowered, there is an effect of increasing the speed. Also, MOS is used for comparison logic.
Since transistors can be used, there is an effect of high integration and low power consumption.

[Brief explanation of the drawing]

1 is a block diagram showing the most basic embodiment of the present invention; FIG. 2 is a circuit diagram showing the comparison cell of FIG. 1;
1 is a circuit diagram showing the sense circuit of FIG. 1. FIG. Figures 4 and 5 are explanatory diagrams of the conventional example, and Figures 6 to 1 are
FIG. 2 is a diagram showing an embodiment in which the present invention is applied to an associative memory. 301... Match line, 401... Comparison cell, 5o1・
...Sense amplifier, 504... Bipolar transistor, 5, o2, 503... Resistance element.

Claims (1)

[Claims] 1. A circuit for detecting a match between n-bit data a_1...a_n and other n-bit data b_1...b_n, comprising a bipolar transistor and a base current of the bipolar transistor. a resistive element that supplies the collector current of the bipolar transistor, a data line that draws out the base current of the bipolar transistor, and n a_m connected in parallel to the data line b_m. 1. A comparator comprising a matching circuit which draws a base current through a data line and turns off the bipolar transistor if they do not match.