JPS6125263B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the configuration of a frequency divider driven by low power consumption.

[Conventional technology]

In order to improve the time accuracy of electronic clocks, it is effective to use a high frequency signal (for example, 4MHz band) such as an AT board crystal oscillator as a time reference signal.

FIG. 3 shows a block diagram of a frequency division method using a conventional frequency divider.

1 is a high frequency time reference signal (hereinafter referred to as HF signal) and the output frequency is . 2 and 3 are frequency dividers, and the whole makes up one frequency divider system. Frequency divider 2 is a high frequency domain frequency divider that divides the HF signal to obtain frequency ₁ =
₀ /n (where n is the division order of frequency divider 2)
Create a signal with . The frequency divider 3 is a low frequency region frequency divider and divides the signal of frequency ₁ to create a time measurement unit signal of, for example, 1 Hz.

In this way, in the conventional frequency division method, the frequency divider is operated continuously.

[Problems to be Solved by the Invention] Electronic watches are strongly required to drive with low power consumption. In the process of creating a time unit signal, the power consumption due to the operation of the frequency divider is large, and in particular, the first frequency divider 2 and the second frequency divider 3 shown in FIG. 3 require frequency division operation in a high frequency band. Frequency divider 2 consumes a large amount of power. SUMMARY OF THE INVENTION An object of the present invention is to provide a frequency divider that eliminates the above-mentioned conventional problems and reduces power consumption in frequency dividing operations in high frequency bands.

[Means for solving problems]

In order to achieve the above object, the present invention has the following configuration.

a time reference signal source, a first frequency divider for a high frequency band in a region close to the source frequency of the time reference signal source, a voltage controlled oscillator, a phase comparator, a charge pump circuit, an integrator, and a voltage control A timing control section is provided which operates according to signals from the oscillator and the phase comparator, and the timing control section generates a first phase comparison period and a second phase comparison period.

In the first phase comparison period, the output signal of the first frequency divider of the time reference signal and the output signal of the voltage controlled oscillator are compared in phase, and the output signal of the voltage controlled oscillator is controlled to detect whether the two signals match in phase. Then, the process moves to the second phase comparison period.

During the second phase comparison period, the frequency division operation of the first frequency divider of the time reference signal is stopped, and the phase comparison between the output signal of the time reference signal source and the output signal of the voltage controlled oscillator is performed. When the output signal is controlled and the set number of pulses of the voltage controlled oscillator is counted, the first phase comparison period starts again.
and a second phase comparison base, and divide the output signal of the controlled voltage controlled oscillator using a second frequency divider that divides the frequency of the low frequency region to obtain a time measurement unit. Create a signal.

[Effect]

When creating a frequency divider driven by low power consumption using the above configuration, in the first phase comparison period, the output signal of the voltage controlled oscillator is accurately frequency-divided with the frequency-divided signal of the high-precision time reference signal. and compensate so that the phases match. In the next second phase comparison period, the output signal from the voltage controlled oscillator, which has been compensated with high accuracy, and the output signal of the time reference signal are compared in phase, and the voltage controlled oscillator is controlled to have the accuracy of the time reference signal source. Do the following. The output signal from the voltage controlled oscillator, which has been compensated with high accuracy in this manner, is frequency-divided to create a timekeeping unit signal.

Since the frequency dividing operation in the high frequency band is stopped during the second phase comparison period, there is no voltage consumption of the frequency divider, and low power consumption is realized.

[Implementation row]

Embodiments of the frequency divider of the present invention will be described below with reference to the drawings.

[Operation of frequency divider system]

FIG. 1 shows a system block diagram of a frequency divider according to the present invention.

1 is a time reference signal that generates a high frequency such as an AT board crystal oscillator, and its output frequency is set to ₀ . (hereinafter referred to as HF signal) 2 is a first frequency divider (hereinafter referred to as frequency divider H) that divides the high frequency band of the HF signal, and the division order of this frequency divider H is defined as n. Then, the output frequency at frequency divider H is ₁ = ₀ /n.

4 is a voltage controlled oscillator (hereinafter referred to as VCO) with an output frequency _{of 2} . 5 is an electronic switch mechanism that controls on/off of the frequency division operation of frequency divider H, and 6 is a gate circuit that performs logical operations on the output signals of each frequency division stage that constitute frequency divider H, and is synchronized with the HF signal. to create a signal with an output frequency of ₁ (hereinafter referred to as the FS signal). 7 is a phase comparator that receives the HF signal, FS signal, and VCR signal as input; 8 is a charge pump circuit that operates according to the output signal of the phase comparator 7; and 9 is an integrator that smoothes the output voltage from the charge pump circuit 8. Then, the voltage from the integrator 9 is fed back to the VCO 4. Furthermore, VCO4 is phase comparator 7
The phase difference information signal from

Reference numeral 13 denotes a timing control section, which operates with input signals from the VCO 4 and the phase comparator 7, and is composed of a phase coincidence detection circuit 10, a timer 11, and a control signal generation circuit 12, and controls the frequency dividing operation of the frequency divider H. A control signal is generated to control the operation of the electronic switch mechanism 5 and the phase comparator 7.

A second frequency divider 3 (hereinafter referred to as frequency divider L) divides the frequency of the output signal of the VCO 4, and creates a time measurement unit signal of, for example, 1 Hz.

FIG. 2 shows a timing chart explaining the concept of the operation of the frequency divider circuit of the present invention shown in FIG. 1, and details of the operation will be explained.

The signal 21 is an HF signal, for example, a signal with an output frequency of 4MHz. Signal 22 is the HF signal sent to frequency divider H
FS obtained by dividing the frequency by and processing in gate circuit 6
The signal is, for example, a 32KHz signal. Signal 23 is
This is the output signal of the VCO and is also in the 32KHz band.

The timing control section 13 generates a first phase comparison period and a second phase comparison period using the VCO signal and the phase difference signal.

Signal 24 is the PS signal that causes the first phase comparison to be performed. Now, the PS signal 24 becomes H level, a signal is generated from the control signal generation circuit 12 during the first phase comparison period, the electronic switch mechanism 5 is turned on, and the first frequency divider 2 starts the frequency dividing operation. conduct,
The FS signal 22 is input to the phase comparator 7. At this time, the control signal generation circuit 12 also issues a control signal, and the phase comparator 7 outputs the VCO signal 23.
The phase comparison operation of the FS signal 22 and the FS signal 22 is performed.

During this first phase comparison period, the phase of the VCO signal 23 and the phase of the FS signal 22 are compared, a phase difference pulse corresponding to the phase difference is generated by the phase comparator 7, and the phase difference pulse controls the phase of the VCO 4. At the same time (this operation will be described later), a control voltage corresponding to the phase difference is generated by the charge pump circuit 8 and the integrator 9 and fed back to the VCO 4 to control the phase and frequency of the VCO signal 23. The frequency and phase of signal 23
The frequency and phase of the FS signal 22 are made to match.

This operation is called prescaler operation (P/S operation).
It is called.

The phase coincidence detection circuit 1 which is a component of the timing control section 13 performs phase coincidence detection in this P/S operation.
0, and the operation of the first phase comparison period is completed. Signal 25 causes a second phase comparison to take place.
It is a PL signal. When PS signal 24 goes to L level
The PL signal becomes H level. At this time, the control signal generation circuit 1 which is a component of the timing control section 13
A control signal is issued by 2 to turn off the electronic switch mechanism 5, causing the first frequency divider 2 to stop dividing and no FS signal 22 being produced.

At this time, the control signal generation circuit 12 also generates
A control signal is issued to the phase comparator 7, and the phase comparator 7 compares the phases of the VCO signal 23 and the HF signal 21.

In this second phase comparison period, the phases of the VCO signal 23 and the HF signal, which were compensated with high precision in the first phase period, are compared, and the phase comparator 7 emits a phase difference pulse corresponding to the phase difference. A control voltage according to the voltage is generated by the charge pump circuit 8 and the integrator 9 and fed back to the VCO 4,
The VCO signal 23 is controlled and compensated to have the accuracy of an HF signal. This operation is called a phase lock operation (P/L operation).

This second phase comparison period is
It is controlled by counting the number of pulses of the VCO signal 23 by the timer 11, which is a component of 3, and when the timer 11 counts the set number of pulses of the VCO signal 23, the operation of the second phase comparison period is stopped. Then, the process returns to the first phase comparison period described above, and this operation is repeated.

As mentioned above, in the first phase comparison period, VCO
If the signal 23 is compensated with high precision, within one cycle of the HF signal 21 during the second phase comparison period,
Even if the VCO signal 23 fluctuates, the VCO signal 23
This second function can compensate for the accuracy of the HF signal.
During the phase comparison period of , it is possible to reduce the frequency division power consumption of the frequency divider H that performs frequency division of a high frequency band.

The longer the second phase comparison period, the greater the effect of reducing power consumption, but if VCO4 is configured with a CR oscillator, the frequency will be reduced by natural discharge of the charge in the capacitor, which is a factor that determines the frequency, and temperature changes in the resistor. Since a deviation may occur, it is necessary to set the second phase comparison period according to the oscillation stability of the VCO 4.

Next, the configuration and operation of each part constituting the frequency divider will be explained.

[VCO operation]

FIG. 4a shows the configuration of a VCO circuit that converges the phase difference to 0, and FIG. 4b shows a signal waveform diagram to explain the operation.

31 and 32 are CMOS inverters, and 33 and 34 are resistors having values of R1 and R2, respectively. 35 is an n-channel MOS transistor whose source and drain electrodes are connected to both ends of the resistor 34, and whose gate electrode is connected to the output side of the integrator 9. 36 is a capacitor whose capacity is _C1 .

As described above, the basic configuration of the VCO 4 is a ring oscillator type including a resistor and a capacitor, but the phase control means 37 is inserted into the capacitor charging/discharging circuit to achieve phase convergence.

For VCO4, the composite low resistance R is determined by the gate voltage V _G of the n-channel transistor 35, and the oscillation frequency changes depending on RC ₁ , but in an ideal state V _G
If = 0, the synthetic resistance will be (R1 + R2),
When V _G =V (power supply voltage), the combined resistance is R1.

Therefore, depending on the frequency of the FS signal 22 mentioned above, R
It is necessary to set 1 and R2, and if the oscillation frequency when V _G = 0 _{is L} and the oscillation frequency when V _G = V is _H , frequency compensation is possible if _L < ₁ < _H. However, since frequency compensation is determined by the phase difference, depending on the configuration of the phase comparator 7, it may be inconvenient if the absolute value of the phase difference between the two signals exceeds the range of 2π. If the FS signal rises at time t ₁ and the VCO signal rises at time t ₂ in the waveform diagram of FIG. A corresponding phase difference pulse is emitted. This phase difference pulse is determined to be ₁ > ₂ , and in order to increase the frequency of the VCO output signal, the charge pump 8 issues a charging pulse as shown in the figure, and the voltage signal integrated through the integrator 9 is
It is applied to the gate electrode of the n-channel transistor 35 of the VCO, and V _G becomes higher than the potential before time _t1 , so that the combined resistance of the VCO becomes smaller and the oscillation frequency becomes higher. Here, ₂ is the frequency of the output signal of VCO4.

Next, when the VCO signal rises at time _t3 and the FS signal rises at time _t4 , the VCO signal is in a phase lead state with respect to the FS signal.
A phase pulse corresponding to the phase difference is emitted from the phase comparator circuit 7. This phase difference pulse is determined to be ₁ < ₂ , and a discharge pulse is emitted from the charge pump 7 in order to lower the output frequency of the VCO.

In the conventional VCO circuit, an electronic switch mechanism 37 for controlling the phase is not added. For example, when the discharge pulse obtained this time is smoothed by the integrator 9 and applied to the VCO circuit, the gate voltage V _G of the transistor 35 becomes the same as before. , the combined resistance R becomes larger, and the period is lengthened. Even if the phases match at time t ₅ , the period of the VCO signal is then that of the period between times t ₃ and t ₅ , and in subsequent phase comparisons, the state at times t ₁ and t ₂ described above will be obtained. A charging pulse will be emitted again. That is, in this way, the phase difference does not converge but always advances, resulting in a lag state, which can only result in an oscillatory stable state. When looking at the gate voltage V _G of the n-channel transistor 35, + and - states of potential are obtained with V _G as the center. This state generally oscillates in a trigonometric manner, and the amplitude is determined by the initial state.

At this time, it can be said that the average value of the VCO signal is close to the FS signal frequency when viewed over a long period, but when viewed over a short period of time, it has a fluctuation component with respect to the FS signal and phase compensation in PL operation after PS operation. The margin becomes small, and errors may be accumulated when the operation changes, making it unstable as a time signal. Further, if such a VCO signal is used, phase synchronization detection becomes impossible, and the timing for stopping the frequency divider 2 cannot be obtained. Next, the operation when the phase control switch means 37 is added will be explained using an example of times t ₃ and t ₄ .

When a discharge pulse as shown in FIG. 4b is obtained, the electronic switch 37 is turned off for the duration of the pulse to open the path between the output side of the inverter 32 and the switch side of the capacitor 36. By doing so, the charge/discharge states of R and _C1 are controlled, and the phase of the VCO signal is controlled. During this time, the discharge pulse
Since the feedback is being fed back to the VCO, the value of the combined resistance R is different from before, and if the switch 37 is turned on again at time _t4 to create a normal charging/discharging path, the period of the VCO signal will be lengthened and at the same time the phase state will also change. It's different. If phase matching is obtained at time t ₅ , then the periods of the VCO signal are t ₄ and t ₅
Since the period of the VCO output signal and the FS signal are determined by the period, no phase correction pulse is emitted, and the phases continue to match, and the period of the VCO signal is exactly equal to the period of the FS signal.

It can be proven that this phase convergence is exponential convergence. If phase convergence is achieved, the potential of V _G will also converge to a constant value.

If the configuration is configured so that phase convergence can be obtained during PS operation in this way, stop information of frequency divider 2 can be easily obtained, and if a VCR signal without fluctuation is obtained, subsequent
The compensation margin during PL operation is increased, and errors at the time of transition of operation can be eliminated. Fourth
Although the explanation in the figure shows an example in which the phase of the VCO is controlled using a lead signal, it is also possible to perform phase control using a phase lag signal.

[Operation of timing control section]

FIG. 5 shows the configuration of the timing control section 13,
The operation of switching between the first phase comparison period and the second phase comparison period will be explained with reference to a timing chart shown in FIG.

FIG. 51 shows a crystal oscillation circuit for creating a high frequency time reference signal (HF signal), and 101 is an AT plate crystal oscillator, for example. 2 is a first frequency divider for HF signals with a reset terminal, and the electronic switch mechanism shown in FIG. 1 corresponds to the reset mechanism of the first frequency divider 2. The gate circuit 6 is constituted by an AND gate, and performs an AND operation on the HF signal and the output signals of each frequency division stage constituting the first frequency divider 2. This AND gate output signal has a frequency of exactly ₁ = ₀ /n. In this way, not using the signal from the last output stage of the first frequency divider 2 (which has a frequency of ₀ /n) eliminates the influence of the delay of the frequency divider and prevents the PL operation from occurring.
This is to eliminate time errors when shifting to PS operation.

The timing control section 13 includes a phase coincidence detection circuit, a timer 11, and a control signal generation circuit 12.

The phase coincidence detection circuit 10 is composed of, for example, a binary flip-flop with a reset terminal, and has an OR
The output signal of gate 102 controls the reset operation. The timer 11 is similarly constructed of a binary flip-flop with a reset terminal, and operates alternately with the phase coincidence detection circuit 10. The control signal generation circuit 12 includes three AND gates 103, 104, 107 and 105, 106, 10.
It consists of 8,109 D-type flip-flops with reset terminals.

It is assumed that the flip-flops constituting the phase coincidence detection circuit 10 and the timer 11 perform frequency division in synchronization with the rising edge of the input signal. As shown in the waveform diagram of FIG.
It is assumed that the output Q _A of 106 and the output Q _B of 106 are at the H level, and the first frequency divider 2 is reset. At this time, the output of AND gate 6 is at L level.
The FS signal is not emitted, and the phase comparator 7 performs a PL operation in which the HF signal and the VCO signal are compared.

Since _A is at the L level, the reset of the timer 11 is released, and the flip-flop composing the timer operates and the AND gate 107
When the signal and the output signal of each stage of the flip-flop 11 become H level, the AND gate 10
An AND operation is performed in step 7, and the reset signal of the timer 11 is set to become H level when the VCO signal is obtained m times.

Now, when (m-1) VCO signal pulses are obtained, the AND gate 10
The output of flip-flop 7 becomes H level, and flip-flop 1
A rising signal is obtained at the clock input terminal of the flip-flop 108, and the output Q _D of the flip-flop 108 becomes H level. Subsequently, at time t _o , the output Q _E of the flip-flop 109 becomes H level. During this PL operation, the Q _B signal which is the output of the flip-flop 106 is at the H level, so the OR gate 102 which is the input to the reset terminal of the phase coincidence detection circuit 10 is at the H level.
level, and the phase coincidence detection circuit 10 stops operating. When Q _E , which is the output signal of flip-flop 109, goes to H level, the reset terminals of flip-flops 105 and 106 go to H level, Q _A and Q _B go to L level, and the first frequency divider 2 operates. A signal is issued for the next PS operation. At this time, since _A becomes H, the timer 11 stops operating.

In this PS operation, the phases of the FS signal and VCO signal are compared, and if there is a phase difference, the OR gate 1
The output of 02 becomes H level. The Q ₁ and Q ₂ signals shown in FIG. 7 are phase comparator output signals during PS operation.

When the phase difference is converged, the output of the OR gate 102 becomes L level, and the signal is frequency-divided.

For example, if the frequency of the signal is divided into 1/4 by the flip-flop of the phase coincidence detection circuit 10, the AND gate 104 becomes H at t _i - ₁ , the flip-flops 108 and 109 are reset, and the output Q
_D and Q _E become L.

Then, AND gate 1 is activated at the falling edge of the VCO signal.
The output of flip-flop 105 becomes H, and at this time, the output Q _A of flip-flop 105 becomes H. Subsequently, when the VCO signal becomes H level at t _i , the Q _B signal output from flip-flop 106 also becomes H level.

When the Q _A signal becomes H level, the frequency division operation of the first division period 2 is stopped, the PS operation is terminated, and the Q _B signal becomes H level, and the phase comparator 7 outputs the VCO signal.
Moving on to the PL operation, which compares the phase of the HF signal.

If spontaneous discharge of charge occurs during PL operation, VCO
The oscillation frequency changes, but such leakage is affected by temperature, and the higher the temperature, the greater the leakage becomes. In such cases, shorten the PL operation time,
It is also necessary not to perform PL operation. Therefore, if the frequency division stage of the timer 11 is made variable and the frequency division ratio is controlled according to the temperature, the influence of leakage can be eliminated.

[Operation of phase comparison circuit]

FIG. 7 shows an embodiment of the phase comparator circuit 7, charge pump circuit 8, and integrator 9.

61 and 62 are D-type flip-flops that perform phase comparison during PS operation.

The D input terminals of flip-flops 61 and 62 are the fifth
_{The A} signal of the flip-flop 105 shown in the figure is applied, the VCO signal is applied to the clock input terminal of the flip-flop 61, and the FS signal is applied to the reset input terminal.

The clock input terminal of flip-flop 62 is FS.
The signal and reset input terminals apply VCO signals.

The operation will be explained using the timing chart shown in FIG. 4b.

During the PS operation, _{the A} signal of the flip-flop 105 is at the H level, and when the FS signal rises at time _t1 , _{the two} output signals of the flip-flop 62 go to the L level, and the output signal _Q1 of the flip-flop 61 also goes to the L level. At time t ₂ ,
When the VCO signal rises, the signal becomes H level, but the _Q1 signal remains unchanged and remains L level.

Next, at time _t3 , when the VCO signal becomes H level, the _Q1 signal becomes H level, and the _Q2 signal remains at H level. At time _t4 , the FS signal goes high
level, the _Q1 signal becomes L level,
₂ signal remains at H level. If the FS signal and VCO signal become H level at the same time at time _t5 ,
Signals Q ₁ and Q ₂ remain in their previous states and no phase difference pulse is generated.

With the above configuration, the leading, lagging, and matching states of the VCO signal with respect to the FS signal are detected.

Next, phase comparison in PL operation will be explained.

Transmission gate 110, D-type flip-flop 63, 64, 65, AND gate 6
6, 67, and a NAND gate 68 are components for phase comparison during PL operation.

The transmission gate 110 is controlled by the Q _B output signal of the flip-flop 106 and outputs an HF signal and an L level DC voltage by switching between them. When the Q _B signal is at an H level, the HF signal is output.
When the Q _B signal is at L level, an L level DC voltage is applied to the clock input terminals of flip-flops 63 and 64 and the D input terminal of flip-flop 65.

When the transmission gate 110 outputs an H signal, it is in P/L operation, and when an L level DC voltage is output, it is in PS operation.

The purpose of switching the HF signal and inputting it to the phase comparator in this way is to save power consumption in the phase comparator during PS operation.

In this PL operation, the VCO signal is applied to the D input terminal of flip-flop 63 and the clock input terminal of flip-flop 65.

The AND gate 66 performs an AND operation on the VCO signal and _{the three} signals of the flip-flop 63, and the UN gate 67 performs an AND operation on the VCO signal and the three signals of the flip-flop _63.
An AND operation is performed between the signal and _{the four} signals of the flip-flop 64, and a NAND gate 68 performs a NAND operation between the output of the AND gate 67 and the ^Q5 signal of the flip-flop 65.

FIG. 8 shows a timing chart of the PS operation and details of the operation will be explained.

Even if the VCO signal is compensated to a signal that does not fluctuate with respect to the FS signal during the PS operation, after the PS operation ends, self-holding etc. may occur and the VCO signal may fluctuate with respect to the FS signal.

At this time, for example, in FIG. 8, times t ₁₀ and t ₂₀
Suppose there is a phase shift between the HF signal and VCO signal.

Therefore, if the VCO signal is out of phase by more than ±π with respect to one synchronization of the HF signal, the VCO signal is
It becomes impossible to convert the signal into a signal whose frequency is divided by n. Conversely, in order to prevent such inconvenience from occurring, it is necessary to provide a sufficient margin in the PS operation.

Now, the fact that the phase of the VCO is delayed with respect to timing t ₁₀ of the HF signal, which is the reference for phase comparison, means that the VCO signal is delayed in time with respect to the reference time. We need to move forward.

However, in this state, if you stand on the side of the VCO signal, t ₁₀
A direct charging pulse cannot be issued after the timing has already passed.

The VCO signal is applied to the D input terminal of the flip-flop 63, and the HF signal is applied to the φ input terminal, but the signal
Q ₃ becomes H level at t ₁₁ and flip-flop 6
4's output _Q4 becomes H level at _t12 . The output _Q5 of the flip-flop 65 becomes H level at _t10 '. When such outputs Q ₃ , Q ⁴ , Q ₅ are obtained, AND
The gate 66 performs an AND operation on the signal VCO signal and the signal ³ , and its output becomes H level during periods _t10 ' and _t11 . AND gate 67 is the AND of signal Q ₃ and signal ₄
The output becomes H level in periods t ₁₁ and t ₁₂ , and further, the NAND gate 68 performs an AND operation between the signal Q ₅ and the output signal of the AND gate 67, and the output signal is the same as the output signal of the AND gate 67. A signal that becomes L level during the periods t ₁₁ and t ₁₂ is obtained.

As described above, when the phase of the VCO signal is delayed with respect to the reference timing, a phase difference pulse for discharging is obtained from the output signal of the AND gate 66, and subsequently a charging pulse for the NAND gate 68 is obtained. If these two discharging operations are repeated in succession, a charging pulse corresponding to the phase difference between the subtractions t ₁₀ and t ₁₀ ' will be provided.

Next, if the phase of the VCO signal is leading with respect to the reference point t ₂₀ and the VCO signal is obtained at t ₂₀ ', it is necessary to consider that the VCO signal is leading and to delay the cycle.

Now at t ₂₀ ' the VCO signal goes to H level, and at t ₂₀ it goes to HF.
If the signal becomes H level, the signal _Q3 becomes H level at _t20 . Subsequently, the signal Q ₄ becomes H level at t ₂₁ , but the signal Q ₅ becomes L level at t ₂₀ ′ and continues in that state. At this time, the output of the AND gate 66 is t ₂₀ ′, t ₂₀
The AND gate 67 becomes H level between t ₂₀ and t ₂₁ , but the output of the NAND gate 68 remains at H level.

In this way, in the case of a phase advance of the VCO signal, only a direct discharge pulse is emitted, unlike the previous example, because there is a reference point t ₂₀ for phase comparison.
The phase comparator circuit of this embodiment has a configuration that operates separately for PS operation and PL operation, but here, electronic switch mechanisms 69 and 70 are provided to adjust the phase difference between signals Q ₁ and Q ₂ during PS operation. Select as pulse, PL
During operation, AND gate 66 and NAND gate 68
It is sufficient to select the output signal of as the phase difference pulse. Note that if the signal Q1 is used as a control signal for the phase control of the VCO described in FIG _. 4, it is possible to control the phase when the phase of the VCO signal advances during PS operation. During PL operation, phase control can be performed using the inverted signal of AND gate 66, and when phase control is not performed, an H level voltage must always be applied when output signal Q _B of flip-flop 106 is at H level. Bye.

Next, the configurations of the charge pump circuit 8 and the integrator 9 will be described.

Reference numerals 71 and 72 show the configuration of a charge pump circuit, where 71 is a P-channel MOS transistor and 72 is an N-channel MOS transistor. Each gate electrode is connected to a phase comparator 7, and when applying a discharge pulse, a transistor 72 is connected.
is turned on and 71 is turned off, and when giving a charging pulse, 71 is turned on and 72 is turned off.

The charge pump output is connected to the integrator,
The integrator can be constructed from a resistor R0 and a capacitor _C0 . The charging/discharging phase difference pulse is smoothed through R0 and ^C0 , and the output is fed back to the VCO circuit.

As is clear from the above explanation, the frequency divider according to the present invention uses a conventional PLL circuit including a VCO, a phase comparator, a charge pump circuit, and an integrator to calculate the phase difference between the FS signal as a reference signal, the HF signal, and the VCO signal. The frequency divider in the high frequency range is operated intermittently while comparing and compensating the phase and frequency of the VCO signal.

〔Effect of the invention〕

According to the frequency divider circuit according to the present invention, the VCO signal can be easily compensated with high precision by the VCO circuit capable of converging the phase difference, and the first phase comparison period and the second phase comparison period are provided. By this,
By intermittently operating a frequency divider in a high frequency range, power consumption in frequency division can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the frequency divider of the present invention.
Figure 2 is a timing chart explaining the operation of the frequency divider shown in Figure 1, Figure 3 is a block diagram of a conventional frequency divider, and Figure 4a is a diagram of the frequency divider of the present invention. An embodiment of the voltage controlled oscillator used, FIG. 4b is a timing chart explaining the operation of the voltage controlled oscillator, FIG. 5 is a diagram showing an embodiment of the timing control section of the frequency divider of the present invention, and FIG. 6 5 is a timing chart explaining the operation of the timing control section, FIG. 7 is a diagram showing an embodiment of the phase comparator of the frequency divider of the present invention, and FIG. 8 is a diagram explaining the operation of the phase comparator. FIG. DESCRIPTION OF SYMBOLS 1... High frequency time reference signal source, 2... First frequency divider, 3... Second frequency divider, 4... Voltage controlled oscillator, 7
... Phase comparator, 8... Charge pump circuit, 9... Integrator, 10... Phase matching detection circuit, 11... Timer, 12... Control signal generation circuit, 13... Timing control unit.

Claims (1)

[Claims] 1. A time reference signal source, a first frequency divider that divides a high frequency region of the time reference signal source, a voltage controlled oscillator, a phase comparator, and an output of the phase comparator. A charge pump circuit that responds to a signal, an integrator that smoothes an output voltage of the charge pump circuit and applies a control voltage to the voltage controlled oscillator, and a timing control section that operates based on the signals of the voltage controlled oscillator and the phase comparator. , a first phase comparison period in which the timing control section compares the phase of the output signal of the first frequency divider of the time reference signal source and the output signal of the voltage controlled oscillator; and the output signal of the time reference signal source. and generating a second phase comparison period in which the output signal of the voltage controlled oscillator is compared, and in the first phase comparison period and the second phase comparison period, according to the output signal of the phase comparator, The output signal of the voltage controlled oscillator is controlled, and the first phase comparison period detects a phase match between the output signal of the first frequency divider of the time reference signal source and the output signal of the voltage controlled oscillator. the operation of the first frequency divider of the first time reference signal source is stopped, and the operation of the first frequency divider of the voltage controlled oscillator is stopped, and the operation of the first frequency divider of the voltage controlled oscillator is stopped; When a set number of pulses of the output signal is counted, the operation is stopped and moved to the first phase comparison period, and a time unit signal is created from the output signal of the voltage controlled oscillator using a second frequency divider. A frequency divider characterized by: