JPS61251960A - Vector instruction processor - Google Patents

Abstract

PURPOSE:To speed up instruction processing by inhibiting reading of a corresponding vector factor while a mask bit read out in such a way that mask bit reading proceeds the reading of the corresponding vector factor is indicating the arithmetic to be restrained. CONSTITUTION:At the time of starting a vector instruction, a mask vector address register 12, an inter-vector factor distance registers 41-43 and vector factor registers 49-51 are initialized. The value of an address addition value register 13 is added to the value of the register 12 so as to read out the mask vector from a memory device 2 and stored in a mask vector register 32. A priority encoder 33 counts arithmetic inhibiting bits from the top of the mask vector until the initial arithmetic indicating bit can be found. A multiplying circuit 45 multiplies an inter-vector factor distance by the number of arithmetic inhibiting bits, an address adder circuit 53 adds a difference address to read the vector factor from a memory device 5. The read-out vector factor is transferred to an arithmetic device, thereby speeding up the instruction processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic processing device that processes large-scale, advanced technical calculations at high speed through vector operations.

In particular, the present invention relates to a vector instruction processing device that controls execution of vector operations using mask bits.

〔overview〕

The present invention provides a processing device that executes or inhibits an operation according to the logic level of a mask bit provided corresponding to each vector element to be operated. By prohibiting reading from the storage device, data is efficiently transferred from the storage device to the arithmetic unit.

[Conventional technology]

Computing devices that process large-scale, highly technical calculations at high speed, so-called supercomputers, perform computations using vector instructions, which are much faster than scalar instructions. In order to achieve high speed, it is important to increase the proportion of the portion processed by vector instructions, that is, the vectorization rate, as much as possible. Therefore, when performing loop calculations including conditional statements, masked vector calculations are performed.

In masked vector operations, a mask bit is provided for each vector element (also called a "vector operand") to be operated on, and when the logic level of this mask bit is "0", the operation is prohibited. .

Hereinafter, the mask focus whose logic level is rOJ will be referred to as an operation inhibition bit, and the mask bit whose logic level is "1" will be referred to as an operation instruction bit. Such a sequence of mask bits is called a mask vector.

A conventional general vector instruction processing device executes a vector instruction with valid mask bits as follows. That is, first, vector elements are read from the storage device regardless of the value of the mask bit, and the vector elements are temporarily stored in a buffer. Thereafter, when the mask bit is an operation instruction bit, the vector elements stored in the buffer are supplied to the arithmetic unit. When the mask bit is an operation inhibit bit, the vector element is not supplied to the arithmetic unit.

Such a vector instruction processing device will hereinafter be referred to as a first conventional example.

In such a first conventional example, when there are many operation inhibiting bits in a mask vector, the proportion of time that an arithmetic unit performs an operation decreases. Therefore, there is a drawback that a lot of calculation time is wasted until the vector instruction is completed.

In order to solve these drawbacks, a vector instruction processing device that processes mask vectors by dividing them into fixed bit widths has been developed.
It is disclosed in Japanese Patent Application No. 56422024. In such a device, a mask vector is divided into a constant bit width, and when all the mask bits therein are operation inhibit bits, reading and operation of vector elements are prohibited. Thereby, processing time can be shortened when the mask vector includes a large number of operation inhibit bits. A mask vector that tends to include a large number of operation inhibit bits is said to have strong sparking properties. Such a vector instruction processing device will hereinafter be referred to as a second conventional example.

[Problem that the invention seeks to solve]

However, the above-mentioned second conventional example has a problem when a small number of operation instruction bits are included in a mask vector divided into a constant bit width. For example, even if there is only one operation instruction bit in a partitioned mask vector and all other mask bits are operation inhibit bits, the vector element is read from the storage device and the same processing as in the first conventional example is performed. conduct. Therefore, there is a drawback that a lot of time is wasted in calculation time.

That is, by increasing the bit width that separates mask vectors, the calculation speed can be reduced if all mask bits in the partitioned mask vectors are operation inhibit bits. However, when this bit width is expanded, the possibility of including an operation instruction bit also increases. When the delimited mask vectors include operation instruction bits, the same processing as in the first conventional example is performed.

On the other hand, by reducing the dividing bit width, it is possible to increase the possibility that the divided mask vectors do not include operation instruction bits. However, there is a drawback that the original purpose of reducing the number of times vector elements are read and shortening processing time by not executing invalid operations cannot be achieved.

SUMMARY OF THE INVENTION An object of the present invention is to provide a vector instruction processing device that can reduce the time required to read vector elements and the wasted time of an arithmetic unit.

Means for Solving Problem c] The vector instruction processing device of the present invention includes vector element reading means that is connected to an arithmetic unit that performs vector operations and reads vector elements from a storage device, and a vector instruction processing device that reads vector elements from a storage device. In a vector instruction processing device comprising means for transferring elements to an arithmetic unit and means for reading a mask vector composed of a sequence of mask bits corresponding to each vector element from a storage device, reading of the mask bits corresponds to means for controlling the reading of the vector element in advance of reading the vector element; and means for inhibiting the reading of the vector element corresponding to the mask bit when the mask bit read by the means instructs to inhibit an operation. It is characterized by having

[Effect]

The vector arithmetic processing device of the present invention searches for an arithmetic instruction bit in a mask vector and reads out only the corresponding vector element from the storage device. Since the vector element corresponding to the arithmetic suppression focus is not read out, the data transfer time from the storage device can be reduced.

〔Example〕

FIG. 1 is a block diagram of main parts of a vector instruction processing device according to an embodiment of the present invention.

The mask vector readout circuit 1 includes a selector 11, a mask vector address register 12, and an address addition value register 13.
and an address addition circuit 14. One input of the selector 11 and the address addition value register 13 are each connected to a control section (not shown) via a signal line LO1L1. The output of selector 11 is connected to mask vector address register 12. Mask vector address register 1
2 and address addition value register 13 are connected to address addition circuit 14 . The output of the address adder circuit 14 is connected to the storage device 2 and the other input of the selector 11.

The operation inhibition bit counting circuit 3 includes a selector 31, a mask vector register 32, a priority encoder 33,
shift circuit 34, addition circuit 35, addition value register 36,
A comparator circuit 37 and an operation inhibition bit number register 38 are provided. The output of the storage device 2 is transmitted via the signal line L2.
It is connected to one input of the selector 31. Selector 31
The output of is connected to a priority encoder 33 and a shift circuit 34. Priority encoder 33
The output is connected to one input of the shift circuit 34 and the adder circuit 35 and to the operation inhibition bit number register 38. The output of the shift circuit 34 is sent to the selector 3 via the signal line L3.
1 is connected to the other input of 1. The output of the addition circuit 35 is connected to an addition value register 36. The output of the addition value register 36 is input to the other input of the addition circuit 35 and the comparison circuit 37.
connected to one input of the The output of the address addition value register 13 is connected to the other input of the comparison circuit 37. The output of the comparison circuit 37 is sent to the selector 1 via the signal line L4.
1.31 and the addition value register 36. The operation inhibition bit number register 38 is connected to one input of the multiplication circuit 45 of the vector element address generation circuit 4 via the signal line L5.

The vector element address generation circuit 4 includes vector element distance registers 41, 42, 43, a selector 44, and a multiplication circuit 45.
, selectors 46, 47, and 48, vector element address registers 49, 50, and 51, a selector 52, and an address addition circuit 53. Vector element distance register 41.
42 and 43 are connected to a control section (not shown) via signal lines L6, Ll, and L8, respectively. The outputs of the vector element distance registers 41, 42, and 43 are sent to the selector 4.
Connected to 4. Selector 44 is connected to the other input of multiplication circuit 45 . One input of each of the selectors 46, 47, and 48 is connected to the signal lines L9, LIO, and L
It is connected to the control unit via ll. Selector 46.4
The outputs of 7.48 are connected to vector element address registers 49.50.51, respectively. Vector element address registers 49, 50, 51 are connected to selector 52. Multiplier circuit 45 and selector 52 are connected to two inputs of address addition circuit 53, respectively. The output of the address addition circuit 53 is sent to the selectors 46, 47, . . . via the signal line L12.
48. Further, the output of the address addition circuit 53 is connected to the storage device 5.

Storage device 2 stores mask vectors, and storage device 5 stores vector elements. These storage devices 2.5 may be provided within the same storage device.

In this vector instruction processing device, at the start of a vector instruction,
Signal lines LO, Ll, L6 to I, 11 and selector 11
．． 46.47.48, mask vector address register 12, vector element distance register 41.42, 4
3. Set respective initial values in vector element address registers 49, 50, and 51.

In the mask vector address register 12, the first reading address of the mask vector is set as an initial value. In the address addition value register 13, an initial addition value "0" is set. The value of the mask vector address register 12 and the value of the address addition value register 13 are added to obtain the address of the mask vector stored in the storage device 2.

By specifying this address, the signal m is sent from the storage device 2.
Read the mask vector to L2. This mask vector is passed through the selector 31 to the mask vector register 32.
Store in. After this, the value held in the address addition value register 13 is transferred to the bit length n of the mask vector register 32.
Set to a constant determined by +1. Thereafter, the address addition value register 13 holds this value.

The priority encoder 33 counts the number of operation inhibit bits from the beginning of the mask vector until the first operation instruction bit is found. The shift circuit 34 shifts the mask vector to the left by the number of operation inhibit bits obtained by the priority encoder 33, shifts in rlJ, inverts the first bit, and outputs it. This output is stored again in the mask vector register 32 via the selector 31. Therefore, the output of the priority encoder 33 indicates the interval between operation instruction bits in the mask vector. The output of the priority echoer 33 is stored in the operation suppression bit number register 38.

The addition circuit 35 stores the number of operation inhibit bits obtained by the priority encoder 33 in an addition value register 36.
Add to the value stored in . The addition value register 36 temporarily holds the addition result obtained by the addition circuit 35. Therefore, the addition value register 36 temporarily stores the number of bits of the mask vector. The comparison circuit 37 is
The value set in the address addition value register 13 (constant n+1 determined by the bit length of the mask vector register 32) is compared with the value held in the addition value register 36.

The inter-vector element distance for each vector element is set in the inter-vector element distance registers 41, 42, and 43 via signals &%L6, L7, and L8, respectively.

In the initial state, the initial values of vector element addresses are input to the vector element address registers 49, 50, and 51 from the signal lines L3, LIO, and Lll, respectively.

The selector 44 selects one of these vector element distance registers 41, 42, 43 and outputs it to the multiplication circuit 45. The multiplication circuit 45 multiplies the distance between vector elements inputted from the selector 44 by the number of arithmetic suppression bits inputted via the signal line L5, and generates an address difference.

The selector 52 selects the corresponding vector element address register 4
9. Select 50 or 51.

The address addition circuit 53 adds the address difference to the address of the corresponding vector element to obtain the address where the vector element to be operated is stored. Based on this address, the storage device 5 is requested to read the vector element, and the read vector element is transferred to the arithmetic unit.

At the same time, signal line L12 and selector 46.47
or 48, the value of the corresponding vector element address register 49.50 or 51 is updated.

Let us return to the explanation of the arithmetic inhibition bit counting circuit 3 again.

When the value held in the addition value register 36 is equal to the value set in the address addition value register 13, that is, f
When i+l, the comparison circuit 37 sends the match signal to the signal line L.
Output to 4. This match signal controls selector 11.31 and resets addition value register 36. When the match signal is input, the selector 11 transfers the value output from the address adder circuit 14 to the mask vector address register 12.
Set to . The address addition circuit 14 adds this value to the value of the address addition value register 13 to generate the address of the next mask vector. Based on this address, the storage device 2 outputs a mask vector to the signal line L2. The selector 31 is
When the match signal is input, the mask vector input via the signal line L2 is stored in the mask vector register 32. Similar processing is performed below.

FIG. 2 is an explanatory diagram showing a method of generating addresses of vector elements for operation instruction bits. This mask vector is stored in the mask vector register 32.

Within one vector instruction, the vector element address V)l
By adding a constant vector element distance VI to , the address of the next vector element is obtained. The vector element address corresponding to the first focus of the mask vector will be described as Vl+.

As shown in FIG. 2 (al), it is assumed that the read mask vector with a bit length of n+1 includes an operation instruction bit at bit 3.8, -1n-3.

Let this number be m. Other n −m +' 1
These bits are all operation inhibit focus.

At this time, the address VH3 of the vector element corresponding to the third bit of the mask vector is obtained as VH2=VHO+3 xVI. Here, the coefficient of the vector element distance v■ is ``
3'' is determined by counting the number of operation inhibit bits from the first bit of this mask vector until the first operation instruction bit is found.

Next, as shown in FIG. 2(b), the mask vector is shifted to the left by 3 bits corresponding to the above coefficient, and accordingly, the calculation instruction focus of the 3rd bit is inverted, and the next mask to be used is Let it be a vector.

At this time, logic level "1" is shifted into the last three bits. A coefficient "5" is obtained by counting the number of operation inhibit bits for the shifted mask vector from the beginning until the operation instruction bit is found again. As a result, the address Vl of the vector element corresponding to the 8th bit of the first mask vector is obtained by νHa =VH3+5 xVI.

By repeating the above operation m times, a mask vector as shown in FIG. 2(C) is obtained. This mask vector is obtained by inverting the (n-3)th operation instruction bit and shifting it to the first bit position. By repeating the above operations on this mask vector, the address VH,' of the vector element vHo' = VHn-3+4 xVI is obtained. This address νH0' is the address of a vector element corresponding to the first bit of the next consecutive new mask vector.

The above operations are performed by adding the coefficients obtained from each operation each time, and the resulting added value is the bit length of the mask vector n +
Repeat until it matches 1.

〔Effect of the invention〕

As described above, the vector instruction processing device of the present invention does not read all vector elements from the storage device, but can read only the vector elements whose operation is instructed by the value of the mask bit. Therefore, there is no need to read useless vector elements that do not need to be calculated, and the time required for reading and transferring data from the storage device can be reduced. The present invention has the effect of increasing the speed of vector calculations.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts of a vector instruction processing device according to an embodiment of the present invention. FIG. 2 is an explanatory diagram showing a method of generating addresses of vector elements for operation instruction bits. DESCRIPTION OF SYMBOLS 1...Mask vector readout circuit, 2...Storage device, 3...Arithmetic suppression bit counting circuit, 4...Vector element address generation circuit, 5...Storage device, 1...Selector, 12...Mask vector address register, 13
...Address addition value register, 14...Address addition circuit,
31 river selector, 32...mask vector register,
33... Priority encoder, 34... Shift circuit, 35 River addition circuit, 36... Addition value register,
37 River comparison circuit, 38... Calculation suppression focus number register, 41.42.43... Vector element distance register, 44... Selector, 45 River multiplication circuit, 46.47.
48... Selector, 49.50.51... Vector element address register, 52... Selector, 53... Address addition circuit. Patent applicant NEC Corporation. Agent Patent Attorney Naotaka Ide Q Procedural Amendment May 29, 1985 1. Indication of Case 1985 Patent Application No. 65397 2. Name of Invention Vector Instruction Processing Device Address 5-chome, Shiba, Minato-ku, Tokyo 33 No. 1 Name (
423) NEC Corporation Representative Tadahiro Sekimoto 4, Agent 177-03-928-5673 Address 2-26-18-7-1, Sekimachi Kita, Nerima-ku, Tokyo
Name Patent attorney (7B23) Naoaki Ide 5 5゜Date of amendment order ゛゛'
- ``Voluntary amendment 6, Number of inventions increased by amendment None 7, Subject of amendment 13 B'' Column ``Detailed description of the invention'' of the specification W"'≠) 8, Contents of amendment fl) Description No. Page 8, line 16, “The output of the selector 31 is” [The output of the selector 31 is the mask vector register 32
connected to. The output of the mask vector register 32 is
” he corrected. (2) In the fifth and sixth lines of page 10 of the specification, [the vector element address register 49.50.51 is] is corrected to "the output of the vector element address register 49.50.5 is". (3) On page 10, line 7 of the specification, "the selector 52 is" is corrected to "the output of the selector 52 is". (4) Correct "Mask vector address register 12," on the 19th to 20th lines of page 10 of the specification to "Mask vector address register 12, address addition value register 13,". (5) Correct "signal line 3" on page 13, line 4 of the specification to [signal line L9J. (6) "Initial value" on page 13, line 5 of the specification is corrected to "initial value, that is, the first address of the vector element." (6) In the 6th line of page 14 of the specification, "control and add value register 36" is corrected to "control and at the same time add value register 36".

Claims (1)

[Claims] (1) Vector element reading means connected to an arithmetic device that performs vector operations and reading vector elements from the storage device; means for transferring the vector elements read by this means to the arithmetic device; and vector elements from the storage device. A vector instruction processing device comprising: means for reading a mask vector consisting of a string of mask bits corresponding to an element; 1. A vector instruction processing device comprising: means for inhibiting reading of a vector element corresponding to a mask bit when a mask bit read by the mask bit instructs to inhibit an operation.