JPS6125079A - Address counter testing circuit - Google Patents

Abstract

PURPOSE:To perform a testing in a short time by a method wherein a plurality of counters is operated to count independently of each other and a carry signal output enable braking is operated as a ripple carry counter to control the counting operation of other counters. CONSTITUTION:This circuit is made up of a riplle carry synchronous type address counter 1 comprising 4 bit counters 51-54 and an address switching circuit 6, a counter control circuit 2 which make the cunter 51 or the like perform a independent integration by feeding a clock or controls the counting of the counter 51 by an external signal, a carry signal or the like and an address presetting circuit 3 for outputting a preset value to the counter 1. With such an arrangement, the counter 51 or the like integrates clocks one at a time upto the first carrier signal output after reset. Following the outputting of the carrer sibnal, the counter 51 or the like indicates an independing counting according to an application state to a load terminal in the control circuit 2 and a signal from the circuit 3 and thus, a testing is possible for the outputting of normal carrier signal and the normal counting function of clocks which follows.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a test circuit for an address counter, and more particularly to a test circuit for confirming and checking all functions of an address counter that generates and outputs address signals to a digital memory circuit.

Conventional technology and its problems Digital delay circuits used to delay digital data by a desired time in reverberant sound adding devices, etc., use digital memory circuits (for example, 64-bit dynamic random memory circuits) to obtain the delay time. ·access·
It has a memory (D, RAM)') and an address control circuit for this digital memory circuit.

The above address control circuit has a digital memory circuit of 64. In the case of a k-bit D RAM, for example, it is composed of a ripple carry synchronous address counter consisting of four 4-bit programmable counters, so the number of counter operation steps is as large as 65,536. Furthermore, with the combination of 5-bit preset counters, the total number of counting operation steps is 2,097,152.
(= 32 x 65536) ways.

For this reason, simply operating this address counter to test its counting operation and whether the preset value has been loaded correctly is extremely uneconomical in terms of the test program and time required, resulting in high production costs. There was a point.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a test circuit for an address counter that solves the above problems by controlling the counting operations of other counters using the carry outputs of a plurality of counters constituting the address counter. .

Problems to be Solved by the Invention FIG. 1 is a block diagram showing the configuration of the circuit of the invention. In the figure, address counter 1 is a ripple carry Domei type address counter consisting of a plurality of counters.
Send address signal.

The counter control circuit 2 brings all of the plurality of counters in the address counter 1 into a countable state by supplying an external test signal, and also supplies a clock to cause these plurality of counters to perform cumulative counting simultaneously and independently of each other. Then, when the carry signals are output from the plurality of counters, the counter control circuit 2 stops supplying the external test signal and transfers the output carry signals of each of the plurality of counters to the enable terminals of other counters without overlapping each other. After supplying the test signal to a countable state, make the clock count by one, and supplying a test signal again to make it a counting state,
Thereafter, a plurality of counters are made to integrate and divide simultaneously and independently from each other until a carry signal is outputted.

The address preset circuit 3 outputs the preset value of the box 1 to the address counter 1 for a period of time after resetting the plurality of counters constituting the address counter 1 until the first carry signal is output, and from the time when the first carry signal is output to the next one. The second preset value is output to the address counter 1 within a period until the carry signal is output.

In the working address counter 1, during the period from when the plurality of counters composing it output the first carry signal after being reset, the clocks are integrated and counted one by one at the same time, that is, independently from each other. It is possible to test whether the counter can properly count clocks. Then, the address counter 1 is supplied with the second preset value within a period from when the plurality of counters output the first carry signal until the next carry signal is output, and when the counters output the carry signal, the second preset value is supplied. Since the second preset value is loaded, it is possible to test whether the preset system operates normally by checking whether the preset value is the predetermined value related to the second preset value when the second carry signal is output. can. Hereinafter, the present invention will be described in more detail along with examples.

Embodiment FIG. 2 shows a circuit system diagram of an embodiment of the circuit of the present invention. In the figure, the same components as in FIG. 1 are denoted by the same reference numerals. In FIG. 2, the address counter 1 consists of four 4-bit counters 5I-54 and an address switching circuit 6. The counter 5I is always enabled for counting operation.

The counter 54 receives 4 bits of the 5-bit address signal output from the address preset circuit 3 in parallel to its data input terminal (preset input terminal).
When a high-level carry signal is output from the carry terminal OA, the carry signal is applied to the load terminal LD through the inverter 7, so that this 4-bit value is loaded. Further, the counter 53 is supplied with the remaining 1 pit of the 5-bit address signal output from the address preset circuit 3 only to the data input terminal DD of the most significant bit among its data input terminals DA to DO, and 3-bit data input terminals DA to I
) A low level signal is always applied to C.

The address switching circuit 6 is supplied with 4-bit parallel output signals from each of the counters 51 to 54.
The 4-bit parallel output signals of counters 53 and 54 are collectively selected and output in 8-bit parallel as 8-bit column address signals AO to A7, and the 4-bit address signals of counters 53 and 54 are collectively output as 8-bit row address signals Al to A7. As A7, 8 bits are switched and output in parallel. That is, the address signal △0
.about.A7 are outputted alternately as a row address signal and a column address signal.

The counter control circuit 2 also includes a two-man OR circuit 9 in which the test signal input to the input terminal 8 is supplied to one input terminal.
．． 10 and 11, and a two-person NAND circuit 12 to which a high-level signal is applied to one input terminal. OR
Each output terminal of circuits 9.10 and 11 is connected to a counter 52.5.
3 and 54, respectively.

Furthermore, each carry terminal C of counter 5+, 52.53
A is connected to the other input terminal of the OR circuits 9, 10.11, and the carry terminal CA of the counter 53 is connected to the NAN
It is also connected to the other input terminal of the D circuit 12.

Next, to explain the test operation, first, a high level test signal enters the input terminal 8, and the OR circuit 9.10.1
1 to each enable terminal of the counters 52 + 53 + 54 to enable counting. Further, as described above, the counter 51 is always in a countable state. At the same time, the first preset value is output from the address preset circuit 3, a signal with all 4 bits at a low level is supplied to the data input terminal of the counter 54, and a 1-bit signal at a low level is supplied to the data input terminal of the counter 54.
is supplied to the most significant bit terminal DD of the data input terminal. In this state, a low level reset signal enters the input terminal 13 and is applied to each reset terminal of the counters 51 to 54 to reset them. As a result, the value (count value) of the output signal of each of the 4-bit output terminals of the counters 51 to 54 becomes 0'' in hexadecimal notation (hereinafter, the value in hexadecimal notation will be indicated by ''). .

Next, one clock enters the input terminal 14, is applied to each clock terminal of the counters 51 to 54, and is counted independently of each other.

Therefore, the count values of counters 51 to 54 are each it 1
It becomes u. Thereafter, in the same way as above, when a high level test signal is input to the input terminal 8 and the first preset value is output from the address preset circuit 3, each time a clock signal is input. Counter 5I~
The count value of 54 increases by 1 (I II), and when a total of 16 clocks are received (the 16th time when the clock rises from low level to high level), the counters 51 to 54 go high level. At the same time, the input of the test signal to the input terminal 8' is stopped, and the input terminal 8 becomes low level.

The output carry signal of the counter 51 is applied to the enable terminal of the counter 52 through the OR circuit 9 to enable counting. Further, each output carry signal of the counters 52 and 53 is sent to the counter 53 through an OR circuit 10 and 11.
．． 54 enable terminals to enable counting.

Further, the output carry signal of the counter 53 is supplied to the NAND circuit 12, and as a result, a low level signal is applied from the NAND circuit 12 to the load terminal of the counter 53, so that the counter 53 is loaded with a value of O''. Also,
Counter 54 is loaded with the value "0" because its output carry signal is applied to its load terminal through inverter 7. Also, when the 16th clock next falls from high level to low level, counters 51 and 5
2 performs counting and the output count value becomes "O". In this way, when the 16th clock comes in, each of the counters 5I-54 normally outputs a carry signal, and when it is supplied to a predetermined other counter, the counters 51-54
Each of the output count values becomes 1 (OII), and the output of the carry signal is stopped.This makes it possible to test whether the carry signal is being output normally. It is possible to test whether or not the clock is counting normally by checking whether the counters 51 to 54 are incrementing by II III during the period from the first clock to the fifteenth clock.

Next, when the 17th clock comes in, a high level test signal comes in to the input terminal 8 again, and the address preset circuit 3 outputs a signal with all 5 bits at a high level as the second preset value. do. As a result, each output count value of the counters 51 to 54 is II I 11
becomes. Thereafter, in the same way as above, in the high-level test signal input state, the argument values of the counters 51 to 54 increase by 1'' each time a clock is input to the input terminal 14, and the 31st clock is incremented by 1''. At the time of entry, each count value of the counters 51 to 54 becomes "F".

Next, when the 32nd clock rises from the low level to the high level, the input of the test signal to the input terminal 8 is stopped, and the high level "carry signal" is output again from the counters 51 to 54. Ru. As a result, the counters 5+, 5
2. Counter 52 by each output carry signal of 53
, 53, and 54 are respectively enabled for counting, and the counters 53 and 54 are respectively loaded with 1 bit and 4 bits of the second preset value by their own carry signals.

Since all 5 bits of the second preset value are at high level, the 4-bit data input terminal of the counter 54 is “
F'' will be input, and 4 of the counter 53 will be input.
A high level is applied to the most significant bit input terminal of the bit data input terminals. Therefore, when the 32nd clock falls from high level to low level, the respective counts of counters 51 and 52 are both '0''.
Therefore, the count value of the counter 53 is l811. The count value of the counter 54 becomes "FIT. Therefore, depending on whether the count values of the counters 51 to 54 reach the predetermined value due to the input of the 32nd clock, the output from the address preset circuit 3 and its output terminal is determined. It is possible to test whether the transmission path leading to the data input terminals of the counters 53 and 54 is normal or not, and to test whether or not it is preset by the carry signal.This completes the test.In other words, this embodiment Now, all functions of address counter 1 can be effectively tested in a total of 33 steps, including the initial reset of counters 51-54.

Note that the address preset circuit 3 may switch to the second preset value at any time within the period from the time when the first carry signal is output to just before the next carry signal is output. Further, by keeping the input terminal 8 at a low level at all times, the address counter 1 performs normal operation.

Effects of the Invention As described above, according to the present invention, a plurality of counters constituting an address counter are operated independently of each other, and then the carry signal output enable control is operated as a ripple carry counter, and each clock input It has features such as being able to perform all functions of the address counter effectively and in a short time based on the change pattern of the count value of each counter every time the carry signal is output, the count value when the second carry signal is output, etc. It is something.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the circuit of the present invention. DESCRIPTION OF SYMBOLS 1...Address counter, 2...Counter control circuit, 3...Address preset circuit, 51-54...
4-bit counter, 6...address switching circuit, 8...
・External test signal input terminal, 9 to 11...OR circuit,
12...NAND circuit, 13...Reset signal input terminal, 14...Clock input terminal.

Claims (1)

[Claims] A ripple carry synchronization type address counter consisting of a plurality of counters, and all of the plurality of counters constituting the address counter are enabled to count by an external test signal, and each clock is integrated and counted simultaneously and independently of the other. When a carry signal is output from a plurality of counters, the supply of the test signal is stopped, and the output carry signals of each of the plurality of counters are supplied to the enable terminals of other counters without duplication to enable counting. After that, count one clock, and
A counter control circuit that supplies the test signal again to enable counting, and thereafter causes the plurality of counters to perform cumulative counting simultaneously and independently from each other until the next carry signal is output, and a reset of the plurality of counters. After that, the first preset value is output to the address counter during the period until the first carry signal is output, and the second preset value is output within the period from the time when the first carry signal is output until the next carry signal is output. 1. A test circuit for an address counter, comprising an address preset circuit that outputs a value to the address counter.