JPS61250728A - Function module - Google Patents

Abstract

PURPOSE:To improve the general-purpose application and processing efficiency by coupling freely between unit function modules and a unit function module and a common bus with a microprogram. CONSTITUTION:Plural two-way common buses (data buses) A, B,...N are provided, a data select circuit 2 is provided to the input port of the function module (unit function module) 1 such as ALU or register and a data distribution circuit 3 is provided at the output port side. The microprogram controls the data select circuit 2 and the data distribution circuit 3 so as to connect the input/ output data of the unit function module 1 to any of plural two-way common buses A, B,...N.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial application field B. Summary of the invention C Conventional technology D. Problem that the invention aims to solve E. Means to solve the problem (Figure 1) F. Effect G Example G. Explanation of basic function modules (Figures 1 and 2) G. Specific example of basic functional module (Fig. 3, fig.

(Figure 4) Explanation when ALU is used as a G3 unit function module (Figure 5) Explanation when a multiplier is used as a G41i function module (Figure 6) Configuring a processor using G5 basic function modules (Figures 7 and 8) Explanation of the configuration and operation of the conventional G6 processor (Figures 9 and 10) Explanation of the processor that further expands the G7 basic function module (Figure 11) ) Effects of the Invention A: Industrial Application Field The present invention relates to a functional module suitable for use in signal processing processors such as image processing and microprogram-controlled processors such as data flow computers.

B. Summary of the Invention The present invention relates to a functional module suitable for use in signal processing processors such as image processing and microprogram controlled processors such as data flow computers, and in particular has a plurality of bidirectional common buses (data buses), By providing a data selection circuit on the input port side of the unit function module and a data distribution circuit on the output port side, and controlling the data selection circuit and data distribution circuit with a microprogram, the input and output data of the unit function module can be transferred to both sides. It can be freely connected to any of the directional common buses, which increases the degree of freedom in the connection relationship between functional modules, improves the symmetry of the processor architecture, and optimizes the instruction set. This eliminates the idiosyncrasies (specialities) between functional modules that would otherwise occur when a processor is integrated into a processor, thereby improving the data processing efficiency of the processor.

C. Conventional technology For example, when using a microprogram-controlled processor as an image processing processor, there are The coupling relationship or the coupling relationship between the functional modules and the internal bus is fixed, and the coupling structure is fixed at the design stage so that it is suitable for the execution of instructions processed by the processor. This is because the coupling structure is generally designed to be suitable for frequently used instruction sets.

However, architectures that are optimized for specific instructions often lack symmetry, and the coupling structure between each functional module and between each functional module and the internal bus is different and specialized for each processor, so the hardware It is difficult to create a general-purpose language using a microprogram that is closely related to the program (and it has become difficult to create a general-purpose language due to the specialization and asymmetry of the coupling structure).

In order to increase the versatility of processors, WCS (Writable Control), which allows microprograms to be freely rewritten to support a variety of extended instructions, has traditionally been used.
ol 5tore) technology is used, or general-purpose [I HP (Univ
er-sal Ho5t Processor) has been developed.・D Problems to be Solved by the Invention However, even if such WC8 technology and UHP technology are used, when looking at them at the functional module level, there are problems between the functional modules. The coupling structure and the coupling structure between function modules and internal buses are still fixed and do not necessarily pass through to the instructions to be processed, resulting in poor architectural symmetry (and IS systems that target a specific instruction set). P
(Instruction Set Process
It has the disadvantage of lower processing efficiency than other methods such as ``SOR''.

Therefore, the present invention improves the symmetry of the architecture and improves the processing efficiency by configuring the coupling structure between functional modules and between the functional modules and the internal bus without fixing them.

E. Means for Solving the Problems In order to solve the above-mentioned problems, the present invention uses a plurality of bidirectional common buses (data buses') A as shown in FIG.
, B, ...N, and has functional modules such as ALU and registers (hereinafter referred to as unit functional module) 1
A data selection circuit 2 is provided on the input port side of the unit, and a data distribution circuit 3 is provided on the output port side.The data selection circuit 2 and the data distribution circuit 3 are controlled by a microprogram, and a plurality of input/output data of the unit function module 1 are provided. It is possible to connect to any of the bidirectional common buses A, B, . . . The final functional module configured as shown in FIG. 1 will be referred to as the basic functional module 10 hereinafter.

F If a data selection circuit 2 and a data distribution circuit 3 are provided on the input and output port sides of the action unit function module 1, and these are controlled by a microprogram, the unit function module 1
The input ports and output ports of
,... can be connected to any of them. Therefore, even if a plurality of basic function modules l having the configuration shown in FIG. 1 are connected to the common buses A, B, etc. as shown in FIG.
Alternatively, by individually controlling the data distribution circuit 3 using the microphone 9 program, the required basic function modules 10A, 10B, . . . can be bidirectionally coupled.

This provides architectural symmetry and improves its processing efficiency.

G Example 01 Description of Basic Functional Module The functional module (basic functional module) 10 according to the present invention will be described in detail with reference to FIG. 1 and the following.

FIG. 1 is a diagram for explaining the outline of a basic functional module 10 according to the present invention, and the unit functional module 1 refers to the above-mentioned ALU, register, multiplier, etc. A data selection circuit 2 is provided on the input port side of the unit function module 1, and a bidirectional common bus (
data bus), and a data distribution circuit 3 is provided on the output port side to connect to a plurality of common buses A and B.
,... is connected to.

The data selection circuit 2 and the data distribution circuit 3 each have data selection and data distribution controlled by a microprogram. That is, by controlling this data select circuit 2 with a microprogram supplied thereto, the input ports of the unit function module 1 are connected to a common bus A, which has a plurality of input ports.

It is connected to any of the buses B, . . . , and the selected data is supplied to the unit function module 1.

Similarly, data obtained at the output ports of the unit function module 1 is transferred to the common buses A, B, etc. under the control of a microprogram supplied to the data distribution circuit 3.
・This allows output data to be transferred to any common bus.

FIG. 2 is a diagram showing a connection relationship when a desired processor 5 is configured by using a plurality of basic function modules IO shown in FIG.
, IOB, .

Each of the basic function modules IOA to ION is provided with a data selection circuit 2 and a data distribution circuit 3 as shown in FIG. -Transfer and receive data between IONs via common bus A-
Data transfer can be performed without worrying about the direction of data transfer via D.

02 Specific Example of Basic Function Module Now, FIG. 3 shows an example of a specific configuration of the basic function module 10 shown in FIG. 1. However, in this example, for convenience of explanation, three common buses are used.

The A-C buses are connected to the data select circuit 2 via buffer circuits 1iS11A to IIC each functioning as an I10 port.
and is connected to the data distribution circuit 3.

The buffer circuit 11A has a ml buffer 12A that functions as an input port and a second buffer 13A that functions as an output port, and a 3-state buffer is used as the second buffer 13A.

The other buffer circuits 11B and IIC are similarly configured.

The data on each bus that has passed through the first buffers 12A to 12C is transferred to the three buffers 15A that constitute the data select circuit 2.
~15C. These buffers 15A to 15C
In both cases, a 3-state buffer is used. The output states of the buffers 15A to 15C are controlled based on a signal obtained by decoding a selection signal (2-pin data) supplied to a terminal 16 by a decoder 17. The selection signal is controlled by a microprogram.

The data of G1 selected by the buffers 15A to 15C is supplied to the input port of the unit function module 1.

Data output from the unit function module 1 is supplied to the data distribution circuit 3 via its output port. That is, the output data is once bordered by the latch circuit 18 that constitutes the data distribution circuit 3, and the latch data output at a predetermined timing is sent to the three buffers 19A to 19.
Commonly supplied to C. Multiple buffers 19A to 19C
In each case, three-state buffers are used, and one or more of the buffers is controlled to be active by an output selection signal supplied to them via the terminal 20, and the output is supplied to the second buffers 13A to 13c. be done.

The output data of the unit function module 1 is supplied to the input port of the unit function module 1 via the fourth buffer 21 provided in the data distribution circuit 2 as required.

The output states of the buffers 21 provided in the launch circuit 18 and the data select circuit 2 are each controlled by a microprogram.

Here, as shown in FIG. 2, when a plurality of basic function modules 10 are connected to a common bus, the second buffers 13A to 13G select a necessary basic function module and Functions as a control buffer to transfer output data from functional modules to the required bus. Further, the buffers 19A to 19C provided in the data distribution circuit 3 are for controlling the data output of the distribution circuit itself when a plurality of data distribution circuits 3 are provided for the unit function module 1.

For example, when a two-man power, two-output type unit function module 1 is used as shown in FIG. Data distribution circuits 3A and 3B are connected respectively. and the first buffer 1
Each data of 2A to 12C is sent to data select circuits 2A and 2.
The output data of the data distribution circuits 3A and 3B are supplied in parallel to the second buffers 13A to 13C.

When the basic function module 10 is configured in this way, it is necessary to select between the basic function modules as shown in FIG. 2 and to select the output data of either the data distribution circuits 3A or 3B. As described above, the second buffers 13A-13C and the buffer 1 for data distribution
This is because it is necessary to provide 9A to 19C in series.

Description of the case where ALU is used as the 0B unit function module FIG. 5 is a block diagram showing an example of the case where the present invention is applied to an ALU. Therefore, the ALU is used as the unit function module 1.

Common bus A obtained via first buffers 12A to 12C
-C is supplied to the first and second data select circuits 2A and 2B, the input data selected by each is supplied to ALUIA as a unit function module, and the output data from which the operation result is obtained is stored in the register. 23 to the data select circuits 2A and 2B, and
The signal is supplied to the second buffers 13A to 13C via the latch circuit 24.

In this configuration, the data distribution circuit 3 is not provided on the output port side of the ALUIA, but this is because the ALUIA is a one-output type, so the data distribution circuit 3 can be replaced with the second buffers 13A to 13C. It is. Therefore, the second buffers 13A to 13C function as the data distribution circuit 3.

Explanation of the case where a multiplier is used as a G4 unit function module FIG. 6 shows a case where the present invention is applied to a multiplier, and the multiplier IB as a unit function module is a two-manpower, two-output type. Therefore, as shown in the figure, a pair of data select circuits 2A and 2B are provided on the input port side of the multiplier IB.
A pair of data distribution circuits 3A and 3B are provided on the output port side, respectively.

The data distribution circuit 3A outputs the upper bits of the multiplication output data (in the case of 16-bit data, the upper 8 bits).
The other data distribution circuit 3B handles the lower bits (similarly, the lower 8 bits).

The configuration of the basic function module 10 when a two-bottom RAM is used as a unit function module is the same as that when a multiplier is used, so a description thereof will be omitted.

05 Explanation of the configuration and operation when configuring a processor using basic function modules FIG.
This is an example in which a microprogram-controlled processor 5 is configured using a multiplier 10B and a register IOC, and the following is how to use this processor 5 to perform, for example, a multiplication process. FIG. 8 is a timing chart showing the processing steps broken down into data buses.

For convenience of explanation, the calculation process of X2+Y2+22 will be explained. As a premise of the processing, it is assumed that these data x, y, and z are all stored in the register 10C.

First, data X read from the register IC provided in the basic function module 10C is sent to the data select circuit 2A of the multiplier IB via the A bus.

2B (FIG. 6) (step 1), both of them are controlled to be in an operating state, and the respective data X and X are calculated by the multiplier IB (step 2). In step 2, data Y is transferred from the register IC to the A bus, and in step 3, data Y is transferred to the multiplier IB, and multiplication processing of Y2 is executed. The multiplication data of X2 calculated by multiplier IB in this step 3 is stored in basic function module IOB.
The multiplication data X2 is transferred to the C bus via the data distribution circuits 3A and 3B in the basic function module IOA, and the transferred multiplication data X2 is supplied to the data selection circuit 2A of the basic function module IOA. In step 3, data Z is further transferred from register IC to A.
The signal is transferred to the bus and fed to the multiplier IB.

In step 4, the multiplication output Y2 is supplied to the other data select circuit 2B in the basic function module IOA via the B bus, and both data X2 and Y2 are sent to the ALU.
Addition processing is performed in IA. The addition output X2+Y2 is supplied to one data selection circuit 2A via the register 23 shown in FIG. 5, and the multiplication output Z2 transferred to the B bus is supplied to the other data selection circuit 2B in the basic function module IOA. By doing so, in step 5, in ALUIA, X 2 + Y 2
A final addition process of +22 is executed, and its output is transferred to the C bus and stored in an external main memory provided in the processor 5, for example.

G6 Configuration of conventional processor and explanation of its operation When such arithmetic processing is performed by a conventional processor, the process is as follows.

Figure 9 shows the circuit configuration of a conventional processor, with ALUI
A, multiplier IB, and register IC are connected as shown in the figure, and four buses A to D are required as data buses. This is because these plurality of unit function modules 1 have no symmetry.

Now, the processing operation will be briefly explained using the timing chart of the arithmetic processing shown in FIG.

First, in step 1, from the register IC to bus B.

The data X and X are transferred to the multiplier IB via C and multiplication processing is executed, and the multiplication output X2 is supplied to the register IC via the D bus (step 2). In the same step 2, data Y and Y are transferred from register IC to multiplier IB using B and C buses. Similarly, in step 3, data Y.

Multiplication processing of Y is executed and the multiplication output Y2 is taken into the register IC via the D bus. At this time, the multiplier l
B has data Z from register IC.

Z is imported.

In step 4, the multiplication process of data Z is executed, and at the same time, the multiplication outputs X2 and Y2 stored in the register IC are
13. , and is transferred to the ALUIA via the bus A, and the addition process is executed in step 5. The addition result is input to the register IC via the A bus (step 6).

In step 6, the multiplication output Z stored in the register IC
2 and addition output (X2+Y2) are sent to A via B and C buses.
This is transferred to the LUIA and subjected to addition processing in step 7, thereby completing the target arithmetic processing, that is, the arithmetic processing of X 2 + Y 2+ 22 .

In this way, the configuration of the conventional processor 5 shown in FIG. 9 in which the connections between unit function modules and between the unit function modules and the data bus are fixed, and the configuration of the conventional processor 5 shown in FIG. It is easy to understand that with the configuration of the processor 5 shown in FIG. 7, in which the connections between the two can be freely selected by a microprogram, the calculation processing time can be shortened even with the simple calculation processing described above.

Description of a processor in which the G77 functional module is further expanded FIG. 11 shows an example in which the present invention is applied to a processor 5 having a hierarchical bus structure.

In this case, a plurality of basic functional modules 10A.

10B, . . . are further made into functional modules as one set. Such a functional module is called a multifunctional module 40. Here, the multifunction module 4
The data transfer buses (three in the figure) a, b, and c in 0 are sub-common buses, and multiple multifunction modules 40A,
40B, old...
The main common buses A, B, and C and the sub common buses a, b, and c are interconnected by bidirectional buffers 42A to 42C.

Even in this configuration, the basic function modules 1 and the multifunction modules 40 can be freely connected by a microprogram.

〔Effect of the invention〕

As explained above, according to the present invention, unit function modules and unit function modules and a common bus can be freely connected by a microprogram.
It has at least the following features compared to the conventional one.

First, as mentioned above, mutual coupling relationships can be changed freely by microprograms via multiple common buses, which improves the symmetry of the architecture of the constituent processors and improves the instruction set. In the case of optimization, special characteristics (specificity) are reduced, and versatility and processing efficiency can be improved.

Second, since the various coupling relationships described above can be freely changed using a microprogram, a processor can be configured simply by determining the number and type of required functional modules and the number of common buses.

Therefore, the design of the processor is easy, the symmetry and specificity of the architecture are improved, and it is also easy to create microprograms and general-purpose programming languages.

Thirdly, since a free connection structure between functional modules can be set through a plurality of common buses, communication efficiency between functional modules is high, various pipeline processing is possible, and double-length data can be handled efficiently.

Fourth, by increasing the number of common buses and the number of functional modules, performance is improved and VLSI implementation is possible.

[Brief explanation of drawings]

Figure 1 is a diagram showing the conceptual configuration of this invention, Figure 2 is a diagram showing its extended configuration, Figures 3 and 4 are configuration diagrams each showing a specific example of this invention, and Figure 5 is a unit function. FIG. 6 is a configuration diagram of a basic function module showing an example of using an ALU as a module and a multiplier. FIG. 7 is a configuration diagram of an example of a processor using the basic function module.
The figure shows the timing chart of the calculation process.
The figure shows an example of a case where the configuration of FIG. 7 is configured with conventional functional modules, FIG. 10 shows a timing chart thereof, and FIG. 11 shows an example of a case where the configuration of FIG. 7 is further expanded. FIG. 1 (IA, IB, ...) are unit function modules, 2 (2A, 2B) are data selection circuits, 3
(3A, 3B) are data distribution circuits, 10 (IOA, IOB. ...) are basic function modules, A, B, C...
..., a, b, c, ... are common buses, II
A-11C is a buffer circuit, and 5 is a processor. Figure 6

Claims (1)

[Claims] It has a plurality of bidirectional common buses, a data selection circuit is provided on the input port side of the unit function module, and a data distribution circuit is provided on the output port side, and the data selection circuit and data distribution circuit are controlled by a microprogram, A functional module configured such that input/output data of the unit functional module can be connected to any of the plurality of bidirectional common buses.