JPS61247227A - Capacitor charging circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention relates to a capacitor charging circuit for initially charging a capacitor that is

[Prior art and its problems]

When converting DC power into AC power using a voltage source inverter using transistors as a power conversion device, for example, a DC power source is connected to the DC input side of the inverter, and a large capacitance capacitor is connected in parallel to the DC power source. . When operating a transistor inverter, this capacitor must first be charged, but if the full voltage is applied directly to this capacitor, a large charging current will flow, which is inconvenient, so it is necessary to take some measure to suppress the charging current. However, it is also necessary that no power loss occurs due to this charging current suppression measure while the inverter is operating. FIG. 4 is a circuit diagram showing a conventional example of a capacitor charging current suppression circuit, in which DC power from a DC power supply consisting of an AC current 12, a power switch 11, and a rectifier 13 is converted into power via a capacitor 30. A case is shown in which a transistor inverter 40 as a device is fed. That is, in FIG. 4, a current limiting resistor 21 and a short circuit switch 25 are installed between the DC output side of the rectifier 13 and the capacitor 30.
When the DC voltage is zero, the short circuit switch 25 is left open. When the power switch 11 is turned on in this state to generate DC voltage, the capacitor 30 has a current limiting resistor. A charging current limited by 21 will flow. In this way, the capacitor 30 is gradually charged, and when the charging detection circuit 26 detects that the voltage has reached the vicinity of the DC power supply voltage, the short circuit switch 25 closes and shorts the current limiting resistor 21. No power loss occurs when transistor inverter 40 is operating. However, the conventional circuit shown in FIG. 4 requires a short circuit switch 25 and a charge detection circuit 26, and thus has the drawback of requiring a large number of components (which hinders miniaturization of the device and increases the cost).

[Purpose of the invention] SUMMARY OF THE INVENTION An object of the present invention is to provide a simple capacitor charging circuit with a small number of parts and capable of effectively suppressing capacitor charging current. [Key points of the invention]

This invention utilizes the saturation of the reactor, and this reactor is connected in parallel to a current limiting resistor that limits the charging current of the capacitor, so that the iron core of the reactor is saturated near the completion of charging of the capacitor. This prevents power loss from occurring due to current resistance.

[Embodiments of the invention]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In FIG. 1, DC power from a DC power source 10 is supplied to a transistor inverter 40 as a power conversion device via a power switch 11 and a capacitor 30, but a charging current control device is installed on the power source side of the capacitor 30. A parallel circuit of a current limiting resistor 21 and a reactor 22 as means is connected. When the power switch 11 is turned on prior to operation of the transistor inverter 40, most of the current that charges the capacitor 30 flows through the current limiting resistor 21 because the reactor 22 is not yet saturated. The peak value of charging current is suppressed. The capacitor 30 is gradually charged according to a time constant determined by the capacitance of the capacitor 30 and the resistance value of the current limiting resistor 21, and the iron core of the reactor 22 is rapidly saturated near the completion of charging. The current that was flowing through the current limiting resistor 21 before the reactor 22 was saturated will now flow through the reactor 22 as the iron core is saturated, and the current that was flowing through the current limiting resistor 21
Both ends of will be shorted. Therefore, while the transistor inverter 40 is operating, no current flows through the current limiting resistor 21.
Therefore, no power loss occurs. FIG. 2 is a circuit diagram showing a second embodiment of the present invention,
Similar to the embodiment shown in FIG. 1, DC power from a DC power supply 10 is supplied to a transistor inverter 40 as a power conversion device via a power switch 11 and a capacitor 30. . In this second embodiment, the charging current suppressing means provided on the power supply side of the capacitor 30 is a current limiting resistor 21. A reactor 22 is connected in parallel to this series circuit. It is the same as the case of the embodiment shown in FIG. 1 that saturation occurs rapidly near completion. Therefore, if the power switch 11 is closed before starting operation, the charging current suppressed via the diode 23 and the current limiting resistor 21 will be transferred to the capacitor 3.
0, and the iron core of the reactor 22 suddenly saturates near the completion of charging, causing the diode 23 and the current limiting resistor 21 to
The series circuit with the transistor inverter 40 is short-circuited by the reactor 22, so that no power loss occurs during the operation of the transistor inverter 40. In the second embodiment shown in FIG.
Even if the power switch 11 is opened after charging is completed, the circulating current flowing from the reactor 22 through the current limiting resistor 21 is blocked by the diode 23, so this circulating current continues to flow for a long time, during which time the magnetic flux of the reactor 22 This can prevent the inconvenience of not being reset. That is, even if the power switch 11 is opened and then turned on again after a very short period of time, the saturation of the iron core of the reactor 22 is canceled by the diode 23, so there is no risk of excessive current flowing when the power switch 11 is turned on again. FIG. 3 is an operating waveform chart in the embodiment shown in FIG. 1 or 2, in which FIG. The current flowing through I 1
1, FIG. 3(c) shows the change in the current flowing through the reactor 22, and FIG. 3(d) shows the change in the voltage E4° applied to the transistor inverter 40. In FIG. 3, when the power switch 11 is closed at time t, a current I□ whose maximum value is limited by the resistance value of the current limiting resistor 21 flows, and as it gradually decreases according to a predetermined time constant, the inverter The applied voltage E0 of 40 gradually increases, but during this time the reactor current 111 is almost zero.
It is shown that i is zero and current is supplied from the reactor 22, that is, the resistor 21 is short-circuited by the reactor 22.

【Effect of the invention】

According to this invention, by utilizing the characteristic that the iron core of the reactor is rapidly saturated, the reactor connected in parallel to the charging current suppressing means is short-circuited when the capacitor charging is completed, so that the number of parts is reduced. It is possible to realize a capacitor charging circuit with a simple structure and no power loss during energization.Furthermore, this reactor exhibits high impedance for high-frequency signals, so the power converter that is the load This has the effect of preventing high-frequency noise from leaking to the power supply side through this reactor, except for a slight leakage to the power supply side through the current-limiting resistor.In addition, when operating with a diode connected in series with the current-limiting resistor, Since this diode is in a blocking state when it is in the middle, high frequency noise that slightly leaks through the above-mentioned current limiting resistor can exhibit the effect of making it even more difficult to leak.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the invention, FIG. 2 is a circuit diagram showing a second embodiment of the invention, and FIG. 3 is a circuit diagram showing a second embodiment of the invention. It is an operation waveform diagram. FIG. 4 is a circuit diagram showing a conventional example of a capacitor charging current suppression circuit. 10: DC power supply, 11: Power switch, 12: AC power supply, 13: Rectifier, 21: Current limiting resistor as charging current suppressing means, 22: Reactor, 23: Diode, 25: Short circuit switch, 26: Charging detection circuit, 30: Capacitor,
40: Transistor inverter as a power conversion device. Figure 2

Claims (1)

[Claims] 1) In a circuit in which a parallel circuit of a DC power source and a capacitor is connected to the DC input side of a power conversion device, a charging current suppressing means and a reactor are connected in parallel between the DC power source and the capacitor. A charging circuit characterized in that the circuits are connected. 2) The capacitor charging circuit according to claim 1, wherein the reactor is a reactor that saturates the capacitor near completion of charging. 3) A capacitor charging circuit according to claim 1 or 2, wherein the charging current suppressing means is a resistor or a series circuit of a resistor and a diode.