JPS61247225A - Overvoltage protection circuit - Google Patents
Overvoltage protection circuitInfo
- Publication number
- JPS61247225A JPS61247225A JP8681385A JP8681385A JPS61247225A JP S61247225 A JPS61247225 A JP S61247225A JP 8681385 A JP8681385 A JP 8681385A JP 8681385 A JP8681385 A JP 8681385A JP S61247225 A JPS61247225 A JP S61247225A
- Authority
- JP
- Japan
- Prior art keywords
- alarm
- fuse
- circuit
- semiconductor
- arrester
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Landscapes
- Emergency Protection Circuit Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概要〕
落雷により電子機器１通信機器等の信号線又は電源線に
異常電圧が発生し機器を破壊するのを防ぐ、半導体アレ
スタを用いた過電圧保護回路において、半導体アレスタ
と警報接点警報表示付きヒユーズとを直列に接続したも
のをｎ段構成とし、半導体アレスタが短絡障害となって
も、ｎ回の半導体アレスタのサージ耐量を越えるサージ
流入塩は間断なく十分過電圧に対し保護出来るようにし
て、過電圧保護に対する信頼性を高くし、又半導体アレ
スタの短絡障害はヒユーズの警報接点又は警報表示によ
りすぐ判明するようにし、すぐ交換可能にし、過電圧保
護に対する信頼性を更に高（したものである。[Detailed Description of the Invention] [Summary] In an overvoltage protection circuit using a semiconductor arrester, which prevents abnormal voltage from occurring in the signal line or power line of electronic equipment 1 communication equipment, etc. due to lightning and destroying the equipment, a semiconductor arrester is used. The n-stage structure consists of a fuse with an alarm contact and an alarm display connected in series, and even if the semiconductor arrester experiences a short-circuit failure, the surge inflow salt that exceeds the surge withstand capacity of the semiconductor arrester will be able to withstand the overvoltage without interruption. The short-circuit failure of the semiconductor arrester can be immediately identified by the fuse alarm contact or alarm display, making it possible to replace it immediately, further increasing the reliability of overvoltage protection. This is what I did.
本発明は、落雷により電子機器９通信機器等の信号線又
は電源線に異常電圧が発生し機器を破壊するのを防ぐ、
半導体アレスタを用いた過電圧保護回路の改良に関する
。The present invention prevents abnormal voltage from occurring in the signal line or power line of electronic equipment 9 communication equipment etc. due to lightning and destroying the equipment.
This article relates to improvements in overvoltage protection circuits using semiconductor arresters.
半導体アレスタばサージ耐量を越えるサージ流入により
破壊するが、この時は短絡状態となることが多い。Semiconductor arresters are destroyed by surges that exceed their surge resistance, but in this case they often become short-circuited.
この為上記過電圧保護回路では、この短絡障害を早く検
出出来ると共に交換する迄の無防備をなくし過電圧保護
の信頼性が高いことが望まれている。For this reason, it is desired that the above-mentioned overvoltage protection circuit be able to quickly detect this short-circuit fault, eliminate the need for protection until replacement, and have high reliability in overvoltage protection.
第３図は従来例の過電圧保護回路の回路図である。 FIG. 3 is a circuit diagram of a conventional overvoltage protection circuit.
図中２０は半導体アレスタ、１００は機器、Ｒは抵抗を
示す。In the figure, 20 is a semiconductor arrester, 100 is a device, and R is a resistor.
従来半導体アレスタを用いた過電圧保護回路は、第３図
に示す如く、半導体アレスタ２０と抵抗Ｒとを直列接続
した回路を、機器１００への信号線又は電源線に並列に
接続し、半導体７レスタ２０がサージ耐量を越えるサー
ジ流入により短絡状態になった場合、抵抗Ｒの両端の電
圧を測定することにより、この回路の漏電流を測定する
ことで、半導体アレスタ２０の劣化を判定し短絡障害に
なっていれば交換していた。As shown in FIG. 3, the conventional overvoltage protection circuit using a semiconductor arrester connects a circuit in which a semiconductor arrester 20 and a resistor R are connected in series to a signal line or a power supply line to a device 100, and connects a semiconductor arrester 20 and a resistor R in parallel. 20 becomes short-circuited due to surge inflow exceeding the surge withstand capacity, by measuring the voltage across the resistor R and the leakage current of this circuit, it is possible to determine the deterioration of the semiconductor arrester 20 and prevent a short-circuit failure. If it had, I would have replaced it.
しかしながら、従来の過電圧保護回路では、半導体アレ
スタが短絡障害となった場合、漏電流を測定し、半導体
アレスタの短絡障害を検出し交換する迄、次に発生する
過電圧保護に対し正常な保護がされておらず、過電圧保
護に対し信頼性が低い問題点がある。However, with conventional overvoltage protection circuits, if a semiconductor arrester experiences a short-circuit fault, the leakage current is measured, the short-circuit fault in the semiconductor arrester is detected, and until the semiconductor arrester is replaced, normal protection is not provided against the next overvoltage protection. However, there is a problem that the reliability of overvoltage protection is low.
上記問題点は、過電圧から保護すべき装置に、第１の半
導体アレスタと第１の警報接点付きヒユーズを直列に接
続した回路を電源線又は信号線に並列に接続し、該第１
の警報接点付きヒユーズに、第２の半導体アレスタと第
２の警報接点付きヒユーズを直列に接続した回路を並列
に接続する如く、第ｎ−１の警報接点付きヒユーズに、
第ｎの半導体アレスタと第ｎの警報接点付きヒユーズを
直列に接続した回路を並列に接続し、半導体アレスタを
ｎ段構成にするか又は、
第１の半導体アレスタと第１の警報接点警報表示付きヒ
ユーズを直列に接続した第１の回路、及び第２の半導体
アレスタと第２の警報接点警報表示付きヒユーズと該第
１の警報接点警報表示付きヒユーズの警報接点とを直列
に接続した第２の回路、及び第ｎの半導体アレスタと第
ｎの警報接点警報表示付きヒユーズと第ｎ−１の警報接
点警報表示付きヒユーズの警報接点とを直列に接続した
第ｎの回路の合計ｎ個の回路を、過電圧から保護すべき
装置に並列に接続した本発明の手段によりにより解決さ
れる。The above problem can be solved by connecting a circuit in which a first semiconductor arrester and a first fuse with an alarm contact are connected in series to a power supply line or a signal line in a device to be protected from overvoltage, and
such that a circuit in which a second semiconductor arrester and a second fuse with an alarm contact are connected in series is connected in parallel to the fuse with an alarm contact of the (n-1)th fuse with an alarm contact,
A circuit in which an n-th semiconductor arrester and an n-th fuse with an alarm contact are connected in series is connected in parallel to form an n-stage configuration of the semiconductor arrester, or a first semiconductor arrester and a first alarm contact are provided with an alarm display. a first circuit in which fuses are connected in series; and a second circuit in which a second semiconductor arrester, a second alarm contact, a fuse with an alarm display, and an alarm contact of the first alarm contact and alarm display fuse are connected in series. and an n-th circuit in which the n-th semiconductor arrester, the n-th alarm contact fuse with alarm display, and the n-1 alarm contact of the fuse with alarm display are connected in series, for a total of n circuits. , connected in parallel to the device to be protected against overvoltage, is solved by the measures of the invention.
前者の手段では、第１番目の過電圧サージに対しては、
第１の半導体アレスタが動作し、この半導体アレスタに
サージ耐量を越えるサージの流入があれば、第１の半導
体アレスタは短絡障害となり、第１の警報接点付きヒユ
ーズは溶断し、第２の半導体７レスタが次の過電圧サー
ジに対し機能するようになり、この原理により、ｎ回迄
のサージ耐量を越えるサージ塩の、次々の過電圧サージ
に対して間断なく機能出来るようになり過電圧保護の信
頼性を向上出来る。 又警報接点付きヒユーズの溶断に
より警報接点はオンとなるので、これを用い半導体アレ
スタの短絡障害をすぐ検出出来るため、交換時間が短縮
出来、更に過電圧保護の信頼性を向上出来る。With the former method, for the first overvoltage surge,
If the first semiconductor arrester operates and a surge exceeding the surge withstand capacity flows into the semiconductor arrester, the first semiconductor arrester becomes a short-circuit failure, the fuse with the first alarm contact melts, and the second semiconductor arrester 7 The resistor will now function against the next overvoltage surge, and based on this principle, it will be able to function without interruption against successive overvoltage surges that exceed the surge resistance up to n times, increasing the reliability of overvoltage protection. I can improve. Furthermore, since the alarm contact is turned on when the fuse with the alarm contact is blown, a short-circuit failure of the semiconductor arrester can be immediately detected using this, so that the replacement time can be shortened and the reliability of overvoltage protection can be improved.
後者の手段では、第１番目の過電圧サージに対しては、
第１の半導体アレスタが動作し、この半導体アレスタに
サージ耐量を越えるサージの流入があれば、第１の半導
体アレスタは短絡障害となり、第１の警報接点警報表示
付きヒユーズは溶断し、警報接点はオンとなり、第２の
半導体アレスタが次の過電圧サージに対し機能するよう
になり、この原理により、ｎ回迄のサージ耐量を越える
サージ塩の、次々の過電圧サージに対して間断な（機能
出来るようになり過電圧保護の信頼性を向上′出来る。With the latter method, for the first overvoltage surge,
If the first semiconductor arrester operates and a surge that exceeds the surge resistance flows into this semiconductor arrester, the first semiconductor arrester will become short-circuited, the first alarm contact fuse with alarm display will melt, and the alarm contact will be turned off. The second semiconductor arrester is turned on and becomes functional against the next overvoltage surge. Based on this principle, the second semiconductor arrester is activated against successive overvoltage surges that exceed the surge resistance up to n times. This improves the reliability of overvoltage protection.
又警報接点警報表示付きヒユーズの溶断による警報表示
により、半導体アレスタの短絡障害をすぐ検出出来るた
め交換時間が短くなり、更に過電圧保護の信頼性を向上
出来る。Further, by displaying an alarm by blowing a fuse with an alarm contact alarm display, a short-circuit failure of the semiconductor arrester can be immediately detected, thereby shortening the replacement time and further improving the reliability of overvoltage protection.
ζノ
第１図は本発明の実施例の過電圧保護回路の回路図であ
る。FIG. 1 is a circuit diagram of an overvoltage protection circuit according to an embodiment of the present invention.
図中１１〜ｉｎは半導体アレスタ、Ｆｉｌ−ＦＩｎばＰ
形ヒユーズの如き警報接点警報表示付きヒユーズ、１０
０は機器を示す。In the figure, 11-in is a semiconductor arrester, and Fil-FIn is P.
Fuse with alarm contact alarm display such as type fuse, 10
0 indicates equipment.
第１図では、機器１００への信号線又は電源線に、半導
体アレスタ１１と警報接点警報表示付きヒユーズＦｉｌ
を直列に接続した回路を並列に接続し、該警報接点警報
表示付きヒユーズＦｉｌに、半導体アレスタ１２と警報
接点警報表示付きヒユーズＦ１２を直列に接続した回路
を並列に接続し、該警報接点警報表示付きヒユーズＦ１
２に、半導体アレスタ１３と警報接点警報表示付きヒユ
ーズＦ１３を直列に接続した回路を並列に接続する如く
、半導体アレスタ１ｎと警報接点警報表示付きヒユーズ
Ｆｉｎを直列に接続した回路を並列に接続する迄のｎ段
構成にしである。In FIG. 1, a semiconductor arrester 11 and a fuse filter with an alarm contact alarm display are connected to the signal line or power line to the device 100.
A circuit in which the semiconductor arrester 12 and a fuse F12 with an alarm contact alarm display are connected in series is connected in parallel to the fuse F1 with the alarm contact alarm display, and a circuit in which the semiconductor arrester 12 and the fuse F12 with the alarm contact alarm display are connected in series is connected in parallel. With fuse F1
2, until the circuit in which the semiconductor arrester 1n and the fuse Fin with alarm contact and alarm display are connected in series is connected in parallel, such as the circuit in which the semiconductor arrester 13 and the fuse F13 with alarm contact and alarm display are connected in parallel. It has an n-stage configuration.
従って、第１番目の過電圧サージに対しては、半導体ア
レスタ１１が動作し、この半導体７レスタにサージ耐量
を越えるサージの流入があれば、半導体アレスタ１１は
短絡障害となり、警報接点警報表示付きヒユーズＦｉｌ
は溶断し、半導体アレスタＩ２が次の過電圧サージに対
し毀鮨するようになり、同じ原理によりｎ回迄のサージ
耐量を越えるサージ塩の、次々の過電圧サージに対して
゛ 間断なく機能出来るようになり過電圧保護の信頼
性を向上出来る。Therefore, in response to the first overvoltage surge, the semiconductor arrester 11 operates, and if a surge that exceeds the surge resistance flows into the semiconductor 7 resistor, the semiconductor arrester 11 will be short-circuited, and the fuse with alarm contact alarm display will be activated. Fil
fuses, and the semiconductor arrester I2 begins to fail against the next overvoltage surge. Based on the same principle, it can function without interruption against successive overvoltage surges of surge salt that exceeds the surge resistance up to n times. The reliability of overvoltage protection can be improved.
又警報接点警報表示付きヒユーズの溶断により警報接点
はオンとなるので、これを用い半導体アレスタの短絡障
害をすぐ検出出来るため、交換時間が短縮出来、更に過
電圧保護の信頼性を向上出来る。Furthermore, since the alarm contact is turned on by blowing the fuse with the alarm contact alarm display, short-circuit failure of the semiconductor arrester can be immediately detected using this, so that replacement time can be shortened and the reliability of overvoltage protection can be improved.
第２図は本発明の他の実施例の過電圧保護回路の回路図
である。FIG. 2 is a circuit diagram of an overvoltage protection circuit according to another embodiment of the present invention.
図中１〜ｎは半導体アレスタ、Ｆ１〜ＦｎはＰ形ヒユー
ズの如き警報接点警報表示付きヒユーズ、ｆ１〜ｆｎ−
１は夫々警報接点警報表示付きヒユーズｌアリ鼾との警
報接点、１０ｏは機器を示す。In the figure, 1 to n are semiconductor arresters, F1 to Fn are fuses with alarm contacts such as P-type fuses, and f1 to fn-
1 indicates an alarm contact with a fuse with an alarm display, and 10o indicates a device.
第２図では、機器１００への信号線又は電源線に、半導
体７レスタ１と警報接点警報表示付きヒユーズＦ１を直
列に接続した第１の回路、及び半導体アレスタ２と警報
接点警報表示付きヒユーズＦ２と該警報接点警報表示付
きヒユーズＦ１の警報接点ｆ１とを直列に接続した第２
の回路、及び半導体アレスタ３と警報接点警報表示付き
ヒユーズＦ３と該警報接点警報表示付きヒユーズＦ２の
警報接点ｆ２とを直列に接続した第３の回路、及び半導
体アレスタｎと警報接点警報表示付きヒユーズＦｎと警
報接点警報表示付きヒユーズＦｎ−１の警報接点ｆｎ−
１とを直列に接続した第ｎの回路を並列に接続するｎ段
構成にしである。FIG. 2 shows a first circuit in which a semiconductor 7 arrester 1 and a fuse F1 with an alarm contact alarm display are connected in series to a signal line or a power supply line to the device 100, and a semiconductor arrester 2 and a fuse F2 with an alarm contact alarm display are connected in series. and the alarm contact f1 of the fuse F1 with alarm contact alarm display are connected in series.
and a third circuit in which the semiconductor arrester 3, the fuse F3 with an alarm contact alarm display, and the alarm contact f2 of the fuse F2 with the alarm contact alarm display are connected in series, and the semiconductor arrester n and the fuse with an alarm contact alarm display. Fn and alarm contact Alarm contact fn- of fuse Fn-1 with alarm display
This is an n-stage configuration in which an n-th circuit in which 1 and 1 are connected in series is connected in parallel.
従って、第１番目の過電圧サージに対しては、半導体ア
レスタ１が動作し、この半導体アレスタにサージ耐量を
越えるサージの流入があれば、半導体アレスタ１は短絡
障害となり、警報接点警報表示付きヒユーズＦ１は溶断
し、警報接点ｆ１はオンとなり、半導体アレスタ２が次
の過電圧サージに対し機能するようになり、同じ原理で
、ｎ回迄のサージ耐量を越えるサージ塩の、次々の過電
圧サージに対して間断なく機能出来るようになり過電圧
保護の信頼性を向上出来る。Therefore, in response to the first overvoltage surge, the semiconductor arrester 1 operates, and if a surge exceeding the surge withstand capacity flows into this semiconductor arrester, the semiconductor arrester 1 becomes a short-circuit failure, and the fuse F1 with alarm contact alarm display is activated. fuses, the alarm contact f1 turns on, and the semiconductor arrester 2 comes to function against the next overvoltage surge. Based on the same principle, it can be used against successive overvoltage surges of surge salt exceeding the surge resistance up to n times. It can function without interruption, improving the reliability of overvoltage protection.
又警報接点警報表示付きヒユーズの溶断による警報表示
により、半導体アレスタの短絡障害をすぐ表示出来るた
め交換時間が短くなり、更に過電圧保護の信幀性を向上
出来る。In addition, the alarm display caused by the melting of the fuse with the alarm contact alarm display can immediately indicate a short-circuit failure of the semiconductor arrester, thereby shortening the replacement time and further improving the reliability of overvoltage protection.
以上詳細に説明せる如く本発明によれば、ｎ回迄のサー
ジ耐量を越えるサージ迄の、次々の過電圧サージに対し
て間断なく機能出来るようになり過電圧保護の信頼性を
向上出来又警報接点警報表示付きヒユーズの溶断による
警報表示又は警報接点により、半導体アレスタの短絡障
害をすぐ検出出来、交換時間が短（なり、更に過電圧保
護の信頼性を向上出来る効果がある。As explained in detail above, according to the present invention, it is possible to function continuously against successive overvoltage surges up to n times of surges exceeding the surge withstand capacity, improving the reliability of overvoltage protection, and alarm contact alarm. By displaying an alarm by blowing a fuse with an indicator or by using an alarm contact, a short-circuit failure of a semiconductor arrester can be immediately detected, the replacement time can be shortened, and the reliability of overvoltage protection can be further improved.
第１図は本発明８★施例の過電圧保護回路の回路図、
くシ
第２図は本発明の他の実施例の過電圧保護回路の回路図
、
第３図は、従来例の過電圧保護回路の回路図である。
図において、
１〜ｎ、１１〜Ｉｎ、２０は半導体アレスタ、Ｆ１〜Ｆ
ｎ、Ｆｉｌ〜Ｆｉｎは警報接点警報表示付きヒユーズ、
ｆ１〜ｆｎ−１は警報接点−−表示（Ｈ区！ｆずＨ〕丑
に−Ｈ橿ｉ透紅
１００は機器、
Ｒは抵抗を示す。
オ→茫旧月一方巳１にトリ阪電しイネ事駈圀吋シの回に
ｉ図第 １ ｆｆｉ
ｇｂ ２ 図Figure 1 is a circuit diagram of an overvoltage protection circuit according to an 8★ embodiment of the present invention, Figure 2 is a circuit diagram of an overvoltage protection circuit according to another embodiment of the invention, and Figure 3 is a conventional overvoltage protection circuit. FIG. In the figure, 1 to n, 11 to In, 20 are semiconductor arresters, F1 to F
n, Fil~Fin are fuses with alarm contact alarm display, f1~fn-1 are alarm contact--display (H ward! O → Tori Handen on the first day of the first month of the month, and the second time of the rice event, Figure i Figure 1 ffi gb 2 Figure
Claims (1)
直列に接続した回路を電源線又は信号線に並列に接続し
、 該第１の警報接点付きヒューズに、第２の半導体アレス
タと第２の警報接点付きヒューズを直列に接続した回路
を並列に接続する如く、 第ｎ−１の警報接点付きヒューズに、第ｎの半導体アレ
スタと第ｎの警報接点付きヒューズを直列に接続した回
路を並列に接続し、 半導体アレスタをｎ段構成としたことを特徴とする過電
圧保護回路。 ２、第１の半導体アレスタと第１の警報接点警報表示付
きヒューズを直列に接続した第１の回路、及び第２の半
導体アレスタと第２の警報接点警報表示付きヒューズと
該第１の警報接点警報表示付きヒューズの警報接点とを
直列に接続した第２の回路、 及び第ｎの半導体アレスタと第ｎの警報接点警報表示付
きヒューズと第ｎ−１の警報接点警報表示付きヒューズ
の警報接点とを直列に接続した第ｎの回路の合計ｎ個の
回路を、 過電圧から保護すべき装置に並列に接続したことを特徴
とする過電圧保護回路。[Claims] 1. In a device to be protected from overvoltage, a circuit in which a first semiconductor arrester and a first fuse with an alarm contact are connected in series is connected in parallel to a power supply line or a signal line, and the first In this way, a circuit in which a second semiconductor arrester and a second fuse with alarm contacts are connected in series is connected in parallel to the fuse with alarm contacts of . An overvoltage protection circuit characterized in that a circuit in which a fuse with an n-th alarm contact is connected in series is connected in parallel to form an n-stage semiconductor arrester. 2. A first circuit in which a first semiconductor arrester, a first alarm contact, a fuse with an alarm display are connected in series, and a second semiconductor arrester, a second alarm contact, a fuse with an alarm display, and the first alarm contact. a second circuit in which an alarm contact of a fuse with an alarm display is connected in series; An overvoltage protection circuit characterized in that a total of n circuits, including an nth circuit connected in series, are connected in parallel to a device to be protected from overvoltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8681385A JPS61247225A (en) | 1985-04-23 | 1985-04-23 | Overvoltage protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8681385A JPS61247225A (en) | 1985-04-23 | 1985-04-23 | Overvoltage protection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61247225A true JPS61247225A (en) | 1986-11-04 |
Family
ID=13897248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8681385A Pending JPS61247225A (en) | 1985-04-23 | 1985-04-23 | Overvoltage protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61247225A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006325288A (en) * | 2005-05-17 | 2006-11-30 | Thor:Kk | Thunder surge protector |
| JP2011205796A (en) * | 2010-03-25 | 2011-10-13 | Nec Infrontia Corp | Failure detection circuit for overvoltage protection elements and subscriber circuit |
-
1985
- 1985-04-23 JP JP8681385A patent/JPS61247225A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006325288A (en) * | 2005-05-17 | 2006-11-30 | Thor:Kk | Thunder surge protector |
| JP2011205796A (en) * | 2010-03-25 | 2011-10-13 | Nec Infrontia Corp | Failure detection circuit for overvoltage protection elements and subscriber circuit |
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