JPS6124665B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timekeeping system using a microprogram as a frequency dividing means for a reference signal.

Conventional electronic clocks use an oscillator with 2 ⁿ for example.
A reference signal of 2 ¹⁵ =32768 (Hz) is generated, this reference signal is divided into a signal with a period of 1 second, and the signals with a period of 1 second are counted to obtain time information. However, if the reference signal is frequency-divided by a frequency divider as in the conventional technique, the frequency divider has a large frequency division ratio, and thus the structure of the frequency divider becomes complicated.

The present invention has been made in view of the above points, and an object of the present invention is to provide a timekeeping system whose configuration can be simplified by frequency-dividing a reference signal using a microprogram.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a key input section, and the key operation output of this key input section 1 is sent to an address section 2, and this address section 2 causes a control section, i.e.
The address of ROM3 is specified. This ROM 3 stores a microprogram for performing a timekeeping operation, and outputs various control signals according to the designated address of the address section 2. The details of this ROM3 will be described later together with the address section 2, but the next address
It outputs NA, key input command K, timing command T, code generation command C, judgment commands J ₁ , J ₂ , calculation command A, gate select signal GS, etc. Then, the next address NA output from the ROM 3 is sent to the address section 2, the key input command K is sent to the key input section 1,
The timing command T is sent to the timing designation circuit 4, the code generation command C is sent to the code generation section 5, and the judgment command is sent to the timing designation circuit 4.
J ₁ and J ₂ are sent to AND circuits 7 and 8 in judgment section 6, calculation command A is sent to AND circuit 9, and gate select signal
GS is sent to the AND circuit 10, respectively. Further, 11 is an oscillator that generates a reference clock of, for example, 32768 Hz, and the output of this oscillator 11 is sent to a timing generation circuit 12. This timing generation circuit 12 generates various timing signals such as digit signals D ₁ , D _{2 .} . . D ₁₂ and bit signals as shown on the left side of FIG. Part 5
sent to. The timing designation circuit 4 has output lines 4a and 4b, and has a ROM shown on the right side of FIG.
According to the timing command T from 3, one or a combination of digit signals from the timing generation circuit 12 (for example, D ₁ to _{D 3} shown in the bottom column of FIG. 2) is output to the output line 4a, and the timing signal is A one-shot signal of one digit is outputted to the output line 4b in synchronization with the leading edge of the signal. In addition, the code generation section 5
When the code generation command C is given from the ROM 3, a predetermined code signal is output in synchronization with the timing signal from the timing generation circuit 12 according to the contents of the command. The code signal output from the code generator 5 is applied to AND circuits 8 and 13. Further, the signal outputted from the timing designation circuit 4 to the output line 4a is connected to the AND circuit 7,
8, 9, 10, and 13 and output to the output line 4b is applied to the AND circuit 13. Therefore, the determination unit 6 determines that the AND circuits 7 and 8
And the outputs of the AND circuits 7 and 8 are the OR circuit 14.
The output of the flip-flop 15 is applied to the judgment section 6.
It is sent to the address section 2 as an output. The flip-flop 15 is reset by a signal from the timing generation circuit 12. Further, the outputs of the AND circuits 9 and 13 are applied to input terminals a and b of a subtracter 16. This subtracter 16 has an input terminal a
The data applied to the input terminal b is subtracted from the data applied to the input terminal b, and the result of the subtraction is applied to the AND circuit 7 and sent to the time register 18 via the gate circuit 17. The details of this time register 18 will be described later, but for example, it has a 12-digit configuration, and its contents are circulated and held through a gate circuit 17.
Its output is applied to AND circuits 8 and 9 and sent to display processing circuitry 19. This display processing circuit 19 performs display processing such as converting serial data sent from the time register 18 into parallel data and adding a delimiter code and the like. The output of this display processing circuit 19 is then sent to the display section 20 and displayed.

FIG. 3 shows the configuration of the time register 18. This time register 18 has, for example, a capacity of 12 digits specified by digit signals _D1 to _D12 , and each digit is composed of 4 bits. and,
The three digits designated by the digit signals _D1 to _D3 constitute reference counters _C0 , _C1 , and _C2 , and the three digits (12 bits) perform a counting operation of "2048".
Furthermore, the digits MI ₀ and MI ₁ specified by the digit signals D ₄ and D ₅ are digits that count minute information.
MI ₀ measures time in minutes, and MI ₁ measures time in 10 minutes. The digits H ₀ and H ₁ specified by the digit signals D ₆ and D ₇ are digits for counting hour information.
H ₀ performs time measurement operation in "hour" units, and H ₁ performs time measurement in "10 o'clock" units. The digits DA ₀ and DA ₁ specified by the digit signals D ₈ and D ₉ are the digits that count day information, with DA ₀ counting in "day" units and DA ₁ counting in "10 days" units. . _{The digits M 0 and M 1 designated by the digit signals D 10 and D 11 are digits for counting monthly information, with M 0 performing a counting operation} in units of "month" and M ₁ performing counting operations in units of "October". And the digit signal
The digit W/AP specified by _D12 is a digit for determining the day of the week and AM/PM.The first bit determines AM and PM, and the second to fourth bits count the day of the week. conduct.

Figure 4 shows the address section 2 and
This shows details of ROM3. Address part 2
, an address register 21 that temporarily stores address data given from the key input section 1, the judgment section 6, or the ROM 3, and a decoder that decodes the code obtained from the address register 21 directly or via an inverter to specify the address of the ROM 3. The first bit of the address register 21 is supplied with the first bit of input address data and the judgment signal from the judgment section 6 via an OR circuit 23. The judgment signal of the judgment unit 6 becomes "0" in the case of YES and "1" in the case of No. Further, the address data input to the address section 2 is given in a code of "2 ⁰ . . . 2 ⁿ " weighted with a 1-2-4-8 code. The address section 2 receives a word pulse φ _w given from the timing generation circuit 12.
Input data is read into the address register 21 in synchronization with , and the address of the ROM 3 is designated according to the read data. In addition, in FIG. 4, address part 2 and corresponding to addresses 0 to 17 are shown.
The configuration of ROM3 is shown. The ROM 3 generates the various signals described above in accordance with the designated address of the address section 2. i.e. the next address
NA is output as a code of " ²⁰ to ²ⁿ " depending on the designated address, and key input command K is output when address No. 3 is designated. The timing command T and code generation command C are output as 4-bit codes according to the specified address. Then, judgment commands J ₁ , J ₂ , calculation command A, gate select signal
Each GS is output as 1 bit and sent to the designated circuit.

FIG. 5 shows an example of an instruction according to the present invention and the output state of the ROM 3 in response to the instruction, that is, a "clear" instruction for the time register 18, and a "D-
code” instruction, the predetermined code is clocked into the register 18
"D code" instruction to write to a predetermined digit of the subtracter 16
``Judgment 1'' instruction to judge the result of subtraction, ``Judgment 2'' instruction to judge whether the contents of the clock register 18 match the predetermined bits output from the code generation section 5, and ``Set key'' to judge the input by the key input section 1. This figure shows the ``determine presence/absence'' command and the output state of the ROM 3 at that time.

Next, the operation of the present invention configured as described above will be explained. The oscillator 11 generates a reference signal of, for example, 32768 Hz, and this reference signal is sent to the timing generation circuit 12. This timing generation circuit 12
In addition to the above-mentioned digital signals D ₁ to D ₁₂ , word pulse φ _w , etc., reference clock pulses φ ₁ and φ
Generates ₂ . These clock pulses φ ₁ , φ ₂
are alternately output once for each cycle of the reference signal. Therefore, the clock pulses φ ₁ , φ ₂
The frequency of is 32768/2Hz. The clock pulses φ ₁ and φ ₂ cause the clock register 18 to shift. That is, data is read by clock pulse _φ1 , and data is read by clock pulse _φ2 .
In this way, the frequency of the reference clock pulses φ ₁ and φ ₂ is 32768/2Hz, and in order to count for one minute using these clock pulses φ ₁ and φ ₂ ,
It is 60 times that amount, or "32768/2 x 60". Further transforming this formula, it becomes 32768/2×60= ²¹⁵ /2×60= ²¹⁴ ×60= ²¹¹ × ²³ ×60= ²¹¹ ×8×6×10= ²¹¹ ×48×10. In the above equation, ²¹¹ is "2048", which can be counted with a 12-bit counter. Therefore, it can be seen that in order to perform counting for one minute, if the number of bits in one word is "48", the counter configuration should be set to 12 bits, and one counting operation should be performed every 10 words. Therefore, in this application, the configuration of the time register 18 is 48 bits ( ₁ word ₎ as shown in detail in FIG. We are making it possible to do this. Referring to the flowchart in Figure 6 below, time register 1
The timing operation of No. 8 will be explained. First, in order to set the time, when the key input unit 1 operates the key operation for the set time and the time setting key, data corresponding to the key operation is output from the ROM 3 (not shown), and the time register 18 is set to a predetermined digit. In this case, the number entry flow for the key input unit 1 is performed by outputting a key input command K from the ROM 3 and by having a set key.
That is, when the key input command K is output from the ROM 3, it is determined whether or not the set key is being operated in the key input unit 1, and if the key is being operated, _F1 in FIG. In other words, the clearing operation of D ₁ to _{D 3} of the number and time register 18, that is, the reference counters C ₀ to _{C 2} is performed. _The reference counters C _{0 to} C ₂ are cleared by the clear command shown in FIG. The reference counter is switched to the subtracter 16 side.
The contents of _C0 to _C2 are cleared. The gate circuit 17 normally circulates the contents of the time register 18 when the output of the AND circuit 10 is "0", and stops the circulation operation when the AND circuit 10 outputs a "1" signal. The subtracter 16 operates to write the output of the subtracter 16 into the time register 18. However, when the above clear command is issued, there is no output from the AND circuits 9 and 13, and the output of the subtracter 16 is "0", and "all 0" is written to the reference counters _C0 to _C2. It can be done. FIG. 7a shows the contents of the register when the time data of "5:30" is entered in the time register 18 in the flow of _F1 described above. After setting the above-mentioned time data, a start key (not shown) in the key input unit 1 is operated when the set time and the current time match, thereby starting the timekeeping operation. That is, when the start key is operated, address 0 of the ROM 3 is first addressed, and the "Judgment ₁ " command causes the contents of _D3 of the time register 18 to become " It is determined whether or not it is "0111" with a weight of "7", that is, 8-4-2-1. This judgment is made by first outputting an instruction, code, timing, etc. at address 0 from the ROM 3, a serial code of numerical value "7" is output from the code generator 5, and a signal is output from the timing specifying circuit 4 at the timing of the digit signal _D3 . is,
In the subtracter 16, "7" is subtracted from the contents of _D3 of the time register 8. Then, the result of this subtraction is sent to the flip-flop 15 via the AND circuit 7 and the OR circuit 14 to make a determination. Since the contents of the reference counters C ₀ to _{C 2} are initially cleared, the subtracter 16 reads “0-
7'' is performed, and the flip-flop 15 is set based on the result of the subtraction. Therefore, the result of the judgment in step _S1 is NO, and the output of the judgment section 6 becomes "1" and is sent to the OR circuit 23 of the address section 2. At this time, the next address based on address 0 of ROM3 is address 2, but the judgment result is NO and the first bit of the address is set to "1" via the OR circuit 23.
is given, the next address will be address 3, and the process will proceed to step _S2 in FIG. Step 2 accompanying address designation of address 3 is a judgment step as to whether or not there is a set key in the key input section 1 described above. At this time, if a set key is present, the address is changed by a signal from the key input section 1 and the address is changed to the above-described flow F. If there is no set key, then address ₁ is designated by the next address and the process advances to step _S3 . The steps from step _S3 to step _S9 are empty steps (adjustment steps) provided for adjusting the number of steps, and do not perform any specific operation, but only the next address NA is specified as shown in Figure 4. Therefore, each of these empty steps _S3 to _S9 requires processing time of one word, just like the other steps. And step
The next address after address 10 is designated by _S0 , and the process advances to step _S10 . In step _S10 , address 10 is specified, so as shown in Figure 4,
The gate select signal GS and calculation command A are outputted from the ROM 3, AND circuits 9 and 10 are opened, and the code generation command C is outputted as "1" and the timing command T is outputted as " _D1 to _D3 ", respectively. , are applied to the code generator 5 and the timing designation circuit 4, and the subtracter 16 performs the operation "D ₁ to D ₃ -1" to subtract "1" from the reference counters C ₀ to _{C 2} . Initially, the contents of the reference counters C ₀ to _{C 2} are all "0", so by the above "-1" operation,
The contents of the reference counters _C0 to _C2 are all "1" as shown in FIG. 7b. And this step
When _S10 is completed, the next address is 0 and the process returns to step _S1 . Thereafter, the operations of steps _S1 to _S10 are repeated, and in step _S10 , the reference counters _C0 to _C2 are decremented by 1 as described above. That is, "-1" is decremented from the reference counters _C0 to _C2 every 10 words. And this "-1" behavior is
When the process is repeated 2048 times, the contents of the reference counters _C0 to _C2 are as shown in FIG _.
The determination of "Is the content of D ₃ 7?" is YES. That is, at the 10×2048th word from the start, the determination result in step _S1 becomes YES, and the process advances to step _S11 . That is, if the judgment result at step _S1 is YES, the flip-flop 15 of the judgment section 6 is not set, and the OR circuit 23 of the address section 2 is set to the address next to step _S1 (address 0).
Address 2 of ROM3 is designated by applying only NA, and the process advances to step _S11 . In this step _S11 , the gate select signal GS, timing signal T specifying "D ₁ to D ₃ ", and
and the next address NA specifying address 11 is output, and the AND circuit 10 outputs the timing “D ₁ ~
By outputting “1” during “D ₃ ”, the time register 18 outputs the subtracter 16 during “D ₁ to D ₃ ”.
The output (“0”) of “ _D1 to _D3 ”, that is, the contents of the reference counters _C0 to _C2, are cleared, and then the process proceeds to step _S12 using the next address NA 11.
At the same time as specifying the address next to address 12, it is determined whether the content of the D ₄ digit of the time register 18 is "9" or not. That is, from the ROM 3 at address 11, the calculation command A and the judgment command J ₁ are output, AND circuits 9 and 7 are opened, and the code generation command "9" and the timing command corresponding to "D ₄ " are output. The code "9" is output from the code generating circuit 5, and the digit signal "D ₄ " is output from the output line 4a of the timing specifying circuit 4, so that the subtracter 16 is outputted via the AND circuits 9 and 13. is given the fourth digit (MI ₀ ) of the clock register 18 and the code "9", and the result is sent to the AND circuit 7 and the OR circuit 14.
The signal is sent to the set terminal S of the flip-flop 15 via the flip-flop 15. In this example, the content of the _4th digit D is "0", so the result of the determination in step _S12 is
Since the answer is NO and flip-flop 15 is set, the address is 13 and the process goes to step _S13.
Proceed to. In this step S ₁₃ , "D ₄ - 15" subtraction,
In other words, subtract "15" from MI ₀ digit in "minutes". That is, the output of the ROM3 at address 13 is the gate select signal GS, the operation command signal A, the code generation command C of "15", the timing command T of "D ₄ ", and the next address of "5", and the subtracter 16 is the “D ₄ ” digit input via the AND circuit 9, that is, MI ₀
The code "15" input via the AND circuit 13 is subtracted from the code "15", and the result is written into the time register 18 via the gate circuit 17 which is switched to the subtracter side by the output of the AND circuit 10. This subtraction operation essentially results in an increase of "+1", and the contents of the time register 18 become as shown in FIG. 7d. When this step _S13 is completed, the process proceeds to an empty step _S5 at address 5, taking into account the processing time of steps _S11 to _S13 , and then returns to step _S1 via steps _S4 to _S10 . Then, step _S10 is executed 2048 times in the same manner as above.
In this way, one minute is counted in steps of "10 x 2048" words, and D ₄ of the clock register,
In other words, "+1" is sequentially added to MI ₀ in the "minute" digit. As a result, the contents of the time register 18 become " _{5:39 "} as shown in FIG _. If the process advances and the judgment of “D ₄ digits is 9” is made in the same way as above,
The judgment result is YES, and the OR circuit 23 is
Only the next address NA from the ROM is applied, and the process proceeds to step _S14 at address 12, where time register 1 is applied.
8 D ₄ digits are cleared. Then step S ₁₅
Then, the next address NA of address 16 is outputted, and it is determined whether the contents of ₅ digits D, that is, the contents of digit MI ₁ in units of "10 minutes" have reached "5". At this point, the content of the _D5 digit is "3", so the judgment result at step _S15 is NO, and the output of the set flip-flop 15 is transferred to the OR circuit 2.
3, the address is changed to address 17 and the process advances to step _S16 . In this step _S16 , the subtraction operation of " _D5 - 15" is performed in the same manner as in the above step _S13 , and as shown in FIG. 7f, "+1" is substantially added to the _D5 digit. After step _S16 is completed, the process returns to step _S7 and a time counting operation for "minutes" is performed.

In addition, the contents of the clock register 18 are
As shown in the figure, if the time changes from "5:59" to "6:00", the judgment result in step _S15 becomes YES, and the process proceeds to step _S17 for the address 10 specified in step _S15 . The contents of D ₅ digits are cleared. Next, the process advances to step _S18 at address 15, where it is determined whether or not the content of the _D7 digit is "1". In this case, judgment is made from the ROM 3 by the judgment instruction J ₂ , the code generation command C of "1", the timing command T of "D ₇ ", and the next address of "18", and the D ₇ digit of the clock register 18, that is, H ₁ . The output “1” of the code generator 5 is output to the AND circuit 8 and the OR circuit 14.
is applied to the flip-flop 15 via the input signal 15, and a match is detected. At this point, the content of D ₇ digits is "0"
Therefore, the determination result in step _S18 is NO, and the process proceeds to step _S19 , where it is determined whether or not the content of the _D6 digit is "9" in the same manner as in step _S12 . The result of this decision is NO and the step
Proceeding to _S20 , the subtraction operation of "D ₆ -15" essentially adds "+1" to the D ₆ digit and the contents of the time register 18 become "6:00", and then the step
Return to _S10 .

The contents of the time register 18 are shown in FIG.
As shown in the figure, when the time changes from "9:59" to "10:00", the content of _{the 6th} digit D is "9", so the judgment result in step _S19 becomes YES and step S Proceed to ₂₁ and D ₆ digits will be cleared. Next, the process proceeds to step _S22 , where a subtraction operation of "D ₁ to _{D 3} -1" is performed. _At this time, since the ₃ digits D ₁ to D have been cleared in step S ₁₁ , the contents of D ₁ to _{D 3} are all "-1" as shown in FIG. 1”. Next, the process proceeds to step _S23 , where the _D7 digit is substantially incremented by ``1'' by the subtraction operation `` _D7-15 '', and then the process returns to step _S2 .

Furthermore, the contents of the time register 18 are shown in FIG.
As shown in l, from "10:59" to "11:00"
In this case, the contents of digit _H1 of the _7- digit "10 o'clock" unit of D is "1", so the judgment result in step _S18 is YES, and the process proceeds to step _S24 , where "D1 _{" is} .about.D ₃ -1" is performed, and the contents of _{the three} digits D ₁ to D, that is, the contents of the reference counters C ₀ to C ₂ become all "1" as shown in FIG. 7I. Next step S ₂₅
Then, it is determined whether the content of the D ₆ digit is "2" or not. In this case, the content of D ₆ digits is “0”
, and the judgment result in step _S25 is NO.
Proceed to S ₂₆ . This step _S26 substantially adds "+1" to the _D6 digit by the subtraction operation " _D6 -15" as shown in FIG.
00 minutes" and then proceed to step _S27 . In this step _S27 , it is again determined whether the content of the _6- digit D is "2" or not, but at this point, the content of _{the 6} -digit D is "1", so the judgment result is NO, and the process returns to step S27. Return to ₂ .

In addition, the contents of the time register 18 are shown in FIG.
As shown in the figure, if the time changes from ``11:59'' to ``12:00'', the change from ``10:59'' to ``11:00''
steps S ₁₈ to S ₂₄ ,
Proceeding to S ₂₅ and S ₂₆ , time measurement processing is performed. This timekeeping process changes the contents of the timekeeping register 18 to “12:00.
minutes", and the content of the ₆ -digit D becomes "2". Therefore, the judgment result in step _S27 becomes YES, and the process proceeds to flow _F2 , where processing for morning, afternoon, day of the week, etc. is performed, and depending on the processing, one of steps _S1 to _S10 is performed, taking into consideration the number of time measurement steps. Return to Also, depending on the processing content of the above flow _F2 , proceed to the processing flow _F3 for the day and month, and proceed to the steps according to the processing content.
Return to any one of S ₁ to S ₁₀ . In addition, the above flow F ₁ ~
Although the details of _F3 are not shown, predetermined processing is performed through the steps shown in the above-mentioned time counting operation.

In addition, the contents of the clock register 18 are
As shown in the figure, when changing from "12:59" to "1:00", the content of ₆ digits D is "2", so
The determination result at step _S25 is ``YES'', and the process advances to step <sub>S28</sub> , where the <sub>D7</sub> digit is cleared as shown in FIG. 7p. Next, the process proceeds to step <sub>S29</sub> , where the content of <sub>the six</sub> digits D is set to ``-1'' from ``2'' to set the content of the time register 18 to ``1:00'', and then the process returns to step _S2 .

In addition, in the flow of FIG. 6, address numbers are assigned to steps _S18 and _S24 , and the ROM is shown in FIG.
I have shown the details of step 3, but the other steps are similar.
It has a ROM configuration, and the output state of the ROM shown in FIG. 5 is appropriately selected based on the processing content of the step.

As described above, in the present invention, no matter which flow is executed, the steps "D ₁ to _{D 3} -1" are executed once for processing 10 words, that is, the steps S ₁₀ , S ₂₂ ,
S ₂₄ and any of the specific steps provided in flows F ₂ and F ₃ , and the reference counter C ₀
~C Perform ₂ count operations. In other words, the reference counters C ₀ to _{C 2} do not directly count the reference clock output from the oscillator 11, but are programmed to count once within the processing time of 10 words. The period becomes very long and the purpose can be achieved with a small capacity. Therefore, the hardware configuration can be significantly simplified.

In the above embodiment, the subtracter 16 is used to perform the timekeeping operation, but an adder may be used instead of the subtractor to perform the timekeeping operation and judgments may also be made by addition. Of course it's a good thing.

Furthermore, although the above-mentioned embodiments have been described with reference to the case where the timekeeping operation is carried out in units of "minutes", it can also be carried out in the same manner as in the above-mentioned embodiments when the timekeeping operation is carried out in units of "seconds".

Furthermore, in the above embodiment, the steps "D ₁ to D ₃ -1" are inserted once within the processing time of 10 words, and the steps "+
1", but for example, if there is no branching due to judgment within the processing time of 20 words or more, "+
2" may be performed in one step, or the above "+1"
may be set to "+n" as appropriate depending on the situation of the processing steps, and the overall number of steps may be omitted.

In short, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the gist of the present invention.

As described above, according to the present invention, the counting operation of the reference counter is performed every predetermined processing time of the microprogram, so that the capacity of the reference counter can be made extremely small, and the circuit configuration can be simplified. It is possible to provide a timekeeping method to obtain.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention;
FIG. 2 is a diagram showing an example of the timing signal output from the timing generation circuit and the output code of the ROM in the same embodiment, FIG. 3 is a diagram showing the configuration of the time register in the same embodiment, and FIG. 4 is a diagram showing the same implementation. FIG. 5 is a diagram showing the details of the ROM (control unit) and address section in the example. FIG. 5 is a diagram showing the contents of instructions used in the example. FIG. 7A to 7P are diagrams showing changes in the contents of the time register according to the time measurement operation in the same embodiment. 1...Key input section, 2...Address section, 3...
ROM, 6... Judgment unit, 11... Oscillator, 12...
...Timing generation circuit, 16...Subtractor, 18...
...Time register.

Claims (1)

[Claims] 1. A control means that executes a timekeeping microprogram having a plurality of processing paths in accordance with a reference signal output from an oscillation means, and a timekeeping operation that performs a timekeeping operation every time the microprogram of this control means is executed a predetermined number of steps. 1. A timekeeping method, characterized in that said microprogram is provided with adjustment steps so that a timekeeping operation is performed every predetermined number of steps no matter which processing path is executed by said microprogram.