JPS61242438A - Transmission system for network control signal - Google Patents

Transmission system for network control signal

Info

Publication number
JPS61242438A
JPS61242438A JP8413785A JP8413785A JPS61242438A JP S61242438 A JPS61242438 A JP S61242438A JP 8413785 A JP8413785 A JP 8413785A JP 8413785 A JP8413785 A JP 8413785A JP S61242438 A JPS61242438 A JP S61242438A
Authority
JP
Japan
Prior art keywords
frame
network control
control signal
bit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8413785A
Other languages
Japanese (ja)
Inventor
Shozo Morihara
森原 昭三
Shigeo Sakai
坂井 茂夫
Takayuki Taniguchi
谷口 孝之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8413785A priority Critical patent/JPS61242438A/en
Publication of JPS61242438A publication Critical patent/JPS61242438A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To eliminate deterioration in multiplex efficiency by stealing state information bits and transmitting a network control signal with them when a frame bit is at a level 1 periodically. CONSTITUTION:The network control signal from a data terminal 4 is inputted to a state signal inserter 6-1. Further, a frame pulse generator 9 generates and sends a pulse to the state signal inserter 6-1 when frame bits of a frame signal from a frame pattern generating circuit 8 which have frame numbers 3, 8, 13, 18... have the level 1. Then, the state signal inserter 6-1 seals a state information bit when the pulse is inputted and superimposes the network control signal, and a frame inserter 7 inserts and transmits a frame signal. When the frame bits having the frame numbers 3, 8, 13, 18... have the level 1, a reception side extracts the state information bit as the network control signal. In this case, the network control signal varies between 0 and 1 alternately, so the state information bit is regarded as discontinuous 1-bit errors, but those discontinuous 1-bit errors do not causes a protecting circuit to malfunction, so that they are received as the network control signal.

Description

【発明の詳細な説明】 〔概要〕 エンベロープ中の1つをフレームビット他ヲ状態情報ビ
ットとするバイト方式のデータ伝送方式において、フレ
ームビットが、周期的な、1レベルの時の状態情報ビッ
トをスチールし、網制御信号を伝送するようにして、網
制御信号専用のチ1ヤンネルを不要にし、多重化効率を
悪くしないようにしたものである。
[Detailed Description of the Invention] [Summary] In a byte-based data transmission system in which one of the envelopes is used as a frame bit and other status information bits, the frame bit periodically transmits the status information bit when it is at level 1. This method eliminates the need for a dedicated channel for network control signals and prevents deterioration of multiplexing efficiency by stealing and transmitting network control signals.

〔産業上の利用分野〕[Industrial application field]

本発明は、エンベロープ中の1つをフレームビット他を
状態情報ビットとするバイト方式のデータ伝送方式の、
回線接続用の網制御信号伝送方式の改良に関する。
The present invention provides a byte-based data transmission system in which one of the envelopes is a frame bit and the other is a status information bit.
This paper relates to improvements in network control signal transmission systems for line connections.

上記の網制御信号を伝送するのには、特に網制御信号用
として専用回線を設けずに伝送出来ることが望ましい。
In order to transmit the above-mentioned network control signals, it is particularly desirable to be able to transmit them without providing a dedicated line for the network control signals.

〔従来の技術・〕[Conventional technology]

第3図は従来例の網制御信号伝送方式のブロック図、第
4図はエンベロープを含むバイト方式のフレーム構成図
である。
FIG. 3 is a block diagram of a conventional network control signal transmission system, and FIG. 4 is a frame configuration diagram of a byte system including an envelope.

第3図中1.2はデータ送信装置、3は多重化装置、4
はデータ端末、5は48にビット・64にビット変喚器
、6は状態信号挿入器、7はフレーム挿入器、8はフレ
ームパターン発生回路を示す。
In Figure 3, 1.2 is a data transmitting device, 3 is a multiplexing device, and 4 is a data transmitting device.
5 is a data terminal, 5 is a bit converter at 48 and 64 is a bit converter, 6 is a status signal inserter, 7 is a frame inserter, and 8 is a frame pattern generation circuit.

第3図は、第4図に示す送信データD1〜D6の6ビツ
トに対し、エンベロープとしてフレームビットF及びデ
ータ端末4が通信中か否かで1又はOとなる状態情報ビ
ットSの2ビツトを持つCCI TT勧告X 50の8
ビツト1フレームの場合の例である。
FIG. 3 shows a frame bit F as an envelope and two status information bits S, which are 1 or O depending on whether or not the data terminal 4 is communicating, for the 6 bits of transmission data D1 to D6 shown in FIG. 4. CCI TT Recommendation
This is an example of a 1-bit frame.

各データ送信装置1. 2のデータ端末4よりの6ビツ
トの48にビット/秒の送信データは、48にビット・
64にビット変換器5にて64にビット/秒のベアラ速
度に変換され、状態信号挿入器6にて状態情報ビットS
の位置に状態信号データが挿入され、又フレーム挿入器
7にて、フレームパターン発生回路8よりのフレームパ
ターンがフレームビットFの位置に挿入され、第4図に
示す構成となり、多重化装置3にて多重化され伝送され
る。
Each data transmitter 1. The 6-bit 48 bits/second transmission data from the data terminal 4 of 2 is 48 bits per second.
64 is converted into a bearer rate of 64 bits/second by the bit converter 5, and the status information bit S is converted by the status signal inserter 6 to 64 bits/second bearer rate.
The status signal data is inserted into the position of frame bit F, and the frame inserter 7 inserts the frame pattern from the frame pattern generation circuit 8 into the position of frame bit F, resulting in the configuration shown in FIG. multiplexed and transmitted.

一方各データ送信装置1.2のデータ端末4よりの回線
接続用の網制御信号は、多重化装置3の別の回線を専用
に使って共通線信号方式で送信している。
On the other hand, the network control signal for line connection from the data terminal 4 of each data transmitter 1.2 is transmitted using a common channel signal method using a separate line of the multiplexer 3 exclusively.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、上記の網制御信号伝送方式では、多重化
装置の1チヤンネルを網制御信号専用に使用するので多
重化効率が悪い問題点がある。
However, the above-mentioned network control signal transmission system has the problem of poor multiplexing efficiency because one channel of the multiplexer is used exclusively for network control signals.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点は、フレームビットが、周期的な、1レベル
の時の、状態情報ビットをスチールし、ここに網制御信
号を乗せ伝送するようにした本発明の網制御信号伝送方
式により解決される。
The above problem is solved by the network control signal transmission method of the present invention, which steals the status information bit when the frame bit is periodic and is at level 1, and transmits the network control signal on top of it. .

〔作用〕[Effect]

本発明は、状態情報ビットの、不連続な、1ビツトの誤
りは、受信側では、保護回路にて誤動作と見做さない点
に着目し、0連続対策を考え、フレームビットが、周期
的な、1レベルの時の、状態情報ビットをスチールし、
ここに、網制御信号を乗せ伝送するようにするので、特
に網制御信号専用の回線を必要としないので多重化効率
を悪くすることはなくなる。
The present invention focuses on the fact that a discontinuous 1-bit error in status information bits is not regarded as a malfunction by the protection circuit on the receiving side, and takes measures against consecutive 0s to prevent frame bits from periodically , steal the state information bits at level 1,
Since network control signals are added and transmitted here, there is no need for a line specifically dedicated to network control signals, so multiplexing efficiency is not degraded.

〔実施例〕〔Example〕

第1図は本発明の実施例のデータ送信装置のブロック図
、第2図は1例の網制御信号挿入位置を示す図である。
FIG. 1 is a block diagram of a data transmitting apparatus according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a network control signal insertion position.

第1図中6−1は状態信号挿入器、9はフレームパルス
発生器を示し、尚企図を通じ同一符号は同一機能のもの
を示す。
In FIG. 1, reference numeral 6-1 indicates a status signal inserter, and reference numeral 9 indicates a frame pulse generator, and the same reference numerals indicate the same functions throughout the plan.

第1図で第3図の場合と異なる点を、O連続とならない
ようにする為、第2図に示す◎の如く、5ビット置きの
フレーム番号が3.8,13,18.3.8・・・のフ
レームビットがlレベルの時、状態情報ビットをスチー
ルする場合を例に取り説明する。
The difference in Fig. 1 from Fig. 3 is that in order to avoid consecutive O's, the frame numbers every 5 bits are 3.8, 13, 18, 3, 8 as shown in Fig. 2. An example will be explained in which the state information bits are stolen when the frame bits of ... are at the l level.

データ端末4よりの網制御信号は状態信号挿入器6−1
に入力せしめておく。
The network control signal from the data terminal 4 is sent to the status signal inserter 6-1.
Please input it to .

又フレームパルス発生器9は、フレームパターン発生回
路゛8よりのフレーム信号の、フレーム番号力3. 8
.、13. 18・・・のフレームビットがlレベルの
時、パルスを発し状態信号挿入器6−1に送り、状態信
号挿入器6−1では、このパルスが入力した時の状態情
報ビットをスチールし、網制御信号を乗せ、フレーム挿
入器7にてフレーム信号を挿入して送信する。
Further, the frame pulse generator 9 receives the frame number 3. of the frame signal from the frame pattern generation circuit ``8''. 8
.. , 13. When the frame bit of 18... is at the L level, a pulse is generated and sent to the status signal inserter 6-1, and the status signal inserter 6-1 steals the status information bit when this pulse is input and inserts it into the network. A control signal is loaded, a frame signal is inserted by a frame inserter 7, and the frame signal is transmitted.

受信側では、フレーム番号が3.8.13.1B、3.
8・・・のフレームビットが1レベルの時の、状態情報
ビットを取り出し網制御信号とする。
On the receiving side, the frame numbers are 3.8.13.1B, 3.
When frame bits 8, . . . are at level 1, the status information bits are taken out and used as network control signals.

この場合、網制御信号はOとなったりlとなったりする
ので、状態情報ビットの、不連続な、1ビットの誤りと
なるが、このような不連続な、1ビツトの誤りは保護回
路では誤動作としないので、網制御信号として受信する
ことが出来る。
In this case, the network control signal becomes O or L, resulting in a discontinuous 1-bit error in the status information bit, but such discontinuous 1-bit error cannot be detected by the protection circuit. Since this is not a malfunction, it can be received as a network control signal.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明せる如く本発明によれば、網制御信号専
用の回線を設けなくとも、網制御信号を送信出来るので
、多重化効率を悪くしない効果がある。
As explained in detail above, according to the present invention, network control signals can be transmitted without providing a dedicated line for network control signals, so there is an effect that multiplexing efficiency is not deteriorated.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例のデータ送信装置のブロック図
、 第2図は1例の網制御信号挿入位置を示す図、第3図は
従来例の網制御信号伝送方式のブロック図、 第4図はエンベロープを含むバイト方式のフレーム構成
図である。 図において、 1.2はデータ送信装置、 3は多重化装置、 4はデータ端末、 5は48にビット・64にビット変換器、6.6−1は
状態信号挿入器、 7はフレーム挿入器、 8はフレームパターン発生回路、 9はフレームパルス発生器を示す。
FIG. 1 is a block diagram of a data transmitting device according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a network control signal insertion position, and FIG. 3 is a block diagram of a conventional network control signal transmission system. FIG. 4 is a frame configuration diagram of the byte method including an envelope. In the figure, 1.2 is a data transmitter, 3 is a multiplexer, 4 is a data terminal, 5 is a bit converter for 48 and 64, 6.6-1 is a status signal inserter, and 7 is a frame inserter. , 8 is a frame pattern generation circuit, and 9 is a frame pulse generator.

Claims (1)

【特許請求の範囲】 エンベロープ中の1つをフレームビット他を状態情報ビ
ットとするバイト方式のデータ伝送方式において、 フレームビットが、周期的な、1レベルの時の、状態情
報ビットをスチールし、 網制御信号を伝送するようにしたことを特徴とする網制
御信号伝送方式。
[Claims] In a byte-based data transmission system in which one frame bit in the envelope and the other status information bits are used, the frame bit periodically steals the status information bit when it is at one level, A network control signal transmission method characterized in that a network control signal is transmitted.
JP8413785A 1985-04-19 1985-04-19 Transmission system for network control signal Pending JPS61242438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8413785A JPS61242438A (en) 1985-04-19 1985-04-19 Transmission system for network control signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8413785A JPS61242438A (en) 1985-04-19 1985-04-19 Transmission system for network control signal

Publications (1)

Publication Number Publication Date
JPS61242438A true JPS61242438A (en) 1986-10-28

Family

ID=13822105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8413785A Pending JPS61242438A (en) 1985-04-19 1985-04-19 Transmission system for network control signal

Country Status (1)

Country Link
JP (1) JPS61242438A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63133737A (en) * 1986-11-26 1988-06-06 Nec Corp Data transmission system
JPH08316991A (en) * 1995-05-17 1996-11-29 Nec Corp Method for transmitting and controlling maintenance information in data communication system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63133737A (en) * 1986-11-26 1988-06-06 Nec Corp Data transmission system
JPH08316991A (en) * 1995-05-17 1996-11-29 Nec Corp Method for transmitting and controlling maintenance information in data communication system

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