JPS61242390A - Word line driving circuit - Google Patents

Abstract

PURPOSE:To set completely a word line at a low level of voltage and to shorten the access time by connecting a MOSFET between the word line and the earth to apply the 1st pulse only when the word line is kept at a high level of voltage and making the MOSFET conductive while the high voltage level of the word line is lowered sufficiently. CONSTITUTION:The 1st pulse produced after the variation of the row address input is detected is applied to the 1st input pulse signal line 16. Thus an N channel transistor TR11 conducts. A P channel TR10 connected in series to the TR11 conducts by an inverter Q2 when a word line 5 is kept at a high level of voltage. Then the current flows through both TR10 and 11 to charge a gate 13 of an N channel TR14 up to the level of a power supply Vcc. When the potential exceeds the threshold level by said charging, the TR14 conducts. Then the reduction of the voltage level of the line 5 is started.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a word line drive circuit for a semiconductor memory configured with multiple complementary insulated gate field effect transistors (hereinafter referred to as CMOSFETs), and particularly relates to a word line drive circuit for a semiconductor memory that is configured with complementary insulated gate field effect transistors (hereinafter referred to as CMOSFETs). After a change in , the time it takes for the previously selected word line to reach the unselected voltage level is shortened, and the influence on the bit line voltage level of the selected memory cell can be quickly eliminated, reducing the access time. This invention relates to a word line drive circuit that can be significantly shortened.

(Prior Art) Generally, in a semiconductor memory circuit, a word line is formed of polysilicon, and one end of the word line is connected to a word line drive circuit controlled by a decode output of a row address decoder.

However, in such a configuration, the word line RC delay time (
(time constant), it takes a considerable amount of time for the new row address signal to affect the bit line voltage level of the memory cell corresponding to it.

Therefore, the time from when the address input changes to when new address data is obtained at the output terminal, that is, the access time, is also quite long.

If we consider the internal operation that determines the access time, first, when the memory address input changes,
The internal address changes accordingly. The change is decoded by a row address decoder and a column address decoder, and one row and one column are selected for one pit of data output. When the access transistor of a memory cell is an n-channel device, typically in a selected row, the word line of that row is driven by a word line drive circuit controlled by the row decoder output, increasing its voltage level. At the same time, due to changes in address input,
In a non-selected row, the word line of that row is driven by a word line drive circuit controlled by the row decoder output, and its voltage level decreases, contrary to the case of the word line of the selected row. .

As a result, after a certain period of time determined mainly by the word line time constant, no matter which column address is compared, the word line voltage level of the row selected due to the row address change is higher than the word line voltage level of the previous row. Yoshi also gets expensive. Only in this state is the data written in the memory of the selected row transferred to the bit line of the column to which the memory cell belongs.
Alternatively, the data is read out to a bit line pair (hereinafter simply referred to as a bit line).

However, at this point, the voltage level of the bit line is still determined by the memory data of the previous memory cell. Therefore, when the data of a memory cell belonging to a newly selected row in a certain column is different from the data of a memory cell belonging to a previously selected row, the bit line of that column changes from the voltage level corresponding to the old data. After passing through an indifferent intermediate voltage level, the voltage level changes to correspond to new data.

Generally, the capacitance of a bit line is large, but the current driving capability of the transistor of the memory cell that drives the large load capacitance is small. Therefore, the bit line changes also. Similar to the process described above for the word line in the selected row to reach a voltage level higher than the word line in the newly unselected row, it takes a considerable amount of time.

In this way, if the voltage level of the bit line changes to the voltage level corresponding to the data in the memory cell corresponding to the newly selected row address, and its magnitude is large enough to be input to the sense circuit, the selected row address is selected. Regarding the bit line of the column, the voltage passes through the data path, is amplified by the sense amplifier, further passes through the output buffer, and is then obtained as output data at the output terminal.

Of the delay time from when the address input changes to when the corresponding output data is obtained as described above, what accounts for a large part is: (a) The delay time from when the row address input changes to when the memory internal In all columns, there is a delay time until the voltage level of the word line of the newly selected row address becomes higher than that of the word line of the unselected row. This delay time is determined by the time required from the change in the row address until the output of the row decoder inside the memory corresponds to the new row address, and the time constant of the word line made of polysilicon.

Second, (b) after the delay time in (a) above, the voltage level of the bit line reaches the voltage level corresponding to the data of the memory cell belonging to the newly selected row, and its magnitude is the input to the sense circuit. This is the delay time required until it becomes sufficient.

As a circuit configuration for shortening the delay time in (b), there has conventionally been a method of detecting a change in the row address input and equalizing or precharging the bit line with a pulse generated thereby. This takes advantage of the delay time until the word line voltage level of the newly selected row exceeds the previous word line voltage level, and detects a change in the row address input during that time and generates a pulse. A change in the bit line forces all bit lines to a level midway between the voltage levels of data "0#" and "1", regardless of whether or not the data in the memory cells read on the bit lines changes. It is something that makes you

By this method, the word line voltage level of the newly selected row, which accounts for a large portion of the delay time in (b) above, exceeds that of the non-selected row, and then the voltage level of the word line that was determined by the data of the corresponding memory cell of the immediately previous selected row is In the process of changing the line voltage level to the voltage level corresponding to the data in the memory cells of the newly selected row, access time is shortened by reducing the time required to reach the intermediate voltage level between the former and latter voltage levels. was.

(Problem to be Solved by the Invention) However, even if the bit line voltage is equalized or precharged as described above, the delay time (,), that is, the time required to decode the row address input and the word line voltage The delay time due to the time constant cannot be shortened. In order to shorten the delay of the word line, a low resistance gate material such as silicide is used for the word line instead of polysilicon, a second aluminum wiring is provided in parallel with the polysilicon, and a second aluminum wiring is installed between them. It has also been proposed to substantially reduce the resistance of the word line by providing contacts at appropriate spacings. However, all of these methods have drawbacks that increase manufacturing difficulty and increase cost.

The delay time described above is determined by (a) the speed at which the word line voltage level rises in the row that was selected intermittently as the row decoder changes due to the input of a new address, and (b) the change from selection to non-selection. Since it is determined by two factors: the speed at which the word line voltage level drops in a row, it is conceivable to use this to shorten the delay time from the circuit design perspective.

In order to raise the word line voltage level of the newly selected row, it is necessary to wait for the output of the row address decoder to change in response to the change in the row address input.

However, lowering the word line voltage level of a newly unselected row can be done without waiting for a change in the row decoder output; for example, as in the case of bit line equalization or precharging, the row address input It is possible to use a pulse generated by detecting a change in . According to K, the word line voltage level can start decreasing in the row that becomes unselected before the row recorder output changes.
The word line voltage level falls faster.

In addition, when providing a circuit that lowers the word line voltage level of non-selected rows regardless of the row recorder output, for example, regardless of the arrangement of the row recorders,
The circuit can be placed in the center of the word line.

By doing so, the word line delay time from the placement position can be significantly shorter than the word line delay time from the row recorder position, so the voltage level of the non-selected word line will fall even faster. .

In this way, J? is generated by detecting a change in the row address input? If a circuit is used that lowers the word line voltage level of non-selected rows by using the delay time, the new Although the speed at which the word line voltage level rises in the selected row does not change, the speed at which the word line voltage level falls in the newly unselected row due to other factors CI:0 can be made considerably faster. Therefore, during the first delay time (a), the voltage level in all columns inside the memory is lower than the new Jl<the word line at the selected row address than the word line at the newly unselected row address. The delay time until the signal becomes high is considerably reduced, and the access time is thereby also reduced. However, the following problems must be overcome in order to put this configuration into practical use.

The simplest circuit for lowering the voltage level of a non-selected word line is to install a transistor with a source-drain path between the word line and the ground line for every word line, and to lower the voltage level of the unselected word line. This is a circuit that commonly detects changes in address input and applies a pulse to generate it.

However, in such a circuit, a reasonably large transistor is required to reduce the word line voltage level quickly enough, and therefore the load capacity of the pulses directly driving that transistor simultaneously becomes enormous. When using a circuit that lowers the voltage level of the word line using a pulse, it is meaningless unless the voltage level is generated earlier than the row recorder output, but if the load capacitance of the pulse becomes large, the row If the time from detecting a change in address to generating a pulse is long, it becomes difficult to generate a pulse quickly when changing a row decoder output.

Furthermore, when driving a large capacity, a large amount of current flows, causing instantaneous fluctuations in the power supply voltage and causing malfunctions.

Instead of directly pulse-driving all such transistors e-), for example, a 0 MOSFET in-group
If you set up and drive a park made up of evenings, will it work? Although the load capacitance of the word lines is reduced, for all word lines,
As long as the gates of transistors whose voltage level is set to ground potential are simultaneously driven, when those transistors conduct, a large current that drives a large date capacitance flows, causing instantaneous fluctuations in the power supply voltage. It cannot be denied that this has an undesirable effect on memory operation.

In order to avoid this, it is necessary to configure a circuit in which the transistors are made conductive only for the word line selected in the previous cycle and at a high voltage, and the others remain non-conductive. An example of such a circuit is a circuit that performs an AND operation between the word line voltage level and the pulse generated by detecting the row address input, and then lowers the voltage level of only the word line at a high voltage level by applying a pulse. do it. However, in such a simple circuit, when the transistor becomes conductive and the word line voltage level drops to a certain extent, it is fed back to the AND circuit, the output of the AND circuit changes, and the transistor is canted off. Thereafter, no matter how many pulses are applied, the word line voltage level cannot be lowered.

Note that this problem occurs when the word line voltage level of the AND input is
If the voltage that changes the logic value is set low enough,
It can perform that function, but in that case, even a very small increase in the word line voltage level will cause a row address change to be detected and generated! As long as the pulse continues to be applied, the output of the AND circuit in that row changes, causing the transistor to conduct and causing the rising word line voltage level to drop again. This problem can be solved by stopping the application of pulses as soon as the word line voltage level of the selected row starts to rise, but in general, in large-capacity memories, the time from the row address change to the row decoder output change is This is because it is shorter than the word line time constant.

The pulse application time becomes insufficient with respect to the time required to sufficiently lower the word line voltage level, and the word line voltage level lowering circuit based on the cycle does not function adequately.

(Means for Solving the Problem) In order to solve the problem of shortening access time in the conventional memory circuit, the present invention utilizes the property that the gate capacitance of a MOSFET temporarily stores the input voltage level. A MOSFET is connected between the word line and ground, and the first pulse of the pulse generated by detecting a change in the row address input is applied to the gate of the MOSFET only when the word line is at a high voltage. By making the MOSFET conductive while the high voltage level sufficiently drops, the high voltage level of the word line is brought to a low voltage level, and a second pulse generated after a certain period of time after the generation of the first pulse is suppressed.
This problem is solved by providing a circuit that applies the voltage to the gate of the MOSFET and makes it non-conductive.

(Function) The present invention has the above-described structure, and the transistor that lowers the word line voltage level changes from non-conductive to conductive when the voltage level of the word line to which the transistor belongs reaches a certain level. exceeds the first voltage level, and only when the row address is applied, and the transistor returns to non-conduction regardless of the word line voltage level.
This is the point in time at which the application of the second pulse, which occurs a certain time after the arm pulse, begins.

Therefore, since the transistor is conductive only in the row where the word line is at a high voltage level, a large instantaneous current as described above does not flow. In addition, even though the level of the word line voltage level controls whether or not to conduct the transistors provided in that row, even if the transistors become conductive and the word line voltage level decreases,
Once it becomes conductive, it will not become non-conductive again until the voltage is cut off. Furthermore, conduction of the transistor,
Because the value of the word line voltage level that controls non-conduction can be set high, for a certain period of time after the newly selective word line voltage level rises, even if the first bus pulse continues to be applied, the newly rising word line voltage level will not increase. Movement of voltage levels is not hindered.

A second node P that turns the above transistor from conductive to non-conductive.
The pulse application timing may be any timing necessary to make the once conductive transistor completely non-conductive again in preparation for the next cycle after the first i4 pulse is applied, so that the transistor is conductive. There's plenty of time,
Therefore, the word line voltage level can be set to a sufficiently low level at high speed, and therefore, a memory with high-speed access time without instantaneous power supply fluctuations can be constructed.

(Example) Hereinafter, the present invention will be explained by examples.

The figure is a main circuit diagram showing an embodiment of the present invention, in which Ql to Q4 are inverters using CMOSFETs.

Output 2 of row recorder 1 is input to inverter Q1 constituted by p and n channel transistors 3 and 4, and word line 5 is driven by its output. Its word line central part 6 is connected to an inverter Q2 consisting of a p- and n-channel transistor 7.8, whose output 9 is input to the gate of a p-channel transistor 10, whose source is connected to a first power supply terminal, i.e. the power supply VCC. , and its drain is connected to the drain of n-channel transistor 11. Further, the source of the n-channel transistor 11 is n
It is connected to the drain of the channel transistor 12, and its source is connected to a second power supply terminal and a ground terminal. The gate of the n-channel transistor 11 is connected to a first input pulse signal line 16, and the gate of the n-channel transistor 12 is connected to a second input pulse signal line 17.

A connection point between the source of n-channel transistor 11 and the drain of n-channel transistor 12 is commonly connected to the gate of n-channel transistor 14. The drain of n-channel transistor 14 is connected to word line central portion 6, and its source is grounded.

In this circuit, if output 2 of row recorder 1 is selected in the cycle immediately before the row address input changes and is at a low voltage level, then inverter Q! Yoshiword lines 5, 6
．． 15 is at a high voltage, the input of the inverter Q2 is a high voltage, and the output 9 is a low voltage. The p-channel transistor 10 receiving this is conductive.

In this state, a first pulse generated by detecting a change in the row address input is applied to the first input/bus pulse signal line 16. Note that this first pulse is normally at the ground voltage level, and after the row address input changes, it remains at V for a certain period of time.
It is like a cc level. When the first pulse is applied, the n-channel transistor 11 becomes conductive. When word line 5 is at a high voltage level, transistor 1
Since the p-channel transistor 10 connected in series with 10 and 10 is rendered conductive by the inverter Q2, a current flows through these transistors 10 and 11 to charge the gate 13 of the transistor 14 to the level of the power supply VCC, and as a result of this charging, the potential increases. , when the threshold value is exceeded, the n-channel transistor 14 becomes conductive, so that the voltage level of the word line 5 begins to fall. Word line center part 6
The voltage level of is determined by the characteristics of inverter Q2,
When the voltage level drops to a certain level, the inverter Q! The output 9 of is inverted and the p-channel transistor IO changes from conducting to non-conducting. Thereby f of transistor 14
The charging current of f-t 13 stops flowing. However, since the transistor 12 that discharges the charge of the gate 13 is non-conductive as long as the second input signal line 17 maintains the ground potential, the gate 13 is in a floating state where it is neither charged nor discharged. There is almost no change in the voltage level of the transistor 14, and the transistor 14 continues to be conductive.

Thereafter, the application of the pulse to the first input pulse signal line 16 ends, and the n-channel transistor 11 changes from a conductive state to a non-conductive state. However, even in this case, gate 13
The voltage level of n-channel transistor 1 hardly changes.
4 remains conductive.

In this way, after the voltage level of the word line 5 (6, 15) has fallen sufficiently, a second pulse signal similar to the first pulse signal line 17 is applied to the second input pulse signal line 17. , n-channel transistor 12 changes from non-conductive to conductive, thereby discharging the charge on f-1-13 and returning n-channel transistor 14 to the non-conductive state. Note that in this case, transistors 10 and 11 in the figure are connected to the power supply VC.
It may be replaced with C.

Next, the case where there is only one output state of the row decoder 1 is as follows.

That is, if the row recorder output 18 of another row is in the unselected state immediately before the row address input changes, and as a result of the row address change, it is newly selected and becomes a low voltage level.
Immediately after the row address input changes, the voltage level of the word line center portion 22 is still at the ground level, so the output 25 of the inverter Q4 is at a high voltage level, so that the p-channel transistor 26 is in a non-conducting state. ing. Therefore, if a pulse is applied to the input signal line 16 at this point, the n-channel transistor 27 becomes conductive, but the p-channel transistor 26 connected in series with it is non-conductive. Power supply V. No charging current flows from C to gate 28 of transistor 30, so transistor 30 remains non-conducting. In this way, in a row where the word line 22 is at a low voltage level, even if a pulse is applied, the transistors 23 and 24
, 26.

No current flows through any of the transistors 27, 29, and 30, so there is little variation in the instantaneous power supply voltage, and the memory operation is stable.

When the output 18 of row decoder 1 goes to a low voltage level, the output of inverter Q3 inverts and connects word line 21.22.3.
1 voltage level begins to rise.

However, even in that case, the transistor 26 does not become conductive immediately. Only when, after a certain period of time determined by the time constant of the polysilicon word line 21, the voltage level at the central portion 22 of the word line exceeds a certain value determined by the characteristics of the inverter Q4, the output 25 of the inverter Q4 is inverted and the transistor 26 changes from non-conducting to conducting. If the application of the first pulse to the first input pulse signal line 16 has been completed by this point, even if the transistor 26 becomes conductive, the transistor 3
0 becomes conductive and the voltage level of word line 21.22.31 does not begin to rise. Even after that, the second
The transistor 14 that lowers the word line voltage level in the row that has changed from selected to unselected does not change from a conductive state to a non-conductive state until the second pulse begins to be applied to the input canoculus signal line 17. Therefore, the conduction period is sufficiently ensured, and the word line voltage level can be lowered to a sufficiently low level at all positions on the word line 5.6.15.

(Effects of the Invention) As is clear from the above detailed description, the present invention utilizes a pulse generated by detecting a change in a row address to select a row address before the row address changes. The high voltage level of a word line that has become unselected due to a change in input is reduced to a low voltage level that does not adversely affect the bit line voltage level of the memory cells connected to that word line.
The newly selective word line voltage level can be lowered before it begins to rise after the row decode output for that row has changed, and the pulses described above can cause the word line voltage level to increase at the selected row. Since sufficient conduction time can be secured for the transistor that lowers the voltage without any interference, the voltage of the word line can be completely reduced to a low voltage. Therefore, since a memory circuit having such a word line driving circuit can shorten the access time, it becomes possible to significantly shorten the processing time of a computer or the like configured with such a memory circuit.

[Brief explanation of the drawing]

The figure is a circuit diagram showing one embodiment of the present invention. 1... line recorder/, 2.18... (line recorder)
Output, 5, 21... word line, 6, 22... word line center, 16.17... input pulse signal line, Ql to Q4... inverter.

Claims (2)

[Claims] (1) In a memory circuit, there is a MOS between the word line and ground.
A FET is connected to the gate, and a pulse generated by detecting a change in the row address input is applied to the gate only when the word line is at a high voltage. By making the MOSFET conductive, the high voltage level of the word line is brought to a low voltage level,
A word line drive circuit comprising a circuit that applies a next pulse generated a certain time after the generation of the pulse to the gate of the MOSFET to make it non-conductive. (2) In a memory circuit having a plurality of word lines, the source electrode of the first MOSFET having the first channel conductivity type is connected to the first power supply terminal, and the source electrode of the second MOSFET having the second channel conductivity type is connected to the first power supply terminal. A source electrode is connected to a second power terminal, respectively, and the first and second MOSFETs are connected to each other.
The gate electrodes of the third MOSFET are both connected to the word line, and the drain electrodes are both connected to the gate electrode of a third MOSFET having the first channel conductivity type.
The source electrode of the FET is connected to the first power supply terminal directly or through a fourth MOSFET having a second conductivity type, and the drain electrode of the third MOSFET is connected to the first power supply terminal, and the drain electrode of the third MOSFET is connected to the first power supply terminal. through or directly a drain electrode of a fifth MOSFET having a second channel conductivity type, and connecting a source electrode of the fifth MOSFET to the second power supply terminal; The gate electrode of the fourth MOSFET is connected to a first input pulse signal line that supplies a first pulse generated by detecting a change in the row address input;
The gate electrode of the OSFET is connected to a second input pulse signal line that supplies a second pulse generated after a certain period of time after the generation of the first pulse, and the source electrode of the fourth MOSFET and the fifth MOSFET are connected to each other. The drain electrode of the MOSFET is connected to a sixth MOSFET having the second channel conductivity type.
2. The word line drive circuit according to claim 1, wherein the word line drive circuit is connected to the gate electrode of the word line, and its source electrode and drain electrode are connected to the second power supply terminal and the word line, respectively.