JPS61242056A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS61242056A JPS61242056A JP8391085A JP8391085A JPS61242056A JP S61242056 A JPS61242056 A JP S61242056A JP 8391085 A JP8391085 A JP 8391085A JP 8391085 A JP8391085 A JP 8391085A JP S61242056 A JPS61242056 A JP S61242056A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- integrated circuit
- element fixing
- semiconductor integrated
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 239000003990 capacitor Substances 0.000 abstract description 5
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 abstract description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体集積回路装置に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor integrated circuit device.
（従来の技術）
従来、ダイナミックＲＡＭの様なＭＯ８型集積回路装置
においては半導体基板にバイアス電圧を印加する必要が
あろうこれまでこのような半導体集積回路装置では、基
板バイアス電圧全半導体チップ内部で自動発生したもの
が実用化されている。(Prior Art) Conventionally, in MO8 type integrated circuit devices such as dynamic RAM, it has been necessary to apply a bias voltage to the semiconductor substrate. What was automatically generated has been put into practical use.
しかし、この場合１．半導体チップを固着する金属化領
域は、浮遊状態となっている。このように半導体基板が
浮遊状態にある素子固着領域と接続しておると半導体チ
ップ内部の傷号ラインが高レベルから低レベルに、ある
いは低レベルから高レベルに変化すると、上記信号ライ
ンと半導体基板との間の容を結合により半導体基板の電
位が変動してしまい、半導体素子の動作に悪影響を及ぼ
してしまう、これをダイナミックＲＡＭ’ｉ例にして説
明する。However, in this case 1. The metallized area to which the semiconductor chip is attached is in a floating state. If the semiconductor substrate is connected to the floating element fixing area in this way, if the signal line inside the semiconductor chip changes from a high level to a low level or from a low level to a high level, the signal line and the semiconductor substrate The potential of the semiconductor substrate fluctuates due to the coupling between the capacitance and the capacitor, which adversely affects the operation of the semiconductor element. This will be explained using an example of a dynamic RAM'i.
第２因に従来のダイナミックＲＡＭの一例の部分断面図
である。The second factor is a partial sectional view of an example of a conventional dynamic RAM.
第２図において、１は半導体基板、２は半導体素子固着
領域、３は電源電位ま几は接地電位の拡散層、４は内Ｓ
信号ラインの拡散層、５に内部信号ラインである。半導
体基板１と半導体素子固着領域２とは、例えば金−シリ
コンなどの導電性材料を用いて接続しである。In Figure 2, 1 is a semiconductor substrate, 2 is a semiconductor element fixing region, 3 is a power supply potential or ground potential diffusion layer, and 4 is an inner S
The signal line diffusion layer 5 is an internal signal line. The semiconductor substrate 1 and the semiconductor element fixing region 2 are connected using a conductive material such as gold-silicon.
（発明が解決しようとする問題点）
基板電位自動発生回路を有するダイナミックＲＡＭでは
外部人力クロックに同期して内部回路が動作する。この
とき、内部信号ライン５の電位が高レベルから低レベル
へ、または低レベルから高レベルへと変化するときに内
部信号ライン５と同電位である拡散層４と半導体基板１
との間の容量Ｃ２による容量結合により半導体基板自身
の電位の電位の変動を生じてしまう、さらに、半導体基
板と内部回路の電源ｉ几に接地電位にある拡散層３との
間の容量Ｃ１による容量結合により電源電位またに接地
７位も変動を起してしまい、半導体集積回路自身の動作
上問題となってしまう。(Problems to be Solved by the Invention) In a dynamic RAM having an automatic substrate potential generation circuit, an internal circuit operates in synchronization with an external manual clock. At this time, when the potential of the internal signal line 5 changes from a high level to a low level or from a low level to a high level, the diffusion layer 4 and the semiconductor substrate 1 which are at the same potential as the internal signal line 5
The potential of the semiconductor substrate itself changes due to the capacitive coupling due to the capacitance C2 between the semiconductor substrate and the diffusion layer 3, which is at the ground potential of the internal circuit power source i. The capacitive coupling causes fluctuations in the power supply potential and the ground potential, causing problems in the operation of the semiconductor integrated circuit itself.
本発明の目的は、基板電位自動発生回路を有する半導体
集積回路の基板電位の変動を抑制する半導体集積回路装
置ｔを提供することにある。An object of the present invention is to provide a semiconductor integrated circuit device t that suppresses fluctuations in the substrate potential of a semiconductor integrated circuit having an automatic substrate potential generation circuit.
（問題点を解決するための手段）
本発明の半導体集積回路装置は、半導体集積回路素子と
基板バイアス自動発生回路ｔ−有する半導体チップを収
納容器内の金属化１から収る素子固着領域上に実装して
なる半導体集積回路装置ｔにおいて、前記半導体チップ
と前記収納容器との間に容量素子が設けられ、前記半導
体チップの固着面が前記容量素子の−１の電極に接続さ
れ、前記容量素子の他方の電極が基単電位源に接続され
ることにより構成される。(Means for Solving the Problems) The semiconductor integrated circuit device of the present invention has a semiconductor chip having a semiconductor integrated circuit element and an automatic substrate bias generation circuit t- on an element fixing area that is accommodated from metallization 1 in a storage container. In the mounted semiconductor integrated circuit device t, a capacitive element is provided between the semiconductor chip and the storage container, the fixed surface of the semiconductor chip is connected to the -1 electrode of the capacitive element, and the capacitive element The other electrode is connected to a base single potential source.
前記容量素子に、収納容器の素子固着領域の金属化層の
上に誘電体層を重ね、該誘電体層の上に導電体の上側素
子固着領域を設けて該上側素子固着領域全−万の電極、
前記金属化層を他方の電極として構成するのが好ましく
、前記上側素子固着領域に半導体チップを固着し、前記
半導体チップの外部電源端子もしくは接地電位端子と前
記他方の電極となる前記金属化層と金半導線で接続する
のが好ましい。A dielectric layer is overlaid on the capacitive element on the metallized layer in the element fixing area of the storage container, and an upper element fixing area of a conductor is provided on the dielectric layer to cover the entire upper element fixing area. electrode,
Preferably, the metallized layer is configured as the other electrode, and a semiconductor chip is fixed to the upper element fixing region, and an external power supply terminal or a ground potential terminal of the semiconductor chip and the metallized layer serving as the other electrode are connected. It is preferable to connect with gold semiconductor wire.
（実施料）
次に、本発明の実施例について説明する、第１図（ａＬ
（ｂ）は本発明の一実施例の平面図及び断面図でちる
。(Practice Fee) Next, FIG. 1 (aL
(b) is a plan view and a sectional view of one embodiment of the present invention.
第１図（ａ）、 （ｂ）ｉＣおいて、半導体基板１．拡
散１３．４．内部信号ライン５は第２図に示しｔものと
同じである。この実施例においては、半導体を収納する
容器の金属化層から収る素子固着領域を上側素子固着領
域と下側素子固着領域７とに分割し、上側領域６と下側
領域７との間に誘電体Ｓｔ−挾んでコンデンサを形成す
る。コンデンサの容量を０３ とする。誘電体８は、
例えば窒化シリコン膜のような材料である。上側領域６
と半導体基板１とは金−シリコンなどの導電性材料を用
いて接続する。次に、電源ま友は接地電位の拡散層３と
下側素子固着領域７とｔ金属線９で接続する。In FIGS. 1(a) and 1(b) iC, semiconductor substrate 1. Diffusion 13.4. The internal signal line 5 is the same as that shown in FIG. In this embodiment, the device fixing region that fits from the metallized layer of the container containing the semiconductor is divided into an upper device fixing region and a lower device fixing region 7, and between the upper region 6 and the lower region 7, A capacitor is formed by sandwiching the dielectric St-. Let the capacitance of the capacitor be 03. The dielectric 8 is
For example, it is a material such as a silicon nitride film. Upper area 6
and semiconductor substrate 1 are connected using a conductive material such as gold-silicon. Next, the power source is connected to the diffusion layer 3 at ground potential and the lower element fixing region 7 through the t metal wire 9.
このようにコンデンサの下部電極である下側素子固着領
域７ｔ−電源まｔに接地電位に固定すると、内部信号ラ
イン５が高レベルから低レベルへ、ま友は低レベルから
高レベルへ電位が変化しても、半導体基板１の１位に最
小限に抑制することができる。さらに、半導体基板の電
位変動が拡散層３と半導体基板１との間の容量Ｃ１ｔ−
通して電源または接地電位全変動させることも抑制でき
る。In this way, when the lower element fixing region 7t, which is the lower electrode of the capacitor, is fixed to the ground potential, the potential of the internal signal line 5 changes from a high level to a low level, and the potential of the internal signal line 5 changes from a low level to a high level. Even if it is, it can be minimized to the first place on the semiconductor substrate 1. Furthermore, the potential fluctuation of the semiconductor substrate causes the capacitance C1t- between the diffusion layer 3 and the semiconductor substrate 1 to
It is also possible to suppress total fluctuations in the power supply or ground potential.
（発明の効果）
以上説明したように、本発明によれば、半導体基板の電
位変動を抑制し、半導体集積回路の動作に悪影響を与え
ることを防止することができる半導体集積回路装置が得
られる。(Effects of the Invention) As described above, according to the present invention, a semiconductor integrated circuit device can be obtained that can suppress potential fluctuations of a semiconductor substrate and prevent adverse effects on the operation of a semiconductor integrated circuit.
第１図（ａｌ、 （ｂ）に本発明の一実施例の平面囚及
び断面図、第２図に従来のダイナミック几ＡＭの−例の
部分断面図である。
１・・・・・・半導体基板、２・・・・・・半導体素子
固着領域、３．４・・・・・・拡散層、５・・・・・・
内部信号ライン％６・・・・・・上側素子固着領斌、７
・・・・・・下側素子固着領域、８・・・・・・誘電体
、９・・・・・・金属線％ ｃｌ、 ｃ、、 ｃ、 ・
旧・・容量。
′￥＝１ ＠FIGS. 1A and 1B are a plan view and a sectional view of an embodiment of the present invention, and FIG. 2 is a partial sectional view of an example of a conventional dynamic AM. 1...Semiconductor Substrate, 2... Semiconductor element fixing region, 3.4... Diffusion layer, 5...
Internal signal line %6... Upper element fixation area, 7
...Lower element fixing region, 8...Dielectric material, 9...Metal wire% cl, c,, c, ・
Old capacity. '￥=1 @
Claims (2)
を有する半導体チップを収納容器内の金属化層から成る
素子固着領域上に実装してなる半導体集積回路装置にお
いて、前記半導体チップと前記収納容器との間に容量素
子が設けられ、前記半導体チップの固着面が前記容量素
子の一方の電極に接続され、前記容量素子の他方の電極
が基準電位源に接続されたことを特徴とする半導体集積
回路装置。(1) In a semiconductor integrated circuit device in which a semiconductor chip having a semiconductor integrated circuit element and a substrate bias automatic generation circuit is mounted on an element fixing region made of a metalized layer in a storage container, the semiconductor chip and the storage container are A semiconductor integrated circuit characterized in that a capacitive element is provided between them, a fixed surface of the semiconductor chip is connected to one electrode of the capacitive element, and the other electrode of the capacitive element is connected to a reference potential source. Device.
層を重ね、該誘電体層の上に導電体の上側素子固着領域
を設けて該上側素子固着領域を一方の電極、前記金属化
層を他方の電極とする容量素子を形成し、前記上側素子
固着領域に半導体チップを固着し、前記半導体チップの
外部電源端子もしくは接地電位端子と前記他方の電極と
なる前記金属化層とを半導線で接続した特許請求の範囲
第（１）項記載の半導体集積回路装置。(2) A dielectric layer is stacked on the metallized layer in the element fixing area of the storage container, and an upper element fixing area of a conductor is provided on the dielectric layer, and the upper element fixing area is connected to one electrode, the A capacitive element having a metallized layer as the other electrode is formed, a semiconductor chip is fixed to the upper element fixing region, and an external power supply terminal or a ground potential terminal of the semiconductor chip and the metallized layer serving as the other electrode. A semiconductor integrated circuit device according to claim (1), wherein the semiconductor integrated circuit devices are connected by a semiconductor wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8391085A JPS61242056A (en) | 1985-04-19 | 1985-04-19 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8391085A JPS61242056A (en) | 1985-04-19 | 1985-04-19 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61242056A true JPS61242056A (en) | 1986-10-28 |
Family
ID=13815762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8391085A Pending JPS61242056A (en) | 1985-04-19 | 1985-04-19 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61242056A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01198062A (en) * | 1988-02-03 | 1989-08-09 | Nec Corp | Integrated circuit |
-
1985
- 1985-04-19 JP JP8391085A patent/JPS61242056A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01198062A (en) * | 1988-02-03 | 1989-08-09 | Nec Corp | Integrated circuit |
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