JPS61240500A - Semiconductor memory circuit device - Google Patents

Abstract

PURPOSE:To enable to carry out simultaneous designing of 1-bit system and multi-bit system by installing a switch and after passing inspection of a multi-bit system in input condition, to convert to input condition of a 1-bit system. CONSTITUTION:In carrying out inspection of acceptable products, two lines out of the 6 signal lines respectively inputted to Y decoder 3a-3d, are grounded by switch 1, then by grounding the sense amplifier data input circuits 5b-5d to the redundant data I/O terminal 6, the 4 bit data of the address designated by the signal from the address input terminal 14, shall be inputted and outputted via the data I/O terminal 12 and the redundant data I/O terminal 6, to enable inspection of the multi-bit system I/O functions. Then by switching over switches 1, 15 and connecting the redundant address input terminal 7 to the Y decoder 3a-3d and the circuit 5b-5d to the data I/O terminal 12, the 1-bit data of the address designated by the signal from the terminal 14 and terminal 7 shall be outputted from the terminal 12 and inputted from the data input terminal 13.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor memory device.

[Conventional technology]

In a conventional semiconductor memory device, the number of bits of input/output data is fixed, and the number of bits for input/output data cannot be stored, for example, at 4 bits.

[Problem that the invention seeks to solve]

Since the diameter has become larger than 6 inches, the inspection time for non-defective products has become a major factor limiting productivity.

At the same time, there was a need to shorten the design and development period in response to the diversification of developed products.

The conventional method of designing semiconductor memory circuits separately for multi-bit and 1-bit circuits has had the disadvantage of not being able to quickly respond to market demands.

SUMMARY OF THE INVENTION In order to eliminate such drawbacks, it is an object of the present invention to provide a semiconductor memory circuit which can shorten the inspection time for non-defective products and can simultaneously design a 1-bit system and a multi-bit system.

an address decoder that enables access to specified memory cells of the plurality of memory cell sections specified by the plurality of memory cell sections; and a plurality of sense amplifiers that are provided corresponding to the plurality of memory cell sections and input and output signals to and from the specified memory cells. - In a semiconductor memory circuit device having an input circuit, an address input terminal connected to the address decoder, a redundant address input terminal, a data input/output terminal connected to either of the sense amplifier/input circuit, and a redundant address input terminal, a data input/output terminal, a first switch capable of switching from a disconnected state to a connected state between the redundant address input terminal and the address decoder, and the sense amplifier/input circuit that is not connected to the data input/output terminal. and a second switch that can switch from a state in which each of the redundant data input/output terminals is connected to a state in which each of the redundant data input/output terminals is connected to the data input/output terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. wX1 is a schematic plan view of an embodiment of the present invention.

The embodiment shown in FIG.
d, X decoder 4. Sense anzu data input circuit 58~
5di, the address input terminal 14 and the redundant address input terminal 7 are connected to the Y decoders 3a to 3d or the X decoder 4, and the redundant address input terminal 7 and the Y decoders 3a to 3
A VcH switch l is provided during the period d. The data input/output terminal 12 is connected to the sense amplifier/data input circuit 5aK, and each of the sense amplifier/data input circuits 5b to 5d is connected to the redundant data input/output terminal 6 via the switch 15, or the data input/output terminal 12.

When inspecting the embodiment shown in FIG. 1, two of the six signal lines input to each of the Y decoders 3a to 3d are
By grounding the switch IC and connecting each of the sense amplifier data input circuits 5b to 5d to the redundant data input/output terminal 6, the 4 bits of the address specified by the signal from the address input terminal 14 can be Data is input/output via the data input/output terminal 12 and the redundant data input/output terminal 6, and the input/output function can be tested in a multi-bit system.

After the quality inspection is completed, switch 1 or 1 according to the required VC.
5', connect redundant address input terminal 7 to Y decoder 33 to 3dK, and connect sense amplifier data input circuit 5.
The data of the connection bits b to 5d of the data input/output terminal 121C is outputted from the data input/output terminal 12 and inputted from the data input terminal 13 (in FIG.
(The signal paths from the to the sense amplifier data input circuits 5a to 5d are omitted).

As shown in FIG. 2, the switch 1 has inverters 21 to 23 connected in series, which are composed of MOS transistors (those circled in the figure indicate P-channel MOS transistors, and the others indicate iN-channel MO8 transistors). The terminal 8 is connected to the input of the inverter 21, connected to the power supply VC via the fuse 9, and grounded via the MOS transistor 20, and the output of the inverter 21 is connected to the gate of the MOS transistor 20. Y decoder 33
Any one of the koto address signal lines input to 3d is connected to the redundant address input terminal 7 via a gate circuit 24 or 25 composed of a MOS transistor, and is also grounded. Point b on the output side of the inverter 22 is the gate circuit 24
A point a, which is the output side of the inverter 23, is connected to the N-channel side of the gate circuit 24 and the P-channel side gate of the gate circuit 25.

Therefore, when the input of the inverter 21 is connected to the power supply from the phase 9 IC, point a becomes the power supply voltage level, point b becomes the earth level, and any of the signal lines connected to the sY decoders 38 to 3d is grounded. The above-mentioned 4-bit data input/output state is reached.

Pad 8# When current is applied from an IC tester etc. to disconnect phase 9, point a becomes ground level and point b becomes power supply voltage level, so that the signal from address input terminal 7 is transmitted to Y decoders 3a to 3d. This results in the above-mentioned 1-bit data input/output state.

The switch 15 connects the inverter 31 as shown in the wx3 diagram.
~33. Terminal 10. The fuse 11 and the MOS transistor 30 are the same as those shown in FIG. 12 is connected to the sense amplifier data input circuit 5 via the sense amplifier data input circuit 5a and the gate circuit 34.
b to 5d, and the data input terminal 13 is connected to the data input circuit via the gate circuit 36. The 0 point on the output side of the inverter 32 is the gate circuit 3
4.36 P channel side gate and gate circuit 3
connected to the N-channel side gate of inverter 3.
Point d, which is the output side of No. 3, is connected to the N-channel side gates of gate circuits 34 and 36 and the P-channel side gate of gate circuit 35.

When the input of the inverter 31 is connected to the power supply by the fuse 11, the 0 point is the power supply voltage level, the d point is the earth level, and the path shown in FIG. 3 is connected, and the path B
is blocked. Therefore, sense amplifier data input circuit 5b
5d are connected to the redundant data input/output terminal 6.

Mayu, at time t when phase 11 is disconnected, point 0 is the earth level - point d is the power supply voltage level, and the route is cut off.
Route B is opened. This connects the redundant data input/output terminal 6 to the friend sense amplifier/data input circuit 5b.
A signal line from ~5d is bonded during assembly and connected to a data output terminal 12 used for external use, and a data input terminal 13 is connected to an internal data input circuit.

Through the above steps, conversion from a multi-bit system to a 1-bit system is performed.

Figure 4 shows the number of semiconductor memory circuit device chips that can be manufactured from one wafer, and Figure 5 shows the number of semiconductor memory circuit device chips that can be manufactured from one wafer. Figure 8g6 shows the measurement time per wafer for good quality inspection of a semiconductor memory circuit device against the number of input/output bits for the case of bit input/output and the case of 4-bit input/output. As can be easily seen from the data shown in FIGS. 4 to 6, the test time for large-diameter wafer semiconductor memory circuit devices with large storage capacity is increased by testing with multi-bit input/output using the present invention. This makes it possible to significantly improve productivity.

〔Effect of the invention〕

As explained above, the semiconductor memory circuit of the present invention has a redundant address input terminal, a redundant data input/output terminal, and first and second terminals whose connection states can be switched.
By providing the switch, it is possible to change the number of bits of input/output data.

In particular, after performing a non-defective inspection in the input/output state of a 9-bit system, 1
By converting to a bit-based input/output state, a 1-bit-based semiconductor memory circuit can be obtained in a short inspection time.

Furthermore, the present invention can standardize much of the design and development of semiconductor storage devices with different bit numbers of input and output data, and can shorten the design and development period in response to the recent increase in capacity. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 and FIG.
The figures are the circuit diagrams of switches 1 and 15 shown in Figure 8g1, respectively, and the graphs shown in Figures 4 to 4 show the number of chips versus wafer diameter, the measurement time for wafer M, and the measurement time per wafer versus the number of bits of input/output data, respectively. It is. 1゜15...Switch circuit, 2a-2d...
...Memory cell section, 3a-3d...Y decoder, 4...X decoder, 5a-5d...
...Sense amplifier/data input circuit, 6...
・Redundant data input/output terminal, 7...Redundant address input terminal, 8.10...Switch switching signal input terminal, 9.11...7Aze, 12...・・・
...Data input/output terminal, 13...Data input terminal. Kaya1koku84-@ ″Y-Left eye

Claims (1)

[Claims] a plurality of memory cell sections, an address decoder that enables access to a specified memory cell of the plurality of memory cell sections specified by an input address signal, and the specified memory cell provided corresponding to the plurality of memory cell sections. In a semiconductor memory circuit device having a plurality of sense amplifiers/input circuits for inputting/outputting signals to/from a semiconductor memory circuit, any one of an address input terminal connected to the address decoder, a redundant address input terminal, and the sense amplifier/input circuit a data input/output terminal connected to the redundant data input/output terminal, the redundant address input terminal, and the address decoder;
and a second switch capable of switching each of the sense amplifiers and input circuits that are not connected to the data input/output terminals from a state in which they are connected to each of the redundant data input/output terminals to a state in which they are connected to the data input/output terminals.
A semiconductor memory circuit device comprising a switch.