JPS61239U - 超高周波回路基板のろう付け構造 - Google Patents
超高周波回路基板のろう付け構造Info
- Publication number
- JPS61239U JPS61239U JP1984084489U JP8448984U JPS61239U JP S61239 U JPS61239 U JP S61239U JP 1984084489 U JP1984084489 U JP 1984084489U JP 8448984 U JP8448984 U JP 8448984U JP S61239 U JPS61239 U JP S61239U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- metal base
- ultra
- high frequency
- frequency circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Die Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図は本考案の一実施例で分離斜視図に示し、第2図
は第1図のA−A線載置状態側断面、第3図は本考案の
異なる実施例の分離斜視図、第4図は第3図のCC線載
置状態側断面。 図において1は回路基板、2,4は金属基台、21,4
1は凹部、3,5は低温ろう薄板、31は突起、42は
凹穴、51は突起をそれぞれ示す。
は第1図のA−A線載置状態側断面、第3図は本考案の
異なる実施例の分離斜視図、第4図は第3図のCC線載
置状態側断面。 図において1は回路基板、2,4は金属基台、21,4
1は凹部、3,5は低温ろう薄板、31は突起、42は
凹穴、51は突起をそれぞれ示す。
Claims (3)
- (1)金属基台と、該金属基台の所定位置に固着される
超高周波回路基板と、該金属基台と回路基板との間に介
在しそれらを固着するための該回路基板の外形よりも小
形な低濾ろう薄板を配置する構成であって、該金属基台
と低温ろう薄板とは相互に位置決め手段を備えたことを
特徴とする超高周波回路基板のろう付け構造。 - (2)位置決め手段は金属基台に形成された凹部または
貫通孔と、低温ろう薄板に形成された該金属基台の凹部
または貫通孔と嵌合する突起とからなることを特徴とす
る実用新亭登録請求の範囲第1項に記載の超高周波回路
基板のろう付け構造。 - (3)位置決め手段は金属基台に形成された回路基板を
嵌合して位置決めするための枠状部と低温ろう薄板の周
囲に形成された該枠状部に接する如き突起からなること
を特徴とする実用新案登録請求の範囲第1項に記載の超
高周波回路基板のろう付け構造。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984084489U JPS61239U (ja) | 1984-06-07 | 1984-06-07 | 超高周波回路基板のろう付け構造 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984084489U JPS61239U (ja) | 1984-06-07 | 1984-06-07 | 超高周波回路基板のろう付け構造 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61239U true JPS61239U (ja) | 1986-01-06 |
Family
ID=30634047
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1984084489U Pending JPS61239U (ja) | 1984-06-07 | 1984-06-07 | 超高周波回路基板のろう付け構造 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61239U (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007012761A (ja) * | 2005-06-29 | 2007-01-18 | Tdk Corp | 半導体ic内蔵基板及びその製造方法 |
-
1984
- 1984-06-07 JP JP1984084489U patent/JPS61239U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007012761A (ja) * | 2005-06-29 | 2007-01-18 | Tdk Corp | 半導体ic内蔵基板及びその製造方法 |
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