JPS6123892B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a current comparison type differential amplifier circuit, and in particular to a reverse-acting NPN type transistor, and furthermore, an integrated injection logic circuit (Integrated Injection Logic Circuit).
It relates to a differential amplifier circuit using a current mirror circuit based on Injection Logic (hereinafter referred to as I ² L).

[Prior art]

Conventionally, what is known as a differential amplifier circuit is a voltage comparison type circuit that amplifies the difference voltage between two input signals. FIG. 1A shows a conventional differential amplifier circuit.

As shown in Figure 1A, a pair of transistors
Connect the emitters of Q ₁ and Q ₂ in common and connect them to constant current source I. Since the constant current source I has a very high impedance, each transistor Q ₁ and Q ₂ operates as an emitter follower, and its input impedance becomes very high. If the transistors Q ₁ and Q ₂ and the loads R ₁ and R ₂ are formed identically, and the input voltages V _I1 and V _I2 are equal, then
The current flowing through each transistor Q ₁ and Q ₂ becomes equal. If the input voltage V _I1 is greater than V _I2 , the current in transistor Q ₁ will be greater than the current in transistor Q ₂ . Since the emitters of both transistors are tied together and connected to a constant current source, the increase in current in transistor Q ₁ and the decrease in current in transistor Q ₂ are equal, and the output voltage V _OUT is equal to the decrease in current in transistor Q ₂ . A proportional voltage increase appears.

In this way, conventional differential amplifier circuits have very high input impedance, so the input current is small.
The output is obtained by comparing the input voltages.

In this conventional differential amplifier circuit, each transistor and resistor must be fabricated separately in an integrated circuit. The constant current source shown in FIG. 1A is also usually formed using an NPN transistor. FIG. 1B shows an example of a plane pattern when the differential amplifier circuit of FIG. 1A is formed in an integrated circuit. As shown in FIG. 1B, the transistors Q ₁ and Q 2 forming a differential pair, the constant current source transistor Q ₃₁ , and the resistors R _{1 and R 2 are} each located in an island region surrounded by isolation regions. 11 must be formed. Therefore, the area occupied in the integrated circuit increases.

When a photo cell is used as an input of a voltage comparison type differential amplifier circuit as an application of a differential amplifier, it is used as shown in FIG. 1C. The (+) and (-) inputs in FIG. 1C correspond to the V _I1 and V _I2 inputs in FIG. 1A.
_D1 is the diode of the photo cell, and a current proportional to the amount of light can be obtained. Diode _D2 is a diode for converting the current generated in _D1 into voltage.

If the optical input is weak, the current flowing through the diode _D1 will naturally be very small, sometimes on the order of 100 pA to several 100 pA. Even in such a state, the differential amplifier circuit A needs to accurately amplify the input signal. Since the diode _D1 is connected in parallel to the input of the differential amplifier circuit and the ground side, if the current generated by the diode _D1 flows to the input side of the differential amplifier circuit, accurate amplification will not be possible. Therefore, the impedance of the differential amplifier circuit is required to be extremely high, and the input current specification must be several tens of pA or less.

Furthermore, when a conventional differential amplifier circuit is used at the same time as I ² L, the signal levels of both circuits are different, so it is necessary to convert the output of the differential amplifier circuit to the signal level of I ² L (or vice versa). ). Generally, the output signal of the differential amplifier circuit has a higher voltage level than I ² L. For this level conversion, a level shift circuit is required in addition to the circuit shown in Figure 1A.
The circuit area becomes even larger.

[Purpose of the invention]

The present invention aims to improve the problems of the conventional differential amplifier circuit described above.

An object of the present invention is to provide a differential amplifier circuit that has a simple circuit configuration and occupies a small area on a semiconductor chip.

Another object of the present invention is to provide a differential amplifier circuit that does not require level conversion to I ² L when used simultaneously with I ² L.

A further object of the present invention is to provide a current comparison type differential amplifier circuit that can be configured only with I ² L.

[General explanation of the invention]

The differential amplification circuit of the present invention is an amplification circuit that uses a plurality of current mirror circuits as a current source, and combines them to take and amplify the sum or difference of currents.
1st, 2nd, 3rd, 4th with multi-collector
one collector of each multi-collector is connected to the base, the first and second inverse NPN transistors are differential input transistors, and the first and second inverse
The other collector of each of the NPN transistors and the bases of the third and fourth inverted NPN transistors are connected to a PNP transistor serving as a load current source, and the other collector of the third inverted NPN transistor is connected to the base of the third and fourth inverted NPN transistors. This is a differential amplifier that extracts differential output.

FIG. 2A is an example of a current comparison type differential amplifier that was first investigated by the present inventors. As shown in FIG. 2A, the differential amplifier of this example consists of reverse operation NPN transistors (hereinafter simply referred to as reverse NPN transistors) Q ₁ , Q ₂ , Q ₅ and PNP transistors Q ₃ , Q 5 having multiple collectors. Q It is made up of ₄ . The inverse NPN transistors Q ₁ , Q ₂ , Q ₅ have their bases connected to the first collectors C ₁₁ , C ₂₁ , C ₅₁ of the multi-collector, and the second collectors C ₁₂ , C ₂₂ , C ₅₂
A current mirror circuit is constructed between the NPN
The type transistors Q ₁ and Q ₂ are differential input transistors, and their second collectors C ₁₂ and C ₂₂ are connected to PNP type transistors that serve as current sources for the load.
Q ₃ and Q ₄ are connected. Also, PNP type transistor
Q ₃ and Q ₄ also have a current mirror circuit configuration. IN1 and IN2 are base terminals of NPN transistors and differential input terminals, respectively. The differential output current is taken out from the terminal OUT of the _second collector C52 of the NPN transistor _Q5 whose _base is connected to the second collector _C22 of the NPN transistor Q2. In FIG. 2A, Vcc is a power supply voltage terminal.

In FIG. 2A, it is assumed that an input current I ₁ is applied to IN1 and an input current I ₂ is applied to IN2.
Further, in the transistors Q ₁ and Q ₂ , it is assumed that the ratio of the current flowing through the first collector connected to the base and the other second collector is set to m. Furthermore, in the transistor _Q5 , it is assumed that the ratio of the currents of the first collector and the second collector connected to the base is set to n. At this time, the current in the second collector of the collector of the transistor Q ₁ connected to the transistor Q ₃ is mI ₁ . Transistors Q ₃ and Q ₄ also have a current mirror circuit configuration, so transistors
The collector current of Q ₄ is also approximately mI ₁ . On the other hand, the current in the second collector of transistor Q ₂ connected to transistor Q ₄ is mI ₂ . Therefore, the current flowing to transistor _Q5 is m( _I1 - _I2 ). The output current I _OUT of the transistor Q ₅ is n times the current of the first collector C ₅₁ connected to the base, so the output current is I _OUT = mn (I ₁ − I ₂ ) (1). Become. Therefore, the current gain is A _I =I _OUT /I ₁ -I ₂ =mn (2).

As can be seen from equation (1), an output current is obtained only when the input current I ₁ is greater than I ₂ . Therefore, this circuit is a current comparison type differential amplifier circuit.

The values of m and n in equation (2) are transistors Q ₁ ,
It can be arbitrarily set by changing the area between the first collector connected to the base and the other second collector in Q ₂ and Q ₃ .

FIG. 2B is an example of a planar pattern diagram of the transistor _Q1 . In an inverted NPN transistor, the area of the base 21 is constant and the area of the collector 2 is
When the areas of 2 and 23 are changed, the current amplification factor is approximately proportional to the ratio of the collector area to the base area. In FIG. 2B, the area of the collector _C11 connected to the base (the connection point of the wiring 24 to the base is 25) is S _C1 . Let the area of the other collector _C12 be S _C2 . Furthermore, if the base area is S _B , the current amplification factors β ₁ and β ₂ of the collectors C ₁₁ and C ₁₂ are β ₁ =kS _C1 /S _B (3) β ₂ =kS _C2 /S _B ......(4) becomes. Here k is a proportionality constant. Therefore, the currents I _C1 and I _C2 flowing through the collectors C ₁₁ and C ₁₂ are respectively I _C1 = β _{1 I B =} kS _C1 / S _B I _B (5) I _C2 = β ₂ I _B =kS _C2 /S _B I _B (6). Therefore, the ratio of the currents in the collectors C ₁₁ and C ₁₂ is I _C2 /I _C1 =S _C2 /S _C1 =m, which is proportional to the ratio of the collector areas. Therefore, the value of m can be set by arbitrarily changing the collector area.

When a photo cell is used in the current comparison type differential amplifier circuit shown in FIG. 2A, a photo cell _D1 is connected in series to the input of the photo cell as shown in FIG. 2C. In Figure 2C, the differential amplifier
The (+) input of _A1 is the IN2 input of FIG. 2A, and the (-) input is the IN1 input. The output of this circuit is connected to (-), and the reference bias current I
If _ref is given, the output current will also increase when the input (+) (IN2 input) increases. When a photo cell is connected in series with the input as shown in FIG. 2C, all the photovoltaic current generated in the photo cell _D1 by the optical input flows to the amplifier, and this current is amplified.
Therefore, unlike the voltage comparison type differential amplifier circuit shown in FIG. 1C, there is no need to worry about leakage current.

In this way, the current comparison type differential amplifier circuit becomes very effective when combined with a photo cell.

The present inventors further investigated the current comparison type differential amplifier circuit shown in FIG. 2A, and invented a current comparison type differential amplifier circuit that can be constructed using only I ² L.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 3A shows an embodiment of the differential amplifier of the present invention. The differential amplifier shown in FIG. 3A has a configuration using I ² L. In Figure 3A, Q ₂₁ , Q ₂₂ ,
Q ₂₃ and Q ₂₄ are I ² L lateral PNP transistors,
Used for base grounding. In Figure 3A,
Q ₁₁ , Q ₁₂ , Q ₁₃ , and Q ₁₄ are I ² L inverted NPN transistors with a current mirror configuration. In Figure 3A, Q ₁₁ and Q ₂₃ , Q ₁₃ and Q ₂₂ , Q ₁₂ and Q ₂₄ ,
Q ₁₄ and Q ₂₁ each constitute I ² L.

In the differential amplifier shown in Figure 3A, the input terminal IN1 is the base terminal of the inverse NPN transistor _Q11 .
input applied to (current drawn from the base I ₁ )
A current proportional to the difference between the input terminal IN2, which is the base terminal of the inverse NPN transistor Q ₁₂ (current drawn from the base I ₂ ), is amplified, and the second current of the inverse NPN transistor Q ₁₃ is amplified. It is output from the output terminal OUT, which is the collector terminal C ₁₃₂ of. That is, each transistor Q ₁₁ , Q ₁₂ , Q ₁₃ ,
If the first and second collector areas of Q ₁₄ are equal and the injector current I _ioj1 = injector current I _ioj3 , then the sink current of the second collector C ₁₄₂ of the inverse NPN transistor Q ₁₄ is I ₁ and the inverse NPN The sink current of the second collector C ₁₂₂ of the type transistor Q ₁₂ is (I _ioj4 −I ₂ ), and the sum of both is (I _ioj4 −I ₂ +I ₁ ). At the connection point M, the injector current I _ioj2 and this sum (I _ioj4 −I ₂ +I ₁ ) are compared, and the difference between the two {I _ioj
2 −(I _ioj4 −I ₂ +I ₁ )} is an inverse NPN transistor Q ₁₃
flows into the base of the , and is output from the OUT terminal. That is, here the injector current I _ioj4 =
If the injector current is I _ioj2 , the output current is I ₂
−I ₁ .

In this circuit, increasing the injector current I _ioj2 or transistors Q ₁₁ , Q ₁₂ ,
The first collectors of Q ₁₃ , Q ₁₄ C ₁₁₁ , C ₁₂₁ , C ₁₃₁ ,
From the area of C ₁₄₁ , the second collector C ₁₁₂ , C ₁₂₂ ,
By increasing the area of C ₁₃₂ and C ₁₄₂ , the current gain can be increased.

FIG. 3B shows a planar pattern diagram of the differential amplifier having the I ² L configuration shown in FIG. 3A in an integrated circuit. In FIG. 3B, in the circuit of FIG. 3A, I _ioj1 = I _ioj2 =
Let I _ioj3 = I _ioj4 , and NPN transistors Q ₁₁ , Q ₁₂ ,
A pattern is shown when the area of each collector of Q ₁₃ and Q ₁₄ is constant (that is, m=n=1).
In FIG. 3B, 60 is an N-type semiconductor (Si, etc.) substrate, 6
1 is the injector region (P-type region that becomes the emitter of the horizontal PNP transistor, 62 and 62' are the horizontal
This is a P-type region that serves as the collector of the PNP transistor and the base of the inverted NPN transistor. Furthermore, 63 is an N-type region that becomes the collector of the inverse NPN transistor, and dotted lines indicate electrode wiring, and cross marks indicate electrode contact portions to each region.

Furthermore, in FIGS. 3A and 3B, the injector currents I _ioj1 , I _ioj2 , I _ioj3 , and I _ioj4 can be arbitrarily set by adjusting the injector facing length.

FIG. 4A shows the length of the base region 62 of the transistors Q ₁₁ to _{Q 13} facing the injector region 61.
7 is a diagram showing a planar pattern in the case where the current is adjusted by changing the opposing length L ₂ between L ₁ and the transistor Q _14. FIG. In FIG. 4A, L ₂ is chosen to be 1.5 times L ₁ , and according to this ratio the injector currents I _ioj1 , I _ioj3 , I _ioj4
and I _ioj2 flows.

Similarly, as a method of adjusting the injector current, a method as shown in FIG. 4B is also possible. In FIG. 4B, the distances M ₁ and M ₂ between the bases of transistors Q ₁₁ , Q ₁₂ , Q ₁₄ and transistor Q ₁₃ facing the injector are changed. In this way, the injector current _Iioj2 can be made larger than _Iioj1 , _Iioj3 , and _Iioj4 .

In the above embodiment, the base grounding
Input the collector of PNP transistor IN1, IN
It is also possible to construct a circuit in which the emitter of a PNP type transistor with a common base is connected to 2,... and the emitter is input. In this case, since the base of the PNP transistor is grounded, there is an advantage that the input impedance can be lowered. This PNP transistor can be made identical to the I ² L lateral PNP transistor.

〔summary〕

The advantages of the differential amplifier of the present invention will be described below.

The differential amplifier of the present invention is a current comparison type differential amplifier circuit.

The differential amplifier of the present invention has a simple circuit configuration. In particular, since it can be constructed using only I ² L, the circuit area becomes extremely small.

The differential amplifier of the present invention is an inverse amplifier used for I ² L.
It uses an NPN transistor and a PNP transistor with a common base, and can be directly connected to I ² L for normal logic operation.

Since the differential amplifier of the present invention is a current comparison type circuit, when used in combination with a photo cell,
Since a photo cell can be placed in series with the input, it has the advantage of not requiring high input impedance, unlike conventional circuits.

The differential amplifier of the present invention can operate with a Vcc of approximately 0.7V.

The amount of feedback can be set arbitrarily by changing the collector area of the inverse NPN transistor.

The main points of the configuration of the differential amplifier of the present invention will be described below.

A differential amplifier circuit that combines multiple current sources to calculate the sum and difference of currents and amplify them.

A differential amplifier circuit that uses a current mirror circuit as a current source.

A differential amplifier circuit that uses a circuit that connects the collector of one of the inverted NPN transistors to the base as a current mirror circuit.

A differential amplifier circuit that uses an I ² L circuit injector as a constant current source.

In a current mirror circuit, this is a differential amplifier circuit that changes the collector area of the inverted NPN transistor to create a difference in the current sinking ability between each collector.

A differential amplifier circuit that changes the current value of the current source by changing the length of the base of the inverse NPN transistor facing the injector.

A differential amplifier circuit that has a grounded base PNP transistor on the differential input side and uses the emitter of the PNP transistor as the input.

[Brief explanation of the drawing]

FIG. 1A is a schematic circuit diagram showing a conventional differential amplifier circuit. FIG. 1B is a plan pattern diagram when the differential amplifier of FIG. 1A is formed in an integrated circuit. FIG. 1C is a schematic circuit diagram when a photocell detection signal is used as an input to the differential amplifier circuit of FIG. 1A. FIG. 2A is a schematic circuit diagram showing a differential amplifier first studied by the inventors. FIG. 2B is a plan pattern diagram of the transistor _Q1 when the differential amplifier circuit of FIG. 2A is formed in an integrated circuit. FIG. 2C is a schematic circuit diagram when a photocell detection signal is used as an input to the differential amplifier circuit of FIG. 2A. FIG. 3A shows an embodiment of the present invention and is a schematic circuit diagram of a differential amplifier circuit composed of I ² L. FIG. 3B shows a planar pattern diagram when the differential amplifier circuit of FIG. 3A is formed in an integrated circuit. Figures 4A and 4B show the injector current I _ioj2 in the differential amplifier of Figure 3A.
FIG. 3 is a planar pattern diagram of an integrated circuit to show an example of an adjustment method. Q ₁ , Q ₂ , Q ₃₁ , Q ₅ , Q ₁₁ , Q ₁₂ , Q ₁₃ , Q ₁₄ ...
Inverted NPN transistor, Q ₃ , Q ₄ , Q ₆ , Q ₂₁ ,
Q ₂₂ , Q ₂₃ , Q ₂₄ ...PNP type transistor, Vcc...
...Power supply voltage terminal, IN1, IN2...Input terminal,
OUT...Output terminal, 62, 62'...Base region of reverse NPN transistor, 63, 63'...Reverse NPN
Collector area of a transistor.

Claims (1)

[Claims] 1. A first inverted NPN transistor having a first collector and a second collector, the first collector being electrically connected to the base, and the emitter electrically grounded; , a second inverted NPN transistor having a second collector, the first collector electrically connected to the base, and the emitter electrically grounded; and first and second collectors; a third inverse transistor having a first collector electrically connected to the base, a first collector electrically connected to a second collector of the second inverse NPN transistor, and an emitter electrically grounded; an NPN transistor; and a first collector and a second collector, the first collector being electrically connected to the base and the second collector of the first inverted NPN transistor; the second collector is the second inverse
A fourth transistor is electrically connected to a second collector of the NPN transistor, the second collector is electrically connected to the base of the third inverse NPN transistor, and the emitter is electrically grounded. reverse
an NPN transistor; a first input terminal that is the base terminal of the first inverted NPN transistor; a second input terminal that is the base terminal of the second inverted NPN transistor; and a third inverted NPN transistor. electrically connected to the output terminal which is the second collector terminal of the first inverted NPN transistor, the first and second collectors of the first inverted NPN transistor, and the first and second collectors of the second inverted NPN transistor. and a constant current circuit configured to output a differential output current of the input currents of the first and second input terminals from the output terminal. 2. In the differential amplifier circuit according to claim 1, the constant current circuit has first, second, third, and third circuits, each having an emitter electrically connected to a power supply and a base electrically grounded. The collector of the first PNP transistor is electrically connected to the second collector of the first inverted NPN transistor, and the collector of the second PNP transistor is electrically connected to the second collector of the first inverted NPN transistor.
electrically connected to the second collector of the fourth inverted NPN transistor; the collector of the third PNP transistor electrically connected to the base of the first inverted NPN transistor; and the fourth PNP transistor A differential amplifier circuit characterized in that the collector of is electrically connected to the base of a second inverted NPN type transistor. 3. In the differential amplifier circuit according to claim 2, the first inverse NPN transistor and the third
PNP type transistor, second inverted NPN type transistor and fourth PNP type transistor, third inverted
NPN transistor and second PNP transistor, fourth inverted NPN transistor and first PNP
type transistor, first, second, third, and
A differential amplifier circuit comprising a fourth integrated injection logic circuit I ² L. 4. The differential amplifier circuit according to claim 3, wherein the injector current values of the first and fourth I ² L are equal. 5. The differential amplifier circuit according to claim 4, wherein the injector current value of the third I ² L is greater than or equal to the injector current value of the second I ² L. . 6. In the differential amplifier circuit according to claim 1, 2, 3, 4, or 5,
A differential amplifier circuit characterized in that in at least one of the first, second, third, and fourth inverted NPN transistors, the second collector area is larger than the first collector area. 7. In the differential amplifier circuit according to claim 1, 2, or 3, the first and second input terminals each have a grounded fifth and a grounded base emitter, respectively. A differential amplifier circuit characterized in that the collectors of six PNP transistors are connected to each other.