JPS61238173A - Half tone recording system - Google Patents

Abstract

PURPOSE:To express and record the half tone easily and without deterioration of the resolution by including a delaying circuit, a selector circuit, an EX-OR circuit to receive the output of a clock signal and a selector circuit and the means to modulate and record by the output from the EX-OR circuit. CONSTITUTION:A delaying circuit 6 has plural delaying elements D1-D5, and these delaying elements D1-D5 are successively serially connected. Only the output of the delaying circuit 6 corresponding to the signal line to show the input density value out of lines l1-l6 is selected by a selecting circuit 7 and derived to an OR gate 9. The output from the OR gate 9 is delayed only for the period DELTAT1 and given to one side input terminal of an EX-OR gate 10. The output from the EX-OR gate 10 is given to a driving circuit 11 to drive a semiconductor laser element 12, and when the output from the EX-OR gate 10 is a high level, a laser element 12 is driven, a laser beam is modulated and irradiated to a rotating polygon mirror 14 of a scanner 13.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for expressing and recording halftones of an image.

BACKGROUND ART Conventionally, when an image is recorded using a printer, the image can only be expressed in binary form, and therefore, when expressing halftones, it is expressed in a pseudo manner using a dither method or the like. *
In laser printers and the like, attempts have been made to express halftones by controlling the output of laser light so that the amount of charge on the photoreceptor corresponds to the electric image of the laser light.

In the above dithering method, which the invention aims to solve, M! If an attempt is made to increase the Jll characteristics, the resolution will deteriorate, and pseudo-contours and moiré will occur, resulting in deterioration of the output image. Many proposals have been made for configuring dither matrices, but they have not yet been sufficiently improved.

Furthermore, in the case of the semiconductor laser described above, the output of the laser is highly temperature dependent, and it is difficult to control the intensity of the laser light by simply controlling the laser (input current).

An object of the present invention is to provide a halftone recording method that can easily and reliably express and record halftones without reducing resolution.

Means for Solving the Problems The present invention provides a delay circuit that delays a clock signal by a plurality of different times, a selector circuit that derives the output of the delay circuit corresponding to the gradation of a video signal, and a clock signal and a selector circuit. EX-, which receives the output of
This is a halftone recording method characterized by including an OR circuit and means for modulating and recording the output from the EX-OR circuit.

According to the present invention, the rear signal and the signal delayed by the delay circuit in accordance with the gradation of the video signal are
Given to R date. The output from the EX-OR date is provided to a recording means. As a result, the recording means performs the recording operation for the delay time, so that the width in the scanning direction can be changed by one dot.

Embodiment FIG. 1 is a block diagram of an embodiment of the present invention. The clock signal from the clock signal generation n1 is sent to the frequency dividing circuit 2,
A decoder 3 and a video signal source 4 such as a CCD (Charge-■■■□ Coupled Device)
given to. The waveform of this clock signal is shown in Figure 2 (1)
The period W1 corresponds to the scanning period of one dot. Therefore, as will be described later, the 0 frequency divider circuit 2, which derives a video signal of 1 dot during this period W1, divides the clock signal by 1/2 as shown in FIG. 2 (2). Line this branched signal! 10 to the correction circuit 5, and a line 711 to the delay circuit 6. The output from delay circuit 6 is given to selector circuit 7. This selector circuit 7 has a plurality of aerolog switches A1-80.

The analog video signal from the video signal II4 is applied to an analog/digital converter 8, where it is converted into a multi-level digital video signal indicating the gray level of the input image, and is applied to the decoder 3. The decoder 3 divides the signal into six gradations and outputs the signal indicating the minimum density value as the line! 1 through analog switch A
1, line the signal indicating the second concentration value! 2 to the analog switch A2. Similarly, the signals indicating the 3rd to 5th positions are connected to the line J! 3~J! 5 to the analog switches A3 to A5-, and output the signal indicating the highest concentration value to the line! Analog switch via 6, A6
Derived as follows. Therefore, in the period W1 corresponding to one dot, the line! 1~! One of the six is always at a high level. Note that the input/output of the video signal source 4 and the decoder 3 is performed in synchronization with a clock signal.

The delay circuit 6 has a plurality of delay elements D1 to D5, and these delay elements D1 to D5 are connected in series. The delay times caused by each of the delay elements D1 to D5 are all equal, and each time the input signal passes through each of the delay elements D1 to D5, it is delayed by a period P.

line! A clock signal applied via line 11 is applied to delay element D1 and is also applied via line node 12 to analog switch A1. The output from the delay element D1 is delayed by a period P and given to the next delay element D2, and the line! 13 to the analog switch A2.

Similarly, delay elements D 2 , D 3 , D 4
, D 5 for periods 2 P and 3 P, respectively.
, 4 P, S Delayed by P and line J! 14~J! 1
7 to analog switches A3 to A6.

The output from analog switches A1 to A6 is OR date 9
is given to each input terminal of Here, 7sag switch A
1 to A6 are line J! 1 to) Conductive when the signal from G is high level. Therefore, in period W1, the line! Only the output signal of the delay circuit 6 corresponding to the signal line indicating the input density value from 1 to Noro is selected by the select circuit 7 and derived to the OR date 9.

The output from OR5'-)9 is delayed by a period ΔT1 and applied to one input terminal of EX-OR date 10. The correction circuit 5 corrects the signal shown in FIG. 2 (2) given via the line 710 by the delay period ΔT1 of the OR date 9 (as shown in FIG. 2 (3)) and outputs the signal as shown in FIG.
-Give to the other input terminal of OR date 10. EX-O
The output from the R date 10 is given to a drive circuit 11 that drives the semiconductor laser element 12, and when the output from the EX-OR date 10 is at a high level, the laser element 12 is driven and the laser beam is modulated. The light beams are irradiated onto the printed surfaces 11 and 14 of the scanner 13. The scanner 13 includes a rotating polygon 14 and a motor 15 that rotationally drives the rotating polygon 14. The laser beam from the laser element 12 is reflected by the rotating polygon 14 and forms an image on a photoreceptor 16. be done. The axis of the photoreceptor 16 and the axis of the rotating polygon mirror 14 are perpendicular to each other. As the polygon mirror 14 rotates, the light beam on the photoreceptor 16 is scanned along the axis of the photoreceptor 16. be done. Around this photoreceptor 16, a charging corona discharger 18, a magnetic brush developing device 19, a transfer corona discharger 20, and a peeling corona discharger n21 are arranged in order along the rotational direction 17. After the photoreceptor 16 is charged by the action of the charging corona discharger 18, an electrostatic latent image is formed by irradiation with laser light. This electrostatic latent image is visualized by a magnetic brush developing device 19. Further, in the transfer area, the toner image on the photoreceptor 16 is transferred to a sheet of recording paper, and the transferred recording paper is peeled off by a peeling corona discharger 21 and conveyed to a fixing device.

Next, with reference to FIG. 2, the operation for expressing halftones of an image will be described. For example, when the input image density value is at the fourth level, line 14 is
only will be at a high level.

Hence the line! The signal from 15 is delayed by period 3P as shown in FIG. 2(4)! and is derived into OR date 9. The output from OR date 9 is delayed by ΔT1 and output from EX-OR date 1 as shown in FIG. 2 (5).
0 to one input terminal. Here, the output of EX-OR date 10 is shown in #2 diagram (6). This EX-
Among the output signals from the OR date 10, the high level period corresponds to the delay time 3P of the delay element D3.
The drive circuit 11 is activated only during this period 3P. As a result, the laser beam is irradiated from the laser element 12 for a period 3P and turns red. Therefore, out of one dot on the photoreceptor 16, only the width in the scanning direction corresponding to the period 3P is developed in black. In the case of the remaining input density values, the scanning direction and width of one dot are changed and recorded in accordance with each delay time. This makes it possible to express and record a grayscale image having six intermediate tones between white and black.

In this way, halftones are expressed by changing the dot width in the scanning direction, so there is no reduction in image resolution, and it is possible to prevent image deterioration due to false contours, mowing, etc.

In the above embodiment, the input image is expressed in six gradations, but the decoder 3 converts it into an even larger number of gradations, and a corresponding number of delay elements and analog switches are provided to express an even larger number of gradations. In this way, it is possible to obtain a gradation characteristic closer to the original image.

Although a semiconductor laser is used in the above embodiment, a laser beam may also be used. In this case, a modulator is used to pass and cut off a continuous beam of light from the laser element depending on the signal from the EX-0 date 10. , the beam light from this modulator may be guided to the scanner 13.

Effects As described above, according to the present invention, it is possible to express halftones without reducing the resolution, and it is possible to record clear grayscale images.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a waveform chart for explaining the operation of the embodiment shown in the figure. 1... Clock signal generator, 2... Frequency dividing circuit, 3...
... Decoder, 4... Video signal source, 6... Delay circuit, 7... Selector circuit, 8... Analog/digital converter, 10... EX-OR date, 11... Drive Circuit, 12... Semiconductor laser element, 13... Scanner, 16... Photoreceptor, D1-D5... Delay element, A
1~A6...Analog switch

Claims (1)

[Scope of Claims] A delay circuit that delays a clock signal by a plurality of different times, a selector circuit that derives an output of the delay circuit corresponding to the gradation of a video signal, and receives the clock signal and the output of the selector circuit. EX-
A halftone recording method comprising: an OR circuit; and means for modulating and recording using the output from the EX-OR circuit.