JPS61238120A - Switching operation detection circuit for field effect transistor - Google Patents

Abstract

PURPOSE:To eliminate the waste time of a system such as an inverter circuit by connecting a photocoupler turned on when the gate potential of a field effect transistor (TR) is lower then a source potential between a gate with a source being the drive circuit side of the field effect TR. CONSTITUTION:A gate resistor R1 is connected to the gate G of the field effect TR 1 and a main power supply 4 and a load 3 are connected in series between the gate and a source S. On the other hand, the positive side of an ON power source in an ON power supply 7 and an OFF power source 8 connected in series is connected to the power supply terminal 2a of the gate resistor R1 and the negative side of the OFF power source is connected to the power supply terminal 2a of the gate resistor R1. A diode 13 and a photocoupler 9 connecting a photocoupler input current limit resistor 14 in series are connected between the gate G and the source S of the field effect TR 1. A limit power supply 10 is connected to the output terminal 9a of the photocoupler 9 and an OFF detection signal line 12 detecting the OFF state of the field effect TR 1 is connected to an output terminal 9a.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a detection circuit for detecting an OFF state during a switching operation, for example, in a drive circuit for a high-power field effect transistor.

[Conventional technology]

In a drive circuit for a power MO3 type field effect transistor, there is a delay time due to various causes from when a field effect transistor OFF command is output until the field effect transistor is actually turned off.

However, in a drive circuit such as an inverter device configured by connecting two field effect transistors in series, the field effect transistors must be controlled alternately. Turn off one field effect transistor to prevent it from turning on.
After detecting the state, the O of the other field effect transistor is
It is necessary to output N instructions.

It is necessary to know the OFF state of the discharge field effect transistor, but conventionally, such an OFF state detection means was not used, and a certain amount of time was allowed between the OFF command and the ON command, and the transistor was turned ON at the same time. They were simply trying to avoid a situation that would become a situation.

A conventional field effect transistor drive circuit and an example of its operation will be described with reference to FIGS. 4 to 8.

Figure 4 is a drive circuit diagram of a conventional field effect transistor, where 1 is a field effect transistor, R1 is a gate resistor to soften the ON/OFF operation of the field effect transistor, 3 is a load, and 4 is a main Power supply SW2 is a switch; 7 is an ON power source for turning on the field effect transistor 1; and 8 is an OFF power source for turning field effect transistor 1 off.

Here, a gate resistor R0 is connected to the gate (hereinafter simply referred to as G) of the field effect transistor 1, and a gate resistor R0 is connected between the drain (hereinafter simply referred to as D) and the source (hereinafter simply referred to as S) of the field effect transistor 1. A main power source 4 and a load 3 are connected in series.

On the other hand, the ON power supply 7 and the OFF power supply 8 connected in series
The positive side of the N power supply is connected to the power supply terminal 2a of the gate resistor RI via the switch SW, and the negative side of the OFF power supply is connected to the power supply terminal 2a of the gate resistor R via the switch SWI. .

Also, the negative side of the ON power supply 7 connected in series and the O
A connection point 7a on the positive side of the FF power supply 8 is connected to a source S of a field effect transistor l.

In this case, the input capacitance between G and 8 of the field effect transistor 1 is ON as shown in the equivalent circuits of FIGS. 5 and 6.
It is expressed as CG in the state, , CGo in the OFF state, and generally C1l<C (12), and there is a mirror capacitance CGtl due to the Miller effect between D and 3 of the field effect transistor 1. do.

In such a circuit configuration, the operation when the field effect transistor 1 is turned on will be described first with reference to FIG.

In FIG. 7, time 1=1. Turn on switch SW1 with
When the switch SW2 is turned OFF, the voltage V of the ON power supply 7 whose voltage is 1 is applied between G-8 of the field effect transistor 1 via the gate resistor R, and thereby the voltage between G-3 VCS rises toward voltage V in an exponential curve with time constant RIXCcs+.

In this process, at time 1=12, the voltage between G-3 is vGs
When reaches the threshold voltage VTM, the drain current ■.

begins to flow, and the voltage VIIg between D and 5 begins to fall accordingly.

At this time, there is a mirror capacitance CGI due to the mirror effect between G and D of the field effect transistor 1, so it takes a certain period of time, that is, from time 1 = 12, until the voltage VOS between D and 3 decreases considerably due to this mirror capacitance CGI1. 1=1.
It remains in a stationary state (flat state) for a period of time until .

Also, time 1=1. When the voltage VGS between G and 3 is reached, each internal capacitance of the field effect transistor 1 starts to increase, so that the voltage VGS between G and 3 becomes 1 at time 1. The stationary state is maintained from 1 to 14.

And when time 1=14, field effect transistor 1
Since the increase in the internal capacitance of G-3 stops, the voltage VGs between G-3 leaves the stagnant state and returns to the voltage V, with a time constant R+
It rises with an exponential function curve of ×'Ca5z. ' Next, a description will be given based on FIG. 8 when the field effect transistor 1 is turned off.

In FIG. 8, time 1=1. Turn off switch SWl with
When the switch is set to V. 3 decreases toward the voltage -2 in an exponential curve with a time constant R1xccs.

In this process, time 1=1. Because the internal capacitance of the field effect transistor 1 begins to decrease when it becomes ■. , enters a stationary state, and time 1=1. This stationary state is maintained until .

When time 1=17, the internal capacitance of the field effect transistor 1 stops decreasing, the drain current I starts to decrease, and the voltage V between D and 3 starts to increase, so the mirror capacitance due to the Miller effect Due to the influence of COD, the voltage VG3 between G and 3 remains in a stationary state.

Then, when time 1=18, the mirror effect ends and G-3
■ Voltage between. , again moves towards −V2 with the time constant RI
It decreases with an exponential curve of CG5+.

[Problem that the invention seeks to solve]

As mentioned above, in the drive circuit of a power MOS type electric field/effect transistor, the voltage of the ON power supply or OFF power supply is applied between G-3 of the field effect transistor before the field effect transistor is actually turned ON. It takes time for various reasons to reach the state or OFF state.

Therefore, for example, two field effect transistors are turned on alternately, such as in a voltage type inverter device.

In a circuit that is turned off, the short-circuit prevention period must be designed with a certain margin so that two field effect transistors do not turn on at the same time, which results in wasted time in the system and has a negative effect on the characteristics of the inverter. This was causing problems.

However, 0FFa′ of this field effect transistor
For example, even if you try to detect the current state with a detector attached to the output side of a field effect transistor, that is, even if you attach a current detector that detects the drain current, depending on the circuit conditions, the drain current of the field effect transistor may not flow. The OFF state of the field effect transistor cannot be detected.

Furthermore, even if a detector is installed to detect the drain-source voltage, for example, in a voltage-type PWM inverter, etc., a freewheeling diode is installed in the opposite direction between D and 3, so when this freewheeling diode is on, a field effect occurs. Even when the field effect transistor is turned off, the drain-source voltage does not change, and this voltage detector cannot detect the off state of the field effect transistor.

Therefore, the present invention provides an O
Considering that there is a particular delay in the time from when the FF voltage is applied until the field effect transistor actually turns OFF, a circuit is provided to detect when the field effect transistor actually turns OFF. The purpose of this circuit is to eliminate the waste time of the above-mentioned system by applying the voltage of the ON power supply in response to the detection signal from the circuit.

[Means for solving problems]

For this reason, the present invention is characterized in that a photocoupler that turns on when the potential of the gate of the field effect transistor becomes lower than the potential of the source is connected between the gate and source of the field effect transistor.

[Effect]

In such a configuration, the field effect transistor is OF
When in the F state, the potential of the gate G of the field effect transistor becomes lower than the potential of the source S.

Therefore, a current flows into the input of the photocoupler, and the photocoupler is turned on.

〔Example〕

The present invention will be described in detail below with reference to FIGS. 1 to 3.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, where 1 is a power MOS field effect transistor, R1 is a gate resistor for softening the ON/OFF operation of the field effect transistor, and 3 is a load. , 4 is a main power supply, sw, , sw is a switch, 7 is an ON power supply for turning on the field effect transistor 1, 8 is an OFF power supply for turning off the field effect transistor 1, and 9 is a power supply for turning off the field effect transistor 1. photocoupler,
10 is a control power supply, 11 is a pull-up resistor, 12 is an off detection signal line, 13 is a diode, and 14 is a photocoupler input current limiting resistor.

Here, a gate resistor R1 is connected to G of the field effect transistor 1, and a main power source 4 and a load 3 are connected in series between G and 3 of the field effect transistor.

On the other hand, ON power supply 7 and OFF power supply 8 connected in series are turned on.
The positive side of the power supply is connected to the gate resistor R via the switch SWI.
The negative side of the OFF power source is connected to the power source terminal 2a of the gate resistor RI via a switch SW.

Also, the negative side of the ON power supply 7 connected in series and the O
A connection point 7a on the positive side of the FF power supply 8 is connected to the source S of the field effect transistor 1.

A photocoupler 9 having a diode 13 and a photocoupler input current limiting resistor 14 connected in series is connected between G-3 of the field effect transistor 1.

A pull-up resistor 11 is provided at the output terminal 9a of this photocoupler 9.
A limited power supply 1o is connected through the output terminal 9a, and an OFF detection signal line 12 for detecting the OFF state of the field effect transistor 1 is connected to this output terminal 9a.

In such a configuration, switch sw is turned off,
Switch sw! Turn on and turn off Voltage of power supply 8 -■2
The operation when is applied between G-3 of the field effect transistor 1 will be explained based on FIG.

As shown in FIG. 2, time 1=1. When the voltage -V2 of the OFF power supply 8 is applied between G and S of the field effect transistor 1, the voltage between G and 3 of the field effect transistor 1 becomes VaS
decreases towards −■2.

Time 1=1. When Vas becomes 0, the drain current becomes ■. =0, that is, the field effect transistor 1 is in the OFF state.

After this time, ves becomes a negative voltage, that is, the gate G
The potential of the source S becomes lower than the potential of the source S.

Here, when the potential of the gate G becomes lower than the potential of the source S, a current flows to the input of the photocoupler 9 via the diode 13 and the photocoupler input current limiting resistor 14, and the photocoupler 9 enters the N state.

As a result, the output terminal 9a of the photocoupler 9 becomes in the state of signal output O, which means that the OFF state of the field effect transistor has been detected.

In Fig. 2, from time 1=18 to time 1=19, VGs is a positive voltage, so a considerable leakage current flows through field effect transistor 1, and field effect transistor l is in the OFF state. It is assumed that it has not.

In this embodiment, the diode 13 is used to prevent current from flowing to the input of the photocoupler 9 when the potential of G of the field effect transistor 1 is higher than the potential of S, and the photocoupler input current limiting resistor 14 is photocoupler 9
This is a resistor to prevent excessive current from flowing to the input.

In this case, the photocoupler input current limiting resistor 9 may be omitted.

As described above, in the embodiment of the present invention, only the ON state of the photocoupler is used, and considering that the ON operation of the photocoupler is very fast, the O and FF states of the field effect transistor, which is a high-speed switching element, are used. Even when used as a detection element, the influence of the delay time of the photocoupler is small.

Next, a second embodiment of the present invention will be described based on FIG.

This second embodiment uses a diode 15 as shown in FIG.
A series circuit consisting of a voltage dividing resistor 16 and a voltage dividing resistor 16 is connected between G-3 of the field effect transistor, and a transistor 17 is connected between the diode 13 and the input terminal of the photocoupler 9, so that the divided voltage of the voltage dividing resistor 16 is The configuration is such that the voltage is applied to the base of the transistor 17.

Since an amplified current flows through the input terminal of the photocoupler between the second G-3, the sensitivity of the photocoupler is increased.

〔Effect of the invention〕

As described above, according to the detection circuit during switching operation according to the present invention, the photocoupler that is turned on when the potential of the gate of the field effect transistor becomes lower than the potential of the source is connected to the drive circuit of the field effect transistor. Since it is connected between the gate and source on the side, it is possible to detect the OFF state of the field effect transistor, and by this detection, for example, it can be turned on and off alternately.
It is possible to eliminate wasted time in systems such as inverter circuits using individual field effect transistors.

Furthermore, since a photocoupler is used, the insulation of the circuit is improved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the present invention in detail, FIG. 3 is a circuit diagram showing another embodiment of the present invention, and FIG. 4 8 to 8 are circuit diagrams of conventional field effect transistors and waveform diagrams for explaining their operations. DESCRIPTION OF SYMBOLS 1... Power MO3 type transistor, 9... Photocoupler, 12... Signal line, 13... Diode, 14
...Resistance for photocoupler input restriction. Agent Masuo Oiwa (and 2 others) 17 Figure 1 + j Figure 3 Figure 2 Figure 8 I7 Telephone 6 Procedural correction minor voluntary 6% 1119 Showa Month/day

Claims (1)

[Claims] A photocoupler that turns on when the potential of the gate of the field-effect transistor becomes lower than the potential of the source is connected between the gate and source of the field-effect transistor, and a signal based on the switching operation is detected from this photocoupler. A switching operation detection circuit for a field effect transistor, characterized in that: