JPS61231698A - Clamping circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

BACKGROUND OF THE INVENTION This invention relates to a clamp circuit for shifting the lowest or highest peak of a human input signal to a predetermined reference level.

When the level of the input signal fluctuates rapidly 1. A normal clamp circuit cannot follow this quickly, and the output signal deviates from the clamped state, and it takes a relatively long time before the peak of the input signal is clamped to the reference level. It took a long time.

SUMMARY OF THE INVENTION The present invention provides a method for handling signals even if the input signal becomes unclamped due to rapid level fluctuations.

It is an object of the present invention to provide a clamp circuit that quickly returns to a clamped state.

The clamp circuit according to the present invention includes a differential amplifier circuit to which a reference voltage is input to one input side, a clamp capacitor connected between the input terminal and the other input terminal of the differential amplifier circuit described in 1. a feedback circuit that guides the output of the charging or discharging circuit and the differential amplifier circuit to the other input terminal;
It is characterized by comprising a switching element provided in the charging or discharging circuit of the clamp capacitor, and a comparison circuit that detects that the output of the differential amplifier circuit exceeds a predetermined limit value and controls the switching element. do.

With the above configuration, the following operations are performed.

In a circuit that clamps the lowest peak of an input signal to a reference voltage, when it is detected that the output voltage of the differential amplifier circuit exceeds a limit voltage (higher than the reference voltage), the charge on the clamp capacitor is forced to The output voltage is controlled so as not to exceed a certain voltage. In a circuit that clamps the highest peak of a human input signal to a reference voltage, when the output voltage is detected to be less than the limit voltage (lower than the reference voltage), the clamp capacitor is forced to charge and the output voltage is controlled so that the voltage does not drop below a certain level. In this way, when the input signal fluctuates rapidly and the output voltage attempts to exceed a certain limit, the output voltage is held at this certain limit voltage, so that the peak level to be clamped does not deviate significantly from the reference voltage. is prevented, and the transition time from the non-clamped state to the clamped state is shortened.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Following the description of the embodiments, a case in which the clamp circuit according to the present invention is used in an optical wireless AE telemeter device will be described in detail.

(1) Overview of optical wireless AE telemeter device Monitoring 7 Automatically detects tool wear, breakage, and other abnormalities in machine tools by using acoustic emissions (hereinafter referred to as AE) generated during cutting and breakage. There is a system. In such a system, an optical wireless AE telemeter device modulates the specific frequency component of the AE multiplied signal obtained from the AE sensor in the form of an optical signal from a transmitter.

A specific frequency component of one element is reproduced by transmitting the signal, receiving it at the receiver side, and performing 11i:pg.

FIG. 1 shows an outline of the electrical configuration of the optical wireless AE telemeter device, and FIG. 2 shows the waveforms of the output signals of each block in FIG. 1.

An AE sensor 11 is placed near a tool or workpiece of a machine tool. The AE multiplied signal output from the AE sensor 11 is sent to a narrow band pass filter I2 having an amplification function. In the AE double signal power spectrum, a peak appears near 50 and llz during normal cutting.
It has been found from many experimental results that a peak appears around 100 to 300 KIIz when the tool wears or breaks. Filter I2 has a center frequency around 100 to 300 KIIz. In this way, the frequency component representing the presence or absence and degree of abnormality in the tool passes through the filter 12 and is input to the envelope detection circuit 13. This detection circuit 13 rectifies and amplifies the signal, and further takes its envelope. The waveform of the output signal C of the detection circuit 13 includes all the information necessary for diagnosing an abnormality in the tool.

The pulse oscillation circuit I4 generates a pulse d having a frequency (for example, about 100112) that is low enough not to destroy the information contained in the waveform of the signal C and a pulse width that is similarly considered. This pulse d is input to the synthesis circuit 15 together with the signal C. The synthesis circuit 15 is a type of switching circuit that is controlled on and off by the pulse signal d, and converts the envelope represented by the signal C during the pulse width of the pulse d.

It works to bring it down to zero level. This clarifies the zero level of signal C.

The output signal e of the synthesis circuit 15 is frequency-modulated in an FM modulation circuit 16 using a carrier wave of an appropriate frequency, and is input to two light emitting diodes and their driving circuit 17. An optical signal representing a carrier wave modulated with signal e is emitted from the light emitting diode into the air.

The transmitter IO consists of the circuits 12-17 described above, which are powered by a battery, for example a lithium battery.

When multiple AE sensors are provided.

A transmitter IO is prepared for each AE sensor 11, respectively. The frequencies of the carrier waves in these plurality of transmitters 10 are different from each other.

The receiving side device includes a plurality of receiving heads 21 and a receiver 20 that processes the signals received by these receiving heads 21. The receiving head 21 includes a photodiode array 22 that receives optical signals transmitted from the nine light-emitting diode autos 17 and converts them into electrical signals, and an amplification circuit 23 for the output signals of the photodiode array 22. The received signals of the plurality of reception heads 21 are sent to the adder circuit 24 of the receiver 20.
is added. Mutual circumference.

When simultaneously receiving optical signals from a plurality of transmitters IO using carrier waves with different wave numbers, the output signals of the adder circuit 24 are converted to intermediate frequencies by the intermediate frequency converting circuit 25, so that one The transmitted signal of the summer transmitter 10 is separated into two parts.

Each separated received signal is demodulated by a frequency demodulation circuit 26. In cases where the carrier frequency is drifting due to temperature changes or the like, an offset is added to the demodulated signal f, and its zero level may not necessarily match the zero level of the signal C representing the envelope. As can be seen from the signal e, the zero level of the signal C is clearly defined as the lowest peak value of the pulse component. Therefore, the clamp circuit 27 clamps (level-shifts) the signal f so that the peak (lowest level) of the pulse included in the demodulated signal f matches the zero level of the receiver 20. In this way, the zero level of the envelope signal is correctly reproduced. A low-pass filter 28 with an amplification function,
A pulse component representing a zero level is removed from the clamped signal g.

It is reproduced as an envelope signal C or a signal.

As mentioned above, the waveform of the envelope signal C contains all the information necessary for diagnosing tool abnormalities.
This waveform must be correctly reproduced on the receiver 20 side. However, due to frequency drift in the carrier wave, a DC component may be added to the demodulated signal f. A pulse signal d for clarifying the zero level is synthesized with the envelope signal C in the synthesis circuit 15, and after demodulation, the signal f is clamped in the clamp circuit 27 to reproduce the zero level, so that the amplitude of the envelope signal is correct. Reproduced.

With this configuration, for example, in FM modulation, demodulation can be performed using PI, 1, (phase locked loop).
, the frequency and voltage of the demodulated signal (
(2) Even if there is a deviation between the self-oscillation frequency of the controlled oscillation circuit and the self-oscillation frequency, there is no need to adjust it, and there is no need to particularly precisely configure the modulation/demodulation circuit.

(2) Problems with the clamp circuit FIG. 3 shows an example of a specific configuration of the clamp circuit (FIG. 1, reference numeral 27). The human power signal V in FIG. 3 corresponds to the signal f in FIG. 1, and is the output signal V. Un 1 corresponds to signal g. Voltage signal source 34 provides a reference level ±VR for clamping, which in the embodiment of FIG. 1 is set to zero. Person, output signal ■, in the circuit of Fig. 3.

n The waveform of ■ is shown in FIG.

out This clamp circuit includes an operational amplifier OP1. An input terminal is connected to the inverting input side of this operational amplifier OP1 via a clamp capacitor C1, and
This inverting input side is grounded via a resistor R1.

A reference voltage source 34 is connected to the non-inverting input side of the operational amplifier OP1. The output of the operational amplifier OPI is fed back to the inverting input via the diode DI, and this inverting input is connected to the output terminal.

It is assumed that the charge stored in the capacitor C11 is zero, and the potential difference between both ends of this capacitor CII is also zero.

At this time, v = v. V > VR deou
Since t + n ou, the output of the operational amplifier OP will be less than the voltage VR,
No current flows through the diode Dl.

At time t, input signal ■ falls below voltage VR 1
+n This is the lowest peak. Since the potential difference between both ends of the capacitor C11 is zero, V=V and o<VR, so the output voltage of the operational amplifier OP exceeds VR, and the diode D1 becomes conductive. The capacitor C1l is charged by the current flowing through the diode D, and the output V rapidly rises. ■ -out
o
When ut■R is reached, the output of the operational amplifier lJ OP becomes the voltage VR.
Since the voltage falls below, the diode DI turns off.

Charging of capacitor C11 is stopped. I wanted to.

The output voltage V is clamped to the reference level VR. Ru.

When the input voltage Vjn rises from its lowest level to exceed the level VR, the output voltage V also follows and rises, so that V=V.

out + n Input voltage v1n first falls to the lowest peak (time t
) After that, the diode D1 is kept in the off state from the time when the diode Dl transitions from on to off until the time t when it falls to the next lowest peak, and during this period, the charge in the capacitor C1 slowly flows through the resistor R1□. is discharged. The amount of change in the potential difference between both ends of the capacitor C1□ due to discharge during this period is assumed to be ΔV.

This is because at time t when the input signal V again falls below the reference level vR, the potential of the capacitor C11 has decreased by ΔV due to discharge.

v=v−ΔV. v Ku VR Teao
Since ut Rq ou, the diode D becomes conductive again and the capacitor C11 is charged until ``out=V''.

In this way, the lowest peak of the input signal v1o is always clamped to the reference level VR.

In the circuit of FIG. 3, if the difference (fluctuation amount) between the lowest peak value of the input signal Vin at time t1 and the lowest peak value of the same signal at time t2 is less than +ΔV, then V =
The VR clamping action is normally achieved.

Under normal operating conditions of the AE telemeter device, the normal lamp operation described above is ensured.

However, due to the occurrence of some abnormality, the lowest peak value of the input signal (2) may rise, which may impede the clamping action. For example, as shown in FIG. 4, the lowest peak value of the human power signal V1n at time t3 is ++ compared to that at time t2.
Suppose that it fluctuates by Δ■.

V = VR at the previous clamp (time t)
If out is clamped, the output at time t3 is v
=vR-ΔV, 10ΔV. If ΔVut > ΔV, then v > vR, and diode-q
out D is kept in the off state, and ■ is the standard level.
o
It will no longer be clamped to VR.

As described above, the circuit shown in FIG. 3 may come out of the clamped state when the pin value of the input signal V varies significantly. The purpose of the clamp circuit 27 shown in FIG. 1 is to reproduce the reference level of the DC signal by matching the peak value of the input signal with the reference level (for example, zero potential). If it does not operate, the reference level of the DC signal will be lost, and it is necessary to return to the clamped state as soon as possible.

(3) Improved clamp circuit (Part 1) Figure 5 is "-
1 shows an improved clamp circuit that overcomes the problems described above. In this figure, the same parts as those shown in FIG. 3 are given the same reference numerals.

Voltage source 3 that generates a voltage V+, which determines the 1st limit level.
5 and this voltage source 35. The output terminal of the output V is
It is controlled on and off by the output signal of the operational multiplier OP2, which is connected in parallel to the resistor R1□ and is connected in parallel to the resistor R1□. A switching transistor T11 is added. This added circuit increases the output V to the level V1, by making the transistor Tit conductive and discharging the charge of the capacitor C1 through the transistor T when the output V becomes equal to or higher than the level VL. Work in such a way that it won't let you go out.

FIG. 6 shows the states of the person, output signal, diode, and transistor of FIG. 5. The operation at time t11°t is the same as time 1. in FIG. It is the same as that in 12.

Due to the occurrence of some abnormality, the output voltage V at time t13
When it exceeds the first limit level vL, this is detected by the operation adder 11 OP2, and the transistor T
turns on. As a result, the charge in the capacitor C11 is discharged, so that the output (2) is maintained at the level V but . When the lowest peak appears in the input signal V, and the voltage falls, the output voltage V naturally follows this and falls.

Input voltage V, around time t. When V begins to fall, the output voltage V ut also falls accordingly. Transistor T11 is turned off at this time.

The charge on the capacitor C returns to its original state where it is slowly discharged through the resistor R11.

When the lowest peak appears in the input signal V1n at time t15, the output voltage V 1 follows it and becomes equal to or higher than the reference ut level V'R)°. In this case, calculation increase 11
The output of the single device OPl rises and the diode D1 becomes conductive.

Capacitor C is charged and output V is at reference level 11
Out is clamped to VR.

As described above, even if the level of the input signal rises abnormally, the output signal can quickly return to the state where it is clamped to level VR. If the two series of added circuits do not exist, the output signal V follows the input signal V, as shown by the dashed line in FIG.
1 hour out +
Even if it reaches nt, the output V is higher than the reference level VR1
5 is out. The unclamped state continues until the charge in the capacitor C11 is slowly discharged through the resistor R11 and the output V becomes equal to or less than the output voltage VR.

If the output signal V exceeds the upper limit level V+, ut In this case, the output signal V is cut at level V1.

out Historical signal waveforms may not be partially reproduced, but
Since the output signal V exceeds the level Vt when some abnormality occurs, there is no adverse effect on the wireless telemeter device.

The circuit shown in FIG. 5 clamps the lowest peak of the input signal to a reference potential. In this type of circuit, the output voltage is at an upper level (higher than the reference level).
Based on this detection, the clamp capacitor is forcibly discharged, and the charge on the clamp capacitor is controlled so that the output voltage does not exceed the upper limit level.

In a type of circuit that clamps the highest peak of the input signal to a reference level, it detects that the output voltage has fallen below the lower limit level (lower than the reference level) and clamps it.
The charge on the clamp capacitor may be controlled so that the capacitor is forcibly charged and the output potential does not fall below the lower limit level.

(4) Improved clamp circuit (part 2) FIG. 7 shows a modified example of the clamp circuit.

The reference level of this circuit is set to the ground level.

In this figure, transistors T, T.

T, TT and current source 36 are differential amplifier circuit 29
30' 33. Transistor T31 connected in series with transistor T33 and another transistor T constitute a current mirror of the output stage;
An output resistor R23 is connected to the output resistor R23.

The feedback element that supplies charge for clamping to clamp capacitor C21 is transistor T. A bias is applied to this transistor T24 by a circuit consisting of a transistor T2 and a resistor R24, and the emitter of the transistor T24 is connected to the collector (point QC) of a transistor T28.The transistor T24 is made up of a transistor T22゜T. Charge is supplied to the capacitor C21 via a current mirror.A transistor T2B is connected to the emitter of the transistor T24.

When the input signal vlo abnormally increases by 1, the capacitor C
The switching element that controls the discharge of the charge of 2 is the transistor T25. Voltage dividing resistors R, R are connected between the base of the transistor T (point Q,) and the ground, and the voltage at this connection point (point Q) is applied to the transistor T T d 25
° 26.

FIG. 8 shows the voltage waveform at each point in the circuit of FIG. 7 and the states of transistors T 1 and T 2 .

It is assumed that a certain amount of charge is stored in the capacitor C21 before time t21. There is a potential difference between the input signal (2) and the base potential (point Qa) n of the transistor T27 depending on the amount of charge charged in the capacitor C21. The charge in the capacitor C2□ is slowly discharged as the base current of the transistor T27. Since transistors T27 to T30 and Ta2 constitute a negative feedback amplifier circuit as described above, points Q and Q
The potentials of b are equal. If the potential at point Qa is positive, a certain value of current ■11 flows through transistor TT, and due to the action of the current mirror consisting of transistors T31'31'33T, resistor R23
A current I'll also flows through the transistor T32,
Positive output voltage V=I-R is output terminal out 11
Appears on the 23rd.

When the input terminal V1o reaches its lowest peak value at time 21, the potential at one point Q becomes negative due to the charge stored in the capacitor C2I.The potential at point Qc changes according to that at point Q, so the potential at point Qc changes accordingly. The potential also decreases, l
- Transistor T24 becomes conductive. At this time, transistor T26 is off. As a result, current {circle around (2)} flows through the transistors T 1 and T 2 , and the capacitor C21 is charged through the transistor T22 by the current mirror made up of the transistors T 1 and T 2 .

As a result, the potential at point Qa increases, and the potential at Q also increases, and 1
When the electric potential C8 at point Q becomes zero potential (earth potential), transistor T24
is turned off. Therefore, ■12" becomes 0, and charging to the capacitor C21 stops. The potentials at points Qa and Q5 are both zero potential, the transistor T is in a cutoff state, and the output voltage V also has a capacity of 33
It is held at around 0LIt.

After the input voltage Vin rises from the lowest peak until time t22 when the next lowest peak arrives, the output voltage ■ should be equal to the input voltage V.
+n changes. During this time, capacitor C21 supplies the base current of transistor T27 and slowly discharges. Therefore, when the input signal V reaches its lowest peak again at time t22, the potential at point Q is 1n
a time t2
Since it was clamped to zero potential at 1, it becomes a negative potential. As a result, the output voltage V is again clamped to the capacity ut.

When the potential at point Q rises due to a sudden rise in the level of input voltage ■In (time t), a at point Qb at point 2 increases.
23 potential force rises, and the potential at point 2 Qd also rises. The potential at point Qd is applied to transistor T2. rises above VBE of transistor T2. conducts, and the charge in the capacitor C2 is discharged (current 113), so that the potential at point Qa is prevented from rising.

Therefore, the output voltage V will never be lower than a certain constant potential V. Since the currents flowing through the transistors T31 (T33) and T32 are equal, this constant potential Vt is given by the following equation.

= 19 ~ V - (R23/R21) 'V np time t
When the input voltage Vjn starts to decrease at 24, point Q
Since the potential at point QQ also decreases, the potential a at point QQ
b' c also decreases, transistor T25 turns off, and the output voltage V becomes V
1. It becomes below.

Due to the parfocality of the limiter action greater than out, a difference occurs in the output voltage (2) shown in FIG. 8 by the solid line and the broken line (Ou). When there is a limiter effect, the output voltage Vout returns to the state where it is clamped to zero potential again at time t25 after time t9, as shown by the solid line. On the other hand, if there is no limiter effect.

As shown by the broken line, the output voltage ■ is the voltage ■, hereafter ut -, and there is a delay in returning to the clamped state.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the electrical configuration of a wireless AE telemeter device, and FIG. 2 is a waveform diagram showing an output signal of the same block. FIG. 3 is a circuit diagram showing the problem of the clamp circuit, and FIG. 4 is a waveform diagram showing the person, output signal, etc. FIG. 5 is a circuit diagram showing an improved clamp circuit. FIG. 6 is a waveform diagram thereof, FIG. 7 is a circuit diagram showing another example of the improved clamp circuit, and FIG. 8 is a waveform diagram thereof. OPl...Operation multiplier that becomes 11 differential multiplier circuits. OF2: Operational intensifier that works as a comparison circuit. C, C...Capacitor in clamp. Dl...Diode of feedback circuit. T, T...Transistor 1 as a switching element T24...Transistor of the feedback circuit. T2□ to T30...Transistors forming the differential amplifier 11 circuit. Below

Claims (1)

[Claims] A differential amplifier circuit into which a reference voltage is input to one input side, a clamp capacitor connected between the input terminal and the other input side of the differential amplifier circuit, and charging or discharging thereof. circuit, a feedback circuit that guides the output of the differential amplifier circuit to the other input side, a switching element provided in the charging or discharging circuit of the clamp capacitor, and an output of the differential amplifier circuit that exceeds a predetermined limit value. a comparison circuit that detects this and controls the switching element;