JPS61228686A - Manufacture of semiconductor coupled superconducting circuit device - Google Patents

Abstract

PURPOSE:To increase the Josephson current of a semiconductor coupled superconducting circuit device and to decrease the dispersion in the Josephson current in a chip, by making it possible to form first and second superconducting electrodes on a high- concentration impurity layers in a close proximity of a distance of about the coherence length of electrons. CONSTITUTION:A superconductor, which is provided in contact with the upper part of a semiconductor substrate 1, is patterned and a superconductor pattern 2 is formed. An anode oxide film 3, whose thickness can block a tunnel current, is grown on the surface of the pattern 2 by using an anode oxidation method. Thereafter, the superconductor pattern, which has the anode oxide film 3 on the surface, is machined, and a first superconducting electrode 4 is formed. Then a second superconducting electrode 5, which has a part contacting with the semiconductor substrate 1 and a part, which is overlapped with the anode electrode are arranged on the semiconductor substrate 1 so that they are separated by the thickness of the anode oxide film 3. Since the thickness of the anode oxide film 3 can be controlled at the accuracy of several tens of nm, the distance between the first and second superconducting electrodes can be shortened, and uniformity is improved.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor coupled superconducting circuit device having two superconducting electrodes in close proximity to each other. A superconducting electrode and a second superconducting electrode are provided in close electrical contact on a semiconductor substrate, and the first superconducting electrode and the second superconducting electrode
A semiconductor-coupled superconducting circuit device has been proposed in which a superconducting electrode is weakly coupled to a superconducting electrode via a semiconductor substrate. The magnitude of the Josephson current flowing between the second superconducting electrodes is the first
．． In order to realize a circuit operation with a margin that increases as the distance between the two superconducting electrodes becomes shorter, the first step is to achieve the following. The distance between the second electrodes must be shortened to about the coherence length of electrons. Furthermore, when a large number of circuit devices are integrated into the same chip, it is necessary to minimize variations in the distance between the first and second superconducting electrodes within the chip.

However, in conventional semiconductor-coupled superconducting circuit devices, as described in Nikkan Kogyo Shimbun, November 10, 1984, page 4 ((Fig. 3)) Because the method of dividing the conductor is used, the distance between the first and second conductive electrodes is 0.2 μm, which is about one order of magnitude larger than the coherence length of electrons. Furthermore, when microfabrication techniques such as the electron beam 4 exposure method, dryer, and etch method are used, the variation in the distance between the first and second superconducting electrodes within the same chip is 0.
．． This cannot be ignored for a value of 2 μm. As a result, with conventional manufacturing methods, it is difficult to realize a semiconductor-coupled superconducting circuit device that uses a large Josephson current and has little variation in Josephson current within the same chip. The present invention eliminates the above-mentioned conventional drawbacks, shortens the distance between the first and second image conduction electrodes to about the coherence length of electrons, and j! An object of the present invention is to provide a method for manufacturing a semiconductor-coupled superconducting circuit device that can reduce variations in the distance between first and second conductive electrodes within the same chip. In manufacturing the combined superconducting circuit device, a first superconducting electrode that is in electrical contact with the semiconductor substrate is provided on the semiconductor substrate, and a tunneling current is applied to the surface of the first superconducting electrode by an anodizing method. forming a second superconducting electrode that has a portion that overlaps with the first superconducting electrode and is in electrical contact with the semiconductor substrate via the insulating layer; A method for manufacturing a semiconductor-coupled superconducting circuit device is obtained, the method comprising the steps of:

(Detailed explanation of the structure) The present invention solves the problems of the prior art by adopting the above-described structure. FIG. 1 is a diagram showing the manufacturing process of a semiconductor coupled superconducting circuit device according to the present invention. o (alt (c
t) is a plan view% (b) (C) (e) is (f) is (a)
o (a), (b) are cross-sectional views at the X-Y position of
), the superconductor provided in contact with the semiconductor substrate l is patterned to form a superconductor pattern 2. Next, using an anodic oxidation method, as shown in (C), an anodic oxide film 3 with a thickness that blocks tunneling current is formed on the surface of the superconductor pattern 2.
grow. After that, a superconducting pattern having an anodic oxide film 3 on the surface is processed to form a first superconducting electrode 4.
Next, as shown in (,=), a second superconducting electrode 5 having a portion in contact with the semiconductor substrate l and a portion overlapping with the anodic oxide film 3 is formed.
1. The second image conduction electrode is arranged on the semiconductor substrate l with a distance of the thickness of the anodic oxide film 3. Since the thickness of the anodic oxide film can be controlled with an accuracy of several tens of nanometers, the first The distance between the second superconducting electrodes can be made shorter than the same distance that can be achieved by conventional microfabrication techniques such as lamination or etching, and its uniformity is also improved. Above result 1
By using the manufacturing method of the present invention, it is possible to realize a circuit device that uses a larger dielectric current than in the past, and furthermore, when a large number of circuit devices are formed at the same time, variations in the dielectric current can be reduced.

Embodiments of the present disclosure will be described in detail below with reference to the drawings.

FIG. 2 is a manufacturing process diagram of a three-terminal semiconductor-coupled superconducting circuit device showing an embodiment of the present invention. ) is a cross-sectional view corresponding to X-Y in the plan view (d). For example, (
As shown in a), a silicon substrate 6 is prepared, and an 8i01 film 7 is grown on its main surface to a thickness of, for example, 150 nm by K thermal oxidation. Thereafter, using a photoresist as a mask, for example, boron (1018 to 1018) is selectively applied to necessary areas.
Ion implantation is performed at a density of 19.73 cyr to form a high concentration impurity layer 8 (a) Next, for example, using a buffered hydrofluoric acid solution, 8iQ! corresponding to the high concentration impurity layer 8 is formed. Apertures 9 are provided in the membrane 7, and (b) a superconducting pattern 10 made of, for example, niobium is deposited to a thickness of, for example, 200 nm by, for example, a sputtering deposition method. And for example CF
, patterning is performed by a dry etching method using gas (C) Note that (C) is a 1L cross-sectional view at the X-Y section of (d). For simplicity, (d) shows the substrate 6 and the superconducting pattern. Only IO is shown, and then, for example, 1569 ammonium pentaborate and 1120-ethylene glycol are 760-
The superconducting butter 710 is anodized using an electrolytic solution dissolved in water, and the surface of the superconducting pattern 100 is covered with an anodic oxide film 11.

At this time, for example, if a current of 0.5 mA an-2 is supplied, the niobium anodic oxide film 1 with a thickness of about 2 nm is applied to the applied voltage IV.
1 grows 0 to 9 When a voltage of about 10V is applied, about 20
It can be formed with a niobium anodic oxide film 11 of nm thickness (e
) Next, as shown in the plan view (f), the superconducting pattern 108 is further patterned by, for example, a CF4 plasma etching method to form the first superconducting electrode 12. 6 and the first superconducting electrode 12 are shown.@Then, after plasma cleaning the exposed surface of the high concentration impurity layer 8 using, for example, argon gas, 1. The film is deposited, and then a second
A superconducting electrode 13 is formed. (g) Then, for example (h)
As shown in the figure, the silicon substrate 6 is etched from the back surface opposite to the main surface using, for example, an aqueous solution of ethylenediamine and pyrocatechol until a thickness of 300 nm remains. ◎Then, a normal silicon process is performed. using well-known methods, e.g.
A film is grown on the back surface of the substrate 6 to form a gate insulating film 148.Next, cyalium is deposited to a thickness of about 700 am by, for example, a vapor deposition method on the underside of the gate insulating film 14, and phosphorus is deposited on the underside of the gate insulating film 14. Gate electrode 1 is patterned by wet etching or dry etching using acid.
◎Additionally, an opening 16 is provided in the anodic oxide film 11 to form a contact portion to the first superconducting electrode 12.If necessary, a wiring layer, a resistive element, etc. are formed using a well-known method. A three-terminal semiconductor superconducting circuit device is completed by incorporating the above results. The first and second superconducting electrodes 12 and 13 are placed on the high concentration impurity layer 8 with the thickness of the anodic oxide film 11 separated. As mentioned above.

The thickness of the anodic oxide film 11 can easily be several tens of nm, and the electron coherence length at 4.2°K is 10 am.
The first one is about the same distance as the first one. Second superconducting electrode 12. .

Moreover, according to the anodic oxidation method, variations in the anodic oxide film thickness 11 within the chip can be ignored, and the first. The uniformity of the distance between the second superconducting electrodes 12 and 13 is improved. Since it can be formed on a high concentration impurity layer, the Josephson current of the semiconductor coupled superconducting circuit device can be increased, and furthermore, the fluctuation of the Josephson current within the chip can be reduced.

[Brief explanation of the drawing]

(b) [c) (el is a cross-sectional view showing the manufacturing process of a three-terminal semiconductor-coupled superconducting circuit device for demonstrating semiconductor-coupled superconductivity according to the present invention, (dl(f) is a plan view of 69 , Fig. 3 is a cross-sectional view of a conventional semiconductor coupled superconducting circuit device. In the figure, 1.16 is a semiconductor substrate, 2 and 10 are superconductor patterns, and 4 and 12. conductive electrode, 3.
11 is an anodic oxide film -5, 13e, 18 is a second superconducting electrode, 9 is an opening, 6 is a substrate, 7 is a StO film, 8 is a high concentration impurity layer, 14 is a gate insulating film, 15 is a gate It is an electrode. Tei 1 Diagram (c) 17 TeiIfIMadenshodenshu16Half-mouthful treatment

Claims (1)

[Claims] In manufacturing a superconducting circuit device combined with a semiconductor, a first superconducting electrode that is in electrical contact with a semiconductor substrate is provided on the semiconductor substrate, and a tunneling current is applied to the surface of the first superconducting electrode by an anodizing method. a second superconducting electrode having a portion overlapping with the first superconducting electrode and electrically contacting the semiconductor substrate via the insulating layer; 1. A method for manufacturing a semiconductor coupled superconducting circuit device, comprising the steps of: