JPS61227440A - Clock selection controller of network terminator - Google Patents

Abstract

PURPOSE:To ensure the stability of clock selection to noise by inverting the switching state of a selection circuit only when it is detected that a reception frame signal is incoming consecutively for a prescribed number of times within a hysteresis width provided before and after a reference value in excess of the reference value from a smaller delay time direction or a 1 larger direction. CONSTITUTION:An identification circuit 105 is provided with the 1st detection circuit 106 detecting that a received frame bit is incoming for a prescribed number of times continuously in a hysteresis width provided before and after the reference value in excess of the reference value from a smaller delay time direction and a larger direction, and the 2nd detection circuit 107, and the changeover of a reproduced clock and a fixed phase clock by a selection circuit 103 is performed only when it is detected that the received frame signal is incoming continuously for a prescribed number of times within the hysteresis width in the other state in excess of the reference value from one state. Thus, instable operation of the selection circuit 103 due to noise or jitter is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The connection form between a network termination device and a terminal device is identified, and a retiming clock is appropriately selected in accordance with the connection form. that time,
In order to prevent malfunctions due to noise, jitter, etc., the identification reference value has a hysteresis characteristic with N protection stages.

[Industrial application field]

The present invention relates to a clock selection control device for network termination equipment.

The clock selection control device of the present invention is used, for example, in an integrated services digital network (ISDN), and selects the retiming clock in the network termination device according to the connection form between the subscriber premises network termination device and the subscriber terminal. Automatically selects and switches between a reproduced clock using a digital phase locked loop (DPLL) or the like and a fixed phase clock.

[Conventional technology]

In digital integrated service networks, there are three types of connections between subscriber premises network terminals (NT) and subscriber terminals (TI): simple path, expanded path, and point-to-point. be. FIG. 2 shows the simple path format, FIG. 3 shows the expanded path format, and FIG. 4 shows the point-to-point format.

According to the plan that is being recommended by the CCITT, the maximum pressure 111 between the network terminal equipment NT and each terminal TE (1) to T E (n) is determined by the single path type a''t'l in Fig. 2.
OO ~ 150m or less, 5 in expanded path form
00m or less, or less than 1km point-to-point. The round-trip delay from sending a transmit frame to receiving a receive frame at the network termination device is 10 to 14 ams in the simple path mode.
In point-tsuku-point form, it is 10 to 32μ easy.
be. In the expanded path mode, it is lO~32μ, but the delay difference between terminals is limited to 1.4AsK.

Communication is carried out between the network termination device and the terminal via the T line and the R line, and the channel structure on the T line and the 8 line is, for example, 6
4KB/a information channel B (1).

B(2) and a 16 KB/s signal channel D are time-division multiplexed, and a frame synchronization signal F (hereinafter referred to as a transmission frame signal or reception frame signal) is added to determine the transmission and reception timing. be done. lQQ%AMI is used as the transmission code.

In the simple path configuration, it is preferred to use a fixed phase clock as the retiming block in the network termination equipment. This is because the distance between the terminals is very limited in this form, so the data from each terminal on the network termination equipment side has almost no eye pattern, so the received signal is
When attempting to reproduce the clock using a PLL, etc., the amount of jitter in the clock is large, making it unsuitable for use as a retiming block, whereas the round trip delay has a small delay of 10μ3 to 14μ, so it can be used even with a fixed phase clock. This is because data from each terminal can be read.

On the other hand, in the case of the expanded path mode and point-to-point mode, the round trip delay is wide, ranging from 10 to 32 μS, so with a fixed phase clock, the signal from each terminal side is read on the network termination equipment side. However, since the time difference between each terminal is limited to within 1.4 μs, the amount of jitter is small even with a reproduced clock using a DPLL or the like, so it is appropriate to use this reproduced clock as a retiming clock.

In this way, the retiming clock in the network termination equipment can be either a fixed phase clock or a DP clock depending on the connection form.
It is preferable to select and use a reproduced clock based on LL or the like. As a method for automatically making this selection, there is a method of replacing each connection type with the distance from the network termination device to the shortest terminal and automatically reading it) and then performing clock switching, for example, in the patent application filed in 1988-1 filed by the present applicant. 149235, entitled "Clock Selection Control System"], and a circuit equipped with a protection circuit having hysteresis characteristics to prevent frequent fluctuations in identification results due to noise, etc. has also been proposed.

FIG. 5 shows a block diagram of the main parts of this system. Fifth
The device shown in the figure is installed in the network termination device, and 1 is a receiver, 2' is a shortest terminal distance identification circuit, 3 is a digital phase synchronization circuit, 4 is a retiming circuit, 5 is a selector, and 6 is a transmission control circuit. It is.

The shortest terminal distance identification circuit 2' uses the transmission frame signal Fo from the transmission control circuit 6 as a reference, extracts the reception frame signal Fl from the output signal from the receiver 1, and measures its delay time. The form is determined and detected, and a selection signal sm is sent to the selector 5. The selector 5 selects either the reproduced clock from the digital phase synchronization circuit 3 or the fixed phase clock from the transmission control circuit 6 as a retiming clock in accordance with the selection signal, and supplies the retiming clock to the retiming circuit 4.

A block diagram of the shortest terminal distance identification circuit 2' in the apparatus shown in FIG. 5 is shown in FIG. In FIG. 6, 21 is a frame detection circuit that detects the received frame signal F1, 22 is a pulse generation circuit that generates a reference time width, G2, 1 . G22
．． What about G23? -) circuit, Fll.

F14 is a D type 7 lip flop, F' 12, F
13 is an R8 type flip-flop.

FIG. 7 shows signal waveforms at various parts of the circuit of FIG. 6. In FIG. 7, (a) is the transmission frame signal Fo, (b)
is the received frame signal Fx, (c) is the pulse P (t) that creates the reference time width T1, (d) is the hysteresis 17 secretion time width T3
These are the waveforms of the pulses INH that create the .

To explain the operation of the device shown in FIG. 6, when the transmission frame signal F is sent from the network terminal device, the time width generating circuit 22 outputs the signal F? Lus p(t) and! An island is generated. In response to this transmission frame signal Fo, the terminal returns a reception frame signal F1.

This received frame signal F1 corresponds to section I in FIG.

The operation of the device differs as follows depending on whether K is in n, m, or ■. First, in the case of section I, since the AND circuit G21 is opened by the pulse p (t), the received frame signal F1 detected by the frame detection circuit 21 passes through the AND circuit G21 and sets the 7-lip 70-tub F13. . In this case, since the AND circuit G22 is closed by the pulse
3 is open. Therefore, if the flip-flop F13 is reset by the transmission frame signal F and then immediately reset by the reception frame signal FIK,
Selection signal S output via flip 70 knob F14
EL is always @1m, single by selection circuit 5.
The li constant phase clock for the path is selected.

In the case of section ■, the AND circuit G21 is opened in the same manner as described above], and the flip-flop F13 is connected to the received frame signal Fl.
Set by. On the other hand, AND circuit G22 also pulses! Since the flip-flop F12 is also set by the reception frame signal F1), it is opened by F).
l”-) circuit G23 is closed, so that 7 lig 7
The 0-tube F13 is never reset, and the selection signal SEL outputted via the flip-flop F14 becomes 11m in this case as well.

In the case of interval (3), the AND circuit G21 is in a closed state because the /else P(t) is 10#, and therefore the 7 lip-flop F13 is not set. Further, as described above, since the f-) circuit G23 is closed, the flip-flop F13 is not reset. As a result, the 7-stage defroster 7'F13 continues to maintain its previous output state, so the selection signal S via the flip 70-stage fF14
EL becomes . if the previous state is maintained. Therefore, this interval (2) is a dead zone due to hysteresis, and it is possible to prevent the selection signal SEL from fluctuating due to noise or jitter.

In the case of section ■, the AND circuit G21 is closed as in the section ■, and on the other hand, the dirt circuit G23 is open. reset via. Therefore, the selection signal SEL outputted via the 7-lip flop F14 is always @0'', and the selection circuit 5 is a DPLL.
Select the regenerated clock from 3.

[Problem that the invention seeks to solve]

In the device shown in Fig. 6, the selection circuit 5.0 has a hysteresis characteristic by making the section (2) in Fig. 7 a dead zone, and the selection signal S
The EL is prevented from changing frequently. However, in this case, the reference distance for separating the single pass form from the expanded path or the one-India-tsuk-I-India form is set at the boundary between sections ■ and ■, or between sections ■ and ■. The problem is that it is not clear what should be done.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In order to solve the above-mentioned problems, the clock selection control device for a network termination device of the present invention has a phase synchronization circuit 101 that extracts and reproduces a timing clock from a received signal, and a fixed phase clock generation circuit 102 that generates a fixed phase clock. , a selection circuit 103 that selects either the recovered clock from the phase synchronization circuit or the fixed phase clock from the fixed phase clock generation circuit as a retiming clock, and a reception frame bit detection circuit 104 that detects reception frame bits from the reception signal. , and compares the delay time from the transmission of the transmission frame bits to the reception of the reception frame bits detected by the reception frame bit detection circuit with a predetermined reference value, and determines the connection form between the network termination equipment and the terminal based on the magnitude of the delay time. an identification circuit 10 that identifies and controls switching of the selection circuit;
5, the identification circuit 105 detects that the received seven frame bits exceed the reference value and enter the hysteresis width provided before and after the reference value a predetermined number of times in a row from the direction of the smaller delay time. a first detection circuit 106 that detects, and that the received frame bit exceeds the reference value from the direction of the larger delay time and consecutively enters a hysteresis width provided before and after the reference value a predetermined number of times; a second detection circuit 107 for detecting the received frame bit, and inverts the switching state of the selection circuit only in response to a detection signal from the first or second detection circuit when the received frame bit falls within the hysteresis width. It is configured as follows.

[Effect]

The selection circuit 103 switches between the recovered clock and the fixed phase clock when the received frame signal exceeds the reference value of one state and falls within the hysteresis width of the other state a predetermined number of times in succession. Second detection circuit 10
6 or 107. Therefore, it is possible to prevent the operation of the selection circuit 103 from becoming unstable due to noise, jitter, etc., and it is also possible to clarify the reference distance for identifying the connection type.

〔Example〕

A clock selection control device for a network termination device as an embodiment of the present invention will be described below.

A block diagram of the shortest terminal distance identification circuit 2 in FIG. 5 is shown in FIG. In FIG. 8, the output signal from receiver l is guided to frame detection circuit 21. In FIG. The frame detection circuit 21 detects and outputs a received frame signal F from the received signal 5(1). Further, the transmission frame signal F (1 pulse generation circuit 23) is guided from the transmission control circuit 6 to the pulse generation circuit 23. The pulse generation circuit 23 is composed of a monostable multivibrator and a logic circuit, each of which is shown in FIG. As shown in the table, a pulse p (t) with a time width T3, a pulse τl with a time width T4, 2 hours @T, and an OI pulse τ8 are output.

The received frame signal Fl from the frame detection circuit 21 is guided to each input terminal of AND circuits G2 to G5. /9 pulses p(t), τ1, τ: are each led to each input terminal of the NOR circuit Gl. AND circuit G2 is this NOR circuit G1
The opening/closing is controlled by the output signal of AND circuit G3. G4.
G5. The output signal from the AND circuit G2, whose opening and closing are controlled by the nodes p (t), τ1, and τ, respectively, is the set input terminal SK of the R8 type 7 lip-flop F4.
is input.

The inverted output signal Q of the flip 70 fF4 is an AND circuit G.
It is led to the data input terminal of the D-type flip-flop fF6 via IO. The output signal Q of the flip-flop F6 is sent to the selection circuit 5 as the selection signal SEL.

The received frame signal F1 that has passed through the AND circuit G3 is led to the set input terminal S of the R8 type flip-flop F5 via the OR circuit G8. The output signal Q of the flip-flop F5 is led to the 7-bit f70fF6 via the AND circuit GIO.

The received frame signal Fl that has passed through the AND circuit G4 is sent to the reset input terminal R of the R8 type flip-flop.

It is guided to the clock input terminal CK of the counter C1 and the B input terminal of the selector 81. 7 Ritsude 70tsu 7'F1
The output signal Q of is led to the load input terminal LDK of the counter C1, and the output signal of the counter C1 is led to the A input terminal of the selector S1. A setting circuit W1 is connected to the counter C1.

When the load input signal of the load input terminal LDK"1" is input, the counter C1 receives and stores the setting value of the setting circuit Wl, and when the load input signal is @0", it is input to the clock input terminal CK. The pulses added are sequentially added to the set value, and when the added value reaches the full value (all 1s), the output signal RCO is sent out at 1!-.Therefore, this counter C1 counts N times. In this case, set the setting circuit so that the total value general fixed value=N.

A flip-flop F is connected to the control input terminal 8 of the selector S1.
A selection signal SEL from 6 is guided, and its output signal Y is guided to flip-flop F5 via OR circuit G8.

The selector S1 selects the input signal B when the input signal to the control input terminal S is 11", and selects the input signal 2 when the input signal is 10#, and outputs it as the output signal Y.

The received frame signal F1 that has passed through the AND circuit G5 is R8 type 7
A reset input terminal R of lip-flop F2 and a clock input terminal CKK of counter C2 are led. 7 lip 7
The output signal Q of the 0 block F2 is guided to the load input terminal LDK of the counter C2 via the AND circuit G7, and the count output signal RCO is guided to the reset input terminal R of the R8 type 7 lip flop fF3. The counter C2 has the same configuration as the counter C1), and is connected to a setting circuit W2.

The output signal from the OR circuit G8 is led to the set input terminal SK of the 7-rip 70-tube F3. 7ritsug 70tsubu F3
The output signal Q controls the opening and closing of the AND circuit G9, and the received frame signal F1 is guided to the input terminal of the OR circuit G8 through the AND circuit G9 and further through the AND circuit Gll. The AND circuit Gll is controlled to open and close by the selection signal 5HLK of the flip-flop F6.

The transmission frame signal F is output from the AND circuit G6. Each input terminal of G7, 7° 70° F4. F5C) It is led to each reset input terminal R and the clock input terminal CKK of flip-flop F6, and also to each set input terminal S of flip-flops Fl and F2 via D-type flip-flop F7 as a delay circuit.

The operation of the apparatus shown in FIG. 8 will be explained below with reference to the signal waveform diagram shown in FIG. In FIG. 9, (a) is the transmission frame signal Fo, and (b) is the time width T! The pulse p (t), (
C) is a pulse τt with a time width T4, (d) is a pulse with a time width Ts
pulse τ, (e) is the output signal of the NOR circuit G1, (
f) is each signal waveform of the received frame signal F1.

First, the operation when the received frame signal F1 enters the section (3) in FIG. 9 will be explained. In this case, since the output signal of the NOR circuit G1 is 0'', the AND circuit G2 is closed, and the flip-flop F4 is not set by the received frame signal Fl and is always set by the transmitted frame signal F.
It is in a reset state. Therefore, 7 rip 70
The inverted output signal of the switch F4 is always 11'', and the AND circuit GIO remains open.

In this section (2), the AND circuit G4. G5 is closed and only AND circuit G3 is open. Therefore, the received frame signal F, and the AND circuit G3. The signal is input to flip-flop F5 via OR circuit G8 and sets flip-flop F5. The l'' output signal of the flip-flop F5 is inputted to the input terminal of the flip-flop F6 via the AND circuit GIO, and the selection signal S of the flip-flop F6 is output from the flip-flop F6.
EL is sent.

When the received frame signal F1 enters the interval (3), its operation differs depending on the previous state of the selection signal SEL. When the selection signal SEL is @1'', the input terminal of the selector S1 is switched to the B side.In this section ■, the received frame signal F
Only AND circuit G4 is open for sK. Therefore, the received frame signal F1 is output from the AND circuit G4. B input terminal of selector s1, 7 rip 70 via OR circuit G8
Since the knob F5 is set, the selection signal SEL becomes @1''.

On the other hand, when the selection signal SEL is @0'', the selector S1 is switched to A@, so the received frame signal F1 from the AND circuit G4 is not directly transmitted to the OR circuit G8 via the selector S1. In this case, the received frame signal F1 resets the 7-rig 70-tube F1, thereby closing the AND circuit G6 and counter C1.
is considered to be in a countable state. Since the AND circuit G6 is open in areas other than section ■, the counter C1 is constantly loaded with the set value of the setting circuit W1 for each frame by the transmission frame signal F passing through the AND circuit G6. The count value never increases. Therefore, only when the selection signal SEL is 10'' and the received 7 frame signal F1 enters the interval ■, the counter C1 receives the received frame signal Fl input to the clock input terminal CK.
starts counting, and when the received frame signal F1 enters the interval ■ N times consecutively, it reaches its full value and sends an output signal to the A input terminal of the selector S1, and flips through the OR circuit G8. Set 70 knob F5. For this]
The selection signal 5ELFi changes from ``0'' to @1''k@.

If the received frame signal F1 that enters section 11 does not occur eight times in a row, the counter C1 is reloaded to the initial set value at the moment of interruption, so an output signal is sent from the counter C1 as long as it does not occur eight times in a row. is the front.

In this way, in this section ■, when the received frame signal F1 enters the section... from the section I side, the selection signal SEL of K is 1.
It is held as 1#, and when entering from the ° section ■ side, when that state continues N times, the selection signal SEL is @
1#, otherwise K is the previous selection signal SE
L maintains the state of @0''. Therefore, section (2) has 8 protection stages when viewed from section (2).

When the received frame signal F1 falls within the section m, the operation differs depending on whether the previous state of the selection signal SEL is 111 or @O''. When the selection signal SEL is 10#, the AND circuit Gll is closed. Therefore, there is no signal to set the flip 70 knob F5, and therefore the selection signal SEL continues to be "0".

On the other hand, when the selection signal SEL is 11" (that is, in the interval ■ or ■), the AND circuit Gll is opened by the selection signal SEL, and the flip 70 knob F3 is set by the output signal of the AND circuit G8. Then, AND circuit G9 is also opened.

Therefore, the received frame signal F1 is sent to the AND circuit G9゜Gll.
Since the flip 70 knob F5 is set via the OR circuit G8, the selection signal SEL becomes @1#, but the counter C2 operates in the same way as in the case of the above-mentioned section ■ and counts the received frame signal F. and received frame signal F
, is repeated 8 times in a row, a count output signal RCO is sent out to reset the 7-reset defrode F3. This is K] The AND circuit G9 is closed, and the flip-flop F5 is no longer set and is only reset by the transmission frame signal F. As a result, the selection signal S
EL is switched from 11'' to 10''K.

In this way, in section m, the received frame signal F1 is in section ■
When section IIK is entered from the side, if it continues N times, the selection signal SEL is switched from @1" to @0")
At other times, maintain the previous condition @1m. Also, when entering from section ■ to section ■, the selection signal SEL is 10.
``This is a decent protection from the section ■ side.''

Finally, when the received frame signal F1 enters the interval ■, the output signal of the NOR circuit G1 is '1', so the AND circuit G2
is open], so the received frame signal F1 passes through the AND circuit G2 and sets the flip 70 knob F4,
As a result, the AND circuit F6 is closed and the selection signal SEL from the flip-flop F6 becomes @O''.

As described above, in the device of this embodiment, the selection circuit 5 can distinguish between the reproduced clock and the fixed phase clock by setting the boundary between the sections ■ and ■ in FIG. 10 as a reference distance.

〔Effect of the invention〕

According to the present invention, it is possible to clearly set a reference distance for identifying a connection type, and to provide a hysteresis characteristic with a number of protection stages to the identification operation, and it is also possible to provide protection against transmission line noise, etc. The stability of clock selection operation can be ensured. As described above, the present invention is extremely effective in automatically identifying the wiring configuration in an ED/network interface 7A such as 15DN.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIGS. 2 to 4 are diagrams showing the connection form between a network termination device and a terminal, and FIG. 5 is a block diagram of a main part of a clock selection control device of the network termination device. 6 is a block diagram of the shortest terminal distance identification circuit in the device shown in FIG. 5, FIG. 7 is a signal waveform diagram of each part in the circuit shown in FIG. 6, and FIG.
This figure is a block diagram of the shortest terminal distance identification circuit in FIG. 5, and FIG. 9 is a signal waveform diagram of each part in the circuit of FIG. 8. DESCRIPTION OF SYMBOLS 1... Receiver, 2, 2'... Shortest terminal distance identification circuit, 3... Digital phase synchronization circuit, 4... Retiming circuit, 5... Selector, 6... Transmission control circuit, 21°21'...Frame detection circuit, Gl...NOR circuit, G2 to G7. G9~Gll...AND circuit,
F1 to F7...7 lips, 70 tabs, Sl...selector, 23...9 bus generation circuit.

Claims (1)

[Claims] A selection circuit (103) for selecting either the recovered clock from the phase synchronization circuit (101) or the fixed phase clock from the fixed phase clock generation circuit (102) as a retiming clock, in the received signal. a received frame signal detection circuit (104) that detects a received frame signal from the received frame signal, and compares the delay time from sending out the transmitted frame signal to receiving the received frame signal detected by the received frame signal detection circuit with a predetermined reference value. A clock selection control device for a network termination device, comprising: an identification circuit (105) that identifies the connection form between the network termination device and the terminal based on the size of the signal and controls switching of the selection circuit; a first detection circuit (106) that detects that the frame signal exceeds the reference value and enters a hysteresis width provided before and after the reference value consecutively a predetermined number of times from the direction in which the delay time is smaller; , a second detection circuit (107) for detecting that the received frame signal exceeds the reference value in the direction of the larger delay time and falls within a hysteresis width provided before and after the reference value a predetermined number of times; ), and configured to invert the switching state of the selection circuit only in response to a detection signal from the first or second detection circuit when the received frame signal falls within the hysteresis width. A clock selection control device for a network termination device.