JPS61227296A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make large a quantity of signal reading even by reducing the size of memory cell by connecting a drain of a writing transistor to a bit line, a gate to a writing word line, a source of the transistor for reading to the bit line and the drain to the reading word line. CONSTITUTION:A drain of a writing transistor Tr4 is connected to a bit line W/RB, a gate to a writing word line WW, a source to one electrode of a capacity C2 for storing an electric charge through a diffused layer forming a data electrode of a reading transistor Tr5. The other electrode of the capacity C2 is fixed to a constant potential. the transistor Tr5 is formed on the capacity C2 by using a polysilicon or monocrystal silicon. A source of the transistor Tr5 is connected to a bit line W/RB, a drain connected to a reading word line RW. Accordingly, a reading of the signal is carried out through the transistor Tr5, and by an amplifying operation, a minute signal stored in a cell can be read.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a large semiconductor memory suitable for memory cells of dynamic RAM.

[Technical background of the invention and its problems]

conventionally], memory, especially dynamic RAM (random
One transistor/one capacity memory cell as shown in FIG. 3 is widely used as the memory cell of the access memory. Cs in the figure.

Ca is a capacitor, Tr is a transistor, BL is a bit line,
WL is a word line. As described above, the dimensions of memory cells are becoming smaller year by year due to the demand for higher memory integration, and as well as the miniaturization of the entire memory cell, it is also necessary to miniaturize the capacity itself. However, the 8i0. It is difficult to reduce the thickness of the (dielectric) film below a certain level due to reliability issues, so a groove is created in the silicon substrate to substantially increase the area of the capacitance. , a memory cell has been proposed in which a capacitor is formed around it. Figure 4 shows a specific example of the configuration shown in Figure 3 that realizes this, where 1 is a P-type silicon layer, 2 is a 5
i01 film, 3 is polysilicon layer, 4 is N layer, 5 is input 1
1 (aluminum) #.

However, such a one-transistor/one-capacitance type memory cell has no problem in writing signals, but has a major drawback in that it is susceptible to noise when reading signals.

Transistor Tr.

The charge Q accumulated in the capacitor C8 via the bit line BL is transferred to the capacitor CB parasitic to the bit line BL during reading.
and Cs. Therefore, the charge Q written in the capacitor C8 at 5V flows into the bit line BL which is at 0 potential, raising the potential of the bit line BL, but the rate is ΔV =
5 C8・/(C11+CB). In a normal memory array, since a number of memory cells are connected in parallel to the bit line BLK, the capacitance CB is larger than the capacitance 11cs, and the ratio is designed to be about CB/C3=20. Therefore, a signal written at 5V drops to about 0.25V or less when read. Conventional 1 transistor/
In a one-capacity memory, this minute signal is connected to the bit line BLK.
The connected sense amplifier circuit amplifies and detects the signal. In this type of system, as memory becomes highly integrated, the capacitance tcB% increases due to an increase in the number of memory cells connected to the bit line BL.Furthermore, the read signal voltage increases due to a decrease in the capacitance C8 due to miniaturization. As ΔV becomes smaller and smaller, it becomes extremely difficult to detect changes in the potential of the bit line BL even if a highly sensitive sense amplifier circuit is used, which is a major obstacle to increasing memory integration. .

In order to overcome these drawbacks, a two-transistor type dynamic memory cell of current flow type as shown in FIG. 5 has been proposed (Japanese Patent Application No. 160521/1982). In the figure, RB is a read word line, WW is a write word line, W/RB is a bit line, and Tr, Tr3 are transistors. However, when using this method,
Element isolation between the transistors Tr, , Tr is required, and the area of the memory cell increases significantly compared to the conventional system shown in FIG. 4, which is a major obstacle to high integration.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and it increases the amount of signal readout, which is a drawback of the conventional one-transistor/single-capacitance type dynamic memory, and also increases the amount of signal readout, which is a drawback of the conventional two-transistor type dynamic memory. This is an improvement on the miniaturization of the size of the semiconductor memory, and aims to provide a miniaturized semiconductor memory that can produce a large amount of read signals even when miniaturized.

[Summary of the invention]

In the present invention, the drain of a write transistor is connected to a bit line, the gate is connected to a write word line,
The source of the transistor is connected to one electrode of a charge storage capacitor through a diffusion layer, the diffusion layer forms a gate electrode of a readout transistor, and the other electrode of the capacitor is fixed at a constant potential, The read transistor is formed on the capacitor using polysilicon or single crystal silicon, the source of the read transistor is connected to a bit line, and the drain is connected to a read word line. It is characterized by

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a memory cell circuit diagram of the same embodiment, and FIG. 2 is a configuration diagram of the same. As shown in the figure, the drain of the write transistor Tr is connected to the bit line W/RB, the gate is connected to the write word line WW, and the source is connected to the charge storage capacitor t.
It is connected to one electrode of Ct through a diffusion layer, and the diffusion layer forms the gate electrode of the read transistor T r 5. The other electrode of capacitor C2 is fixed at a constant potential. The transistor Tr is formed on the capacitor C1 using polysilicon or single crystal silicon,
Transistor Tr! The source is connected to the bit line W/RB, and the drain is connected to the read word line RW.

In FIG. 2, ZZ is P type i/recon M, 12. .

12, is N@, 13 is P 11% 141~Z 4
4 is an N polysilicon layer, 15 is a P type polysilicon layer,
16/ri8ro, 7 is Al line (bit line W/RB
). The N layer 121 constitutes the source of the transistor Tr, the gate of the transistor Tr5, and the electrode of the capacitor tC1. The P layer 13 forms an impurity layer for separating adjacent memory cells. N@12□ is the drain of the transistor Tr, the polysilicon layer 141 is the source of the transistor Tr11, the polysilicon layer 142 is the drain of the transistor Tr, the polysilicon #I5 is the drain region of the transistor Tr, polysilicon Layer 143 forms the gate of transistor Tr4.

In the above configuration, signal writing is performed on the bit line W/RB.
After charging up to 5V, the writing word line WW is raised to 5V, which turns on the transistor Tr4, and the bit line W/RB is charged to the capacitor 11c,
This capacitance is accumulated in the electrode 144 in the groove formed in the silicon substrate 11 and the N113 formed on the side wall of the groove.
12, and an insulating layer between them. The electrode 144 is usually fixed at a constant potential and shared with the capacitance of an adjacent memory cell. The N layer 121 that accumulates charges is the P layer at the bottom of the groove.
Separated by @ZJ. The charge written in this way is N by the word line WW becoming Ov.
IIK is accumulated.

Next, to read the signal, connect the read word line RW to 5
When charged up to v, the capacitance C2 becomes 5 as shown above.
When the voltage is charged up to V, the transistor Tr5 is turned on and the transistor T is connected from the word line RW.
A current flows into the bit line W/RB, which has already been lowered to Co potential, through r, and this is detected by k. When the N layer 121 of capacitor C1 is Ov,
Since the transistor Trg is off, no current flows through the bit line W/RH even if the word line RW is charged up to 5V.

An important point of the present invention is that Nl-72 between the transistor and the capacitor tc, which was not used in the past, is used as the gate of the read transistor Tr.

An example of the manufacturing process for the above structure is as follows.

That is, an isolation groove is formed on the P-type silicon substrate l by a known etching technique, and a PI layer 13 is formed at the bottom of the groove by B ion implantation. After that S i 02
An insulator made of / 8 i N / S i 02 is formed, and the 3@ film in the portion parallel to the main surface is removed by anisotropic etching, leaving the 3@ film only on the trench sidewalls. Thereafter, the A8 doped polysilicon is left in the trench to form a common capacitor electrode 14. shall be. Next, a writing transistor Tr is formed using a known technique. After forming the source and drain regions of the transistor Tr, an oxidation treatment is performed to form the read transistor T.
The gate oxide film is r5. Thereafter, polysilicon is deposited and As ions are implanted using a predetermined mask to form a source and a drain. At this time, the masked P-type polysilicon has S in a part of N@rz.
iO, so that it is installed via @. Thereafter, the polysilicon layer is etched using a predetermined mask. Next, the polysilicon layer is crystallized by irradiating it with an Ar laser. Furthermore, an 8402 film is deposited using the CVD method. After that, a contact hole is opened, and then A7427 wiring is performed.

According to the above embodiment, signal reading is performed by the transistor T
Since this is done via r5, there is no need for amplification, and even minute signals accumulated within the cell can be read out, making it possible to realize a highly sensitive memory. Also, by forming grooves in the semiconductor,
The actual capacity can be increased without reducing the degree of integration, and a memory cell that is resistant to noise has been realized. Furthermore, by providing the separation layer 13 at the bottom of the trench, a high-density memory cell could be realized. Furthermore, since the readout transistors Tr were formed in an overlapping manner without impairing the degree of integration, an ultra-high-density, island-sensitive memory cell could be realized.

Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, the drain (source) of the transistor in the embodiment may be referred to as the source (drain). Although the write/read bit line W/RB is used in this embodiment, the write bit line WB and the read bit line R are
You may use what was separated into B.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a semiconductor memory that can provide a large amount of read signals even if the memory cells are miniaturized.

[Brief explanation of the drawing]

Figure 1 shows a cell circuit diagram of an embodiment of the present invention, Figure 2 is a sectional view showing the configuration of the same cell, Figure 3 is a conventional memory cell circuit diagram, and Figure 4 shows the configuration of the same cell. The cross-sectional view shown in FIG. 5 is a circuit diagram showing another example of a conventional memory cell. Tr,...Writing transistor, Tr5...
・Reading transistor, W/RB...Bit line, WW...Writing word line, RW...Reading word line. Applicant's agent Patent attorney Takehiko Suzue IWi Figure 2 Figure 3 Figure 4ii.

Claims (2)

[Claims] (1) The drain of a writing transistor is connected to a bit line, the gate is connected to a writing word line, the source of the transistor is connected to one electrode of a charge storage capacitor through a diffusion layer, and the diffusion layer is forming a gate electrode of a read transistor; the other electrode of the capacitor is fixed at a constant potential; the read transistor is formed on the capacitor using polysilicon or single crystal silicon; A semiconductor memory characterized in that the source of the read transistor is connected to a bit line, and the drain is connected to a read word line. (2) the capacitor is formed in a groove-shaped region in the semiconductor substrate, and is provided via an insulator on an impurity layer provided to separate adjacent memory cells; 2. The semiconductor memory according to claim 1, wherein a part of the read transistor is placed on the capacitor with an insulator interposed therebetween.