JPS61224868A - Control delay compensator - Google Patents

Abstract

PURPOSE:To compensate the time delay of an output power source by providing time delay recovering means and flowing a command value current having a periodicity therethrough. CONSTITUTION:A control delay compensator is composed of a single-phase power converter 4, a current detector 5, a subtractor 6, a voltage detector 7, and a current controller 8, and the first and second changeover switches 9, 11 and time delay recovering means 30 having a memory 10 are added thereto. The value of command value current ic* during the prescribed one cycle period is sequentially written in the memory cell of the memory 10, this value is sequentially switched by the switches 9, 11 at the writing address of the value and designated. Thus, a control delay Ta due to the dead beat control, for example, corresponds to 2/512 of one cycle period T of a power source, the designated addresses of the switches 9, 11 are displaced by two addresses. Thus, the value ic* is output in the state preceded only for the prescribed time to compensate the time delay.

Description

Detailed Description of the Invention [Field of Industrial Application] This invention relates to a control delay compensator for improving the follow-up characteristics of a target value in a deadbeat control group, etc. The present invention relates to a control delay compensation device for a device in which a target value appears periodically, such as a device.

[Conventional technology]

This type of compensating sterilization device can be applied to the above-mentioned active waveform improvement device. Third
The example shown in the figure is Showa! This is a compensation control device for an active waveform improvement device proposed by Isao Takahashi, the inventor of the invention in this application, at the Institute of Electrical Engineers of Japan Semiconductor Power Conversion Study Group held on March 17, 2017 (Reference 5P)
Cff, 7-<47). In this Figure 3, (1
) is the power system.

(2) is a load, and (3) is an active waveform improvement device.

In such a device, the load currents mue, jve
, ↓we contains some kind of fault current, and the compensation current to compensate for this ↓uC, jrV6, =
Assuming that wc is flowing to the active waveform improvement device (3), the electric power R, Lu, irv, L from the power system (1) is
Each w is represented by the following formula (1).

Lu = Aue+ =uc =v = =ve + =vc --
・(t)Lw = Lw@ + =yc Here, the currents iru, Lv, from the power system (1)
It is preferable that Lvr is a balanced three-phase alternating current.

By the way, in order to compensate for such a fault current, as can be understood from equation (1) above, it is necessary to activate a current other than a balanced three-phase alternating current that has the opposite polarity and the same magnitude as the fault current. It is sufficient to supply it from the waveform improving device (3). In Figure 6.

The circuit configuration of the -phase component of the active waveform improvement device (3) is illustrated. In this FIG. 6, (4'l is a single-phase power converter, (j) is a current detector for detecting the output current IC from the single-phase power converter C, (6'
) is a subtractor, and the current detected by the current detector (,!il K (which is equal to the output current from the single-phase power converter (&)) AC and the fault current are of opposite polarity and magnitude. Equal command value current LC * Which difference is taken, L and R
is the inductance and resistance of the impedance inserted between the single-phase power converter (4'l) and the power system (1), eL- is the voltage applied from the power system (1), and (ri) is the voltage applied from the power system (1). a voltage detector for detecting voltage eL; and (t) a current controller.

Based on the voltage detected by the voltage detector (7) (which is equal to the voltage applied from the power system (1)) eL and the current deviation @(Lc''-↓C) from the subtractor (A),
According to the following equation (2), the output e of the single-phase power converter (
This is for calculating the command value voltage ec* for ().

ec” = (Lc*10Kv(L.”-4c))R+
44. -421 Here, Kv is expressed by the following formula (3).

/−9−−, Ts is 1 during sampling of the current controller (ff), and τ is a time constant (τ=−) that is determined depending on the values of L and R. It is already known that the shortest time control algorithm in a power circuit including a back electromotive force as shown in FIG. 43-41
(see t). In the power circuit shown in FIG. 6, the current controller is now controlling a certain command value voltage e
When c* is calculated, the single-phase power converter (ri) outputs voltage ec in response to the application of the command direct voltage ec*. As a result, the output current ↓C from the single-phase power converter follows the command value current 〃C* with l sample time delay.The control performed in this way is dead. This is called beat control, and an output response is made in an extremely short time to a current command with a certain predetermined directivity.The one shown in Fig. 7 is an 8g
FIG. 7 is an exemplary diagram of current follow-up characteristics in the power circuit of FIG. 6;

[Problem that the invention seeks to solve]

Deadbeat control is used in the conventional example described above, and therefore, as can be understood from FIG.
In principle, l sample time (
This results in a delay of Td) in FIG. However, this delay has a significant negative effect on K because it compensates for high-order fault power in the target power system, and in the worst case, the compensation current and the fault current may have the same polarity. Therefore, there was a problem in that the fault current actually increased.

This invention was made in order to solve the above-mentioned problems, and includes storing a certain predetermined current command value,
The object of the present invention is to provide a device capable of compensating for the above-mentioned delay in tracking, rather than outputting the signal after advancing it by l sample time.

[Means for solving problems]

The control delay compensation device according to the present invention is for a control system in which an output current is generated with a predetermined time delay following a command value current having periodicity, and is for recovering the predetermined time delay. A time delay recovery means is provided for
The command value current is set to pass through this time delay recovery means.

Further, a control delay compensation device according to another invention of the present invention includes:
The control system is for a control system in which an output current is generated with a predetermined time delay following a command value current having a periodic component and a non-periodic component, and includes a time delay recovery means through which the command value current is passed. It is configured to include an estimating function section for estimating the periodic component of the command value current.

[For production]

According to this invention, the command value current input to the time delay recovery means is outputted in a state in which it is preceded by a predetermined time, and the time delay of the output current of the control system with respect to the command value current is compensated for.

According to another aspect of the present invention, when the command value current has a periodic component and an aperiodic component.

The periodic component is estimated, and a time delay in the output current of the control system with respect to the command value current is compensated based on the estimation result.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In Figure 1, (Hiroshi) , (t) # (A) I
(ri) and (za) are similar to the conventional device shown in FIG. 5 or @6.

(10) is memory, and each /~! The value of the command value current Lc* in a predetermined l cycle period is sequentially written into the 512 memory elements numbered up to /. (
TE) is the first changeover switch that specifies the write address of the command value current ↓C* to the memory (lO), from address 1 to address 1.

Sequential busy switching [specified] (it) is memory (10)
This is the third selector switch that specifies the read address of
Do the same thing, starting from number 1! You can specify up to 1 addresses by sequentially changing the busy address. The time delay recovery means ( 3
0) is configured.

Next, the operation of this embodiment will be explained. Here,
The explanation will be given assuming that the control delay due to deadbeat control, Td, corresponds to 2151 cycles of one cycle period T of the power supply. In such a case, switch (9) and switch (/
/) and memory (lo)K are shifted from each other by a co address, for example, if the switch (9) is 1
When specifying the address, the switch (it) is 3 for □
You will be asked to specify the address. FIG. 2 shows an example of how such an address switching designation changes over time. What is shown in FIG. 3 is an operational waveform diagram of the embodiment of the present invention in FIG. Here, FIG. 3 (at is a repetitive waveform diagram of the command value current ↓C* with a period T, and the scan from address 1 to address 31 of the memory (10) by the switch (?) is performed with the period T. Therefore, the waveform of the command value current LC* for exactly 1 cycle period (that is, 1 period T) is stored in the memo +) (10) from address 1 to address 51. .

On the other hand, the read address of the memory (10) by the switch (l/) is specified to be the first address in comparison to the busy address and the above-mentioned fragrance address, as described above.
10), a waveform obtained by advancing the waveform of /cycle period ago by the address co is read out. As a result, the waveform Lc0 read from the memory (10) is
), the waveform is advanced by Td with respect to the command value current 20*. Then, such a waveform Lc**
When a secondary command value current with
As shown, from the above-mentioned -next command value current Lc **'
Since there is a delay of rd, there is no pressure between ↓C* and ↓C.

By the way, if the fault current component is completely periodic, the configuration shown in FIG. A periodic wave component element (1) consisting of a fundamental wave and harmonic wave whose phase changes slowly and a random non-periodic wave component n(t)
and are included. In such a case, since r (tl is a predictable component, it can be estimated based on past values.

Now, it is assumed that this estimated value γ(tl is expressed by the following equation).

Here, ak (k=z, ko, . . . p m ) is a loading coefficient. Then, the weighting coefficient ak that minimizes the estimation error e of the estimated value r(tl) is determined as follows.

Assume now that the evaluation function has a mean-root error of 11.

This is expressed as the following formula.

In order to obtain ak that minimizes the above-mentioned e J (tl), the following equation (6) may be used.

Namely.

-φr η=O -φγr(koT>=.

Here, + 11 (01eφγr(T), old..., +
1γγ(mT) is the autocorrelation function of r (tl, −
rγ(○) is the autocorrelation function of n(tl. Now, if the above equation (ri) is expressed as a matrix, then the following CS)
It is expressed as the formula.

(za) ′ Find in advance ak that satisfies this (za) formula,
By using this to calculate the equation (4') above, it is possible to estimate the periodic component (tl) with the minimum estimation error.If the optimal periodic component can be estimated in this way, the estimated value By advancing the signal by l sample time and outputting it, the rounding delay in the deadbeat side leg can be reliably compensated for.

What is shown in FIG. 3 is a block diagram of another embodiment of the present invention, which is adapted to perform the above-mentioned estimation operation. Here, it is assumed that the number of stages of the estimator (Q) described later is t stages, and the power supply period T is divided into StX. In this Figure 9, (t2) is the estimation memo I), (i3
) is a third changeover switch, and the estimation memory (
12), which is specified by switching the write address of (tI
I) is a coefficient multiplication element, (l is an adder, and
Each of these means (t2)Ats)Ate) and (15
) constitutes the estimation function unit (λO).

When a command value current LC* of a certain predetermined value is input to the estimation function section (20), via the switch (13),
Data for every l cycle is written for t cycles to a memory element in the estimation memory (/J) corresponding to the time when the power supply cycle T is divided into 1/2. Note that the estimation memo IJ(/2) has one stage and includes t components of memories having addresses 1/co. These data are
It is successively read out at each time corresponding to the write time, weighted by a coefficient multiplication element (/), and added by an adder (tS
) is used to calculate their sum. This adder (13)
The output of is written to the prediction data memory (IOA) via the switch (9). Furthermore, the estimated data γ(tl) calculated based on the formula (4I) is added to this prediction data memory (/7A). ) Via!
The estimated value advanced by the sample time Td is read from the prediction data memory.

In addition, (/6) and (17) in Fig. 1 are a yjC calculator and an adder, respectively, and these are
(It is for processing tl, ie.

In the subtracter (16), estimated value r (tl and command f'
fi, by taking the difference from the flow b c's, n(t
l is detected and added to the secondary command value current l in an adder (17).

Although the above embodiment has been described as being applied to an active waveform improvement device, as is clear from the above description, the present invention has a periodic component and is applied to a predetermined target value. It can be applied to any deadbeat control system whose purpose is to follow the output.

Furthermore, the present invention can be similarly applied to control systems other than deadbeat control systems as long as they have a delay of a predetermined time.

Furthermore, the number of memory divisions, deviations in read and write addresses, and the number of estimation memory stages can be arbitrarily selected as they do not change the operating principle of the device according to the embodiment of the present invention. can do.

〔Effect of the invention〕

As explained above, the present invention is configured to include a time delay recovery means, through which a command value current having one periodicity passes, and therefore, the command value current is output in accordance with the command value current. This has the effect of compensating for the time delay in the output power from the control system.

Further, another invention of the present invention is configured to provide a time delay recovery means including an estimating function section, through which a command value current having a one-period component and a non-periodic component passes,
The periodic component is estimated by the estimation function unit, and based on the estimation result, the time delay of the output current from the control system that is output in response to the command @current is more reliably compensated for.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a sterilization delay compensating device which is an embodiment of the present invention, and FIG. 2 is an example for explaining that the address switching designation in the above embodiment changes over time. Figure, Figure 3 is. FIG. 3 is an operation waveform diagram for explaining the operation of the above embodiment. Figure q shows fttl+1 which is another embodiment of the present invention.
FIG. 3 is a schematic configuration diagram of a Bill delay compensation device, and FIG. 6 is a schematic configuration diagram illustrating that an active waveform improvement device that has been conventionally and generally used is incorporated into a power system.
FIG. 1 is a schematic configuration diagram of a conventional current control circuit device. FIG. 7 is an operational waveform diagram for explaining the operation of the conventional device. (4'l/Φ single-phase power converter, (S)... current detector,
(6) Fist/subtractor, (wa)...voltage detector, (za)...
current controller,

[ri]...First changeover switch, (
20) -.; Memory, (toA) - Memory for fist prediction data. (//)... @ selector switch, (/2)... estimation memory, (13)... selector switch, (1g) - coefficient multiplication element, (/&)... third addition (t6)...subtractor, (17)...adder, (koO)...estimation function unit,
(30), (JOA> . . . time delay recovery means. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (4)

[Claims] (1) In a control delay compensation device for a control system in which an output current is generated with a predetermined time delay following a command value current having periodicity, a time delay is provided to recover the predetermined time delay. A recovery means is provided, the command value current is passed through the time delay recovery means to generate a secondary command value current whose time delay has been recovered, and an output current is generated in accordance with the secondary command value current. control delay compensator. (2) The time delay recovery means includes a first changeover switch for accepting the command value current, a second changeover switch for sending out the secondary command value current, and a second changeover switch for accepting the command value current, and a second changeover switch for receiving the command value current. a memory having a number of memory elements corresponding to the plurality of time points for sequentially storing instantaneous values of the command value current at a plurality of time points divided into equal parts, and a memory element having a number of memory elements corresponding to the plurality of time points; The instantaneous value of the command value current is sequentially written into the corresponding memory element of the memory, and the contents of the memory element of the memory preceding the first changeover switch by a predetermined time are read through the second changeover switch. 2. The control delay compensating device according to claim 1, wherein the control delay compensating device reads data sequentially and uses the read contents as a secondary command value current. (3) In a control delay compensation device for a control system in which an output current is generated with a predetermined time delay following a command value current having a periodic component and a non-periodic component, an estimation function for the periodic component is provided. A time delay recovery means for recovering the predetermined time delay is provided, the periodic component of the command value current being estimated by the estimating function section, and a secondary component having the time delay recovered based on the estimated value. A control delay compensation device characterized in that a command value current is generated and an output current is generated in accordance with this secondary command value current. (4) The time delay recovery means having the estimation function section includes:
a third changeover switch for accepting the command value current; and a third changeover switch for receiving the command value current, and sequentially transmitting the instantaneous values of the command value current at a plurality of points in time, which are obtained by equally dividing one cycle of the command value current, through the third changeover switch. an estimation memory consisting of a plurality of stages of memory having a number of memory elements corresponding to the plurality of time points for storing, a coefficient multiplication element corresponding to each stage of the estimation memory, and an output of the coefficient multiplication element; an estimating function unit consisting of an adder for the purpose of the present invention; and an estimating function unit that sequentially accepts the output from the adder as an estimated value, and sequentially outputs the contents at a time point a predetermined time preceding the acceptance time as a secondary command value current. 4. The control delay compensation device according to claim 3, further comprising a memory for prediction data.