JPS61224336A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS61224336A JPS61224336A JP60065799A JP6579985A JPS61224336A JP S61224336 A JPS61224336 A JP S61224336A JP 60065799 A JP60065799 A JP 60065799A JP 6579985 A JP6579985 A JP 6579985A JP S61224336 A JPS61224336 A JP S61224336A
- Authority
- JP
- Japan
- Prior art keywords
- conductive post
- conductive
- post
- black
- white
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
」11ヒ罎耕1隻1
本発明は基板上に形成した導電ランドに、半導体素子を
含む電子部品ならびに導電ポストを載置し、前記電子部
品と前記導電ポストとを金属細線で電気的に接続した混
成集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention places an electronic component including a semiconductor element and a conductive post on a conductive land formed on a substrate, and connects the electronic component and the conductive post. The present invention relates to a hybrid integrated circuit device electrically connected by thin metal wires.
従来の技術 ・ ′
従来混成集積回路装置にあっては、第14図に示すごと
く、セラミック等を材料とした絶縁基板a上に、所定の
パターンで導電ランドb・・・を形成し、一つの導電ラ
ンドbl上には半導体集積回路素子Cを、また他の導電
ランドb2上には導電ボス)dをそれぞれ半田付けし、
これら半導体集積回路素子0と導電ボス)dとの間に、
ア?レミニウムあるいは金などの金属細線・をボンディ
ングして半導体集積回路素子Cと導電ボス)dとを電気
的に接続して回路を構成していた。Prior Art ・' In a conventional hybrid integrated circuit device, as shown in FIG. 14, conductive lands b are formed in a predetermined pattern on an insulating substrate a made of ceramic or the like, A semiconductor integrated circuit element C is soldered on the conductive land bl, and a conductive boss ) d is soldered on the other conductive land b2,
Between these semiconductor integrated circuit elements 0 and conductive boss) d,
a? A circuit was constructed by electrically connecting the semiconductor integrated circuit element C and the conductive boss (d) by bonding thin metal wires such as reminium or gold.
前記ボンディングの際、直接導電ポストd側の導電ラン
ドb2にボンディングを施さすに、導電ボス)dを介在
させているのは、ボンディング強度上及び大電流動作に
よる熱的な問題の解消等の理由からである。During the above-mentioned bonding, the reason why the conductive boss (d) is interposed when bonding is directly performed to the conductive land b2 on the side of the conductive post d is to improve the bonding strength and to solve thermal problems caused by large current operation. It is from.
ここで、金属細線・を導電ポストd側にボンディングす
る際の基板a上における導電ボス)dの位置の確認は、
工業用TVカメラを用いて行ない、第15図に示す如き
明度に応じ九映像信号を得、第15図の二点鎖線で示す
レベpしで2値化し、第16図に示すごとく白か黒の2
値価映像信号を得る。そして第17図に示すごとく、導
電ボストd上面の白しベIしとその周辺部分(半田付は
部分)の黒しベtしとの境界領域に縦横それぞれ1対の
マーカー!1111 m ma e 11s 6t−重
畳させることにより、前記導電ボストの位置を確認して
いた。Here, when bonding the thin metal wire to the conductive post d side, confirming the position of the conductive boss) d on the substrate a is as follows:
This was carried out using an industrial TV camera, and nine video signals were obtained according to the brightness as shown in Fig. 15, and the signals were binarized at the level p shown by the two-dot chain line in Fig. 15, and the signals were converted into white or black as shown in Fig. 16. 2
Get the value video signal. As shown in FIG. 17, there are a pair of vertical and horizontal markers in the boundary area between the white marking I on the top surface of the conductive post d and the black marking in the surrounding area (the soldering part)! The position of the conductive post was confirmed by superimposing 1111 m ma e 11s 6t.
前記マーカーm* + ma * Is * 7gは相
対位置を保って移動でき、各マーカー!DI s ”!
t ’1 * ’tが第17図に示すごとく白と黒と
の境界領域に位置したとき、各マーカー”i s ”R
e 11 s Itで囲まれた領域の中心が導電ボス)
dの中心であると判定するが、第18図に示すごとく4
つのマーカーが境界領域からずれていると、各マーカー
が白黒レベワレ領域のいずれにあるかを判別して白黒レ
ベ?しの境界領域に各マーカーが位置するように各マー
カt−移動させる。The markers m*+ma*Is*7g can be moved while maintaining their relative positions, and each marker! DIs”!
When t '1 * 't is located in the boundary area between white and black as shown in FIG. 17, each marker "i s "R
The center of the area surrounded by e 11 s It is the conductive boss)
It is determined that it is the center of d, but as shown in Figure 18, 4
If one marker is off the boundary area, determine which of the black and white level areas each marker is in and adjust the black and white level. Each marker is moved by t so that each marker is located in the border area.
発明が解決しようとする問題点
ところが、導電ポストdは一般にア?レミニウム製のも
のが用いられているため上方(よシ光を照射した場合白
の画像となるが、導電ランドb2上の導電ボストdから
食み出した半田1もア?レミニウムに近い反射率を有し
ているため、画像t−2億価像に置換した場合、白レベ
ルとなってあられれ、導電ボストとの境界領域の区別が
明瞭でなくなることがある。Problems to be Solved by the Invention However, is the conductive post d generally a? Since a reminium material is used, the image will be white when illuminated with direct light, but the solder 1 protruding from the conductive post d on the conductive land b2 also has a reflectance close to that of reminium. Therefore, when the image is replaced with a t-2 billion image, the white level may appear, and the boundary area with the conductive post may not be clearly distinguished.
かかる場合には、前記マーカーfill e !Ell
* ’l I ’Rが全て同時に白黒レベrしの境界
領域に位置させることができず、導電ボス)dの位置a
1認は不可能となってしまうものであった。In such a case, the marker fill e! Ell
*'l I'R cannot all be located at the same time in the boundary area between black and white level r, and the position a of conductive boss) d
First approval would have been impossible.
問題点を解決するための手段
しかして、本発明は上記した如き問題点に鑑みなされた
もので、導電ボストの工業用TVカメラによる位置確認
が常に正確に、かつ容易・迅速に行なえるごとくなすも
ので、導電ボストの上面周縁近傍に傾斜面を形成したこ
とを特徴とするものである。Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to make it possible to always accurately, easily and quickly confirm the position of a conductive post using an industrial TV camera. The conductive post is characterized in that an inclined surface is formed near the periphery of the upper surface of the conductive post.
尚、この傾斜面としては断面形状が直線状のものの他、
円弧状のもの等も含むものである。In addition to the slope with a straight cross-sectional shape,
It also includes arc-shaped ones.
実 施 例
以下、本発明の実施例を図面に基づいて説明する。1は
、セラミック等を材料とする絶縁基板であシ、2・・・
は、この絶縁基板1上に所定のパクーンで形成した導電
ランドであシ、これら導電ランド2・・・のうちのある
導電ランド2a上の所定箇所には半導体集積回路素子3
を、また他の導電ランド2b上の所定箇所には導電ボス
ト4をそれぞれ半田付けしである。Embodiments Hereinafter, embodiments of the present invention will be described based on the drawings. 1 is an insulating substrate made of ceramic or the like, 2...
are conductive lands formed in a predetermined pattern on this insulating substrate 1, and a semiconductor integrated circuit element 3 is located at a predetermined location on a certain conductive land 2a among these conductive lands 2.
In addition, conductive bosses 4 are soldered to predetermined locations on other conductive lands 2b.
半導体集積回路素子3上には多数のポンディングパッド
部3a・・・を形成してあり、このポンディングパッド
部3a・・・のりちの1つと前記導電ボスト4とを電気
的に接続すべく、ア?レミニウムあるいは金などの金属
細線5をこれら部材3a、4間にボンディングしである
。6は導電ランド2b上で導電ボスト4から食み出した
半田である。A large number of bonding pad portions 3a are formed on the semiconductor integrated circuit element 3, and in order to electrically connect one of the bonding pad portions 3a to the conductive post 4, a? A thin metal wire 5 made of reminium or gold is bonded between these members 3a and 4. 6 is solder protruding from the conductive post 4 on the conductive land 2b.
しかして本実施例にあっては、導電ボスト4の上面周縁
部分を第3図に示すごとく面取りしている。導電ボスト
4f:かかる構成となすことによシ、上面よシ光を照射
して工業用TVカメラによシ導電ボスト4の位置の確認
を行なう場合、第4図に示すごとく上面平坦面4a1に
あられす白色部分の周縁に、照射光を全く反射してとな
い面取り部分4bのあざやかな黒色部分が形成されるこ
ととなる。すなわち、照射光は面取シ部分4bにあって
は、第5図に示すごとく反射されることとなシ、基板1
の上方に位置せしめたカメk、面取り部分4bよりの反
射光は全く入らないこととなるのである。故に、2値化
レベヤの設定を行なり場合、この面取り部分4bは黒色
レベ?しとなし、半田付は部分6を含むその他の部分を
白色レベIしとなすこともgg6図の二点鎖線で示すよ
うに容易に行なえるのであシ、その結果は第7図のごと
くなり導電ポスト中央部4aの白色部分と、その周辺部
の面取り部分4bの黒色部分とがあざやかなコントラス
トを構成した2値化映像信号が得られるのである。In this embodiment, however, the upper peripheral edge of the conductive post 4 is chamfered as shown in FIG. Conductive post 4f: With this configuration, when the position of the conductive post 4 is to be confirmed using an industrial TV camera by irradiating light from the top surface, the top flat surface 4a1 can be illuminated as shown in FIG. A bright black part of the chamfered part 4b, which reflects no irradiated light, is formed around the periphery of the hail white part. In other words, the irradiated light is reflected at the chamfered portion 4b as shown in FIG.
This means that no reflected light from the chamfered portion 4b and the turtle k positioned above the lens enters. Therefore, when setting the binarization leveler, is this chamfered portion 4b a black level? It is also easy to solder the other parts, including part 6, to the white level I, as shown by the two-dot chain line in Fig. gg6, and the result is as shown in Fig. 7. A binarized video signal is obtained in which the white portion of the central portion 4a of the conductive post and the black portion of the chamfered portion 4b at the periphery constitute a vivid contrast.
そして、従来は導電ボスト4と半田6との境界領域に設
定していたマーカーを、第4図に示すごとく導電ポスト
中央部4mと面取シ部分4bとの境界領域に設定するこ
とにより、あざやかなコントラメに基づく位置確認操作
とすることができ、マーカーml、m2.jl、/2に
よる導電ボスト4の位置の?i!認がきわめて正確に、
かつ、迅速に行なえることとなシ、従って、ボンディン
グ作業のスピードアップが図れるのである。また、前記
導電ポスト4の面取りは特別の工程を付加することなく
容易に行なえるものである。The marker, which was conventionally set at the boundary area between the conductive post 4 and the solder 6, is now set at the boundary area between the conductive post central portion 4m and the chamfered portion 4b, as shown in FIG. The position confirmation operation can be performed based on the contrast, and the markers ml, m2 . The position of the conductive post 4 according to jl, /2? i! recognition is extremely accurate,
Moreover, it can be done quickly, and therefore the bonding work can be speeded up. Moreover, chamfering of the conductive post 4 can be easily performed without adding any special process.
即ち、これら導電ポスト4の製造は、一般に金属平板か
ら打ち抜き作業で行なわれており、この打ち抜き作業の
際の受は部7側を第8図に示すごとく面取りした形状と
しておくことKよシ、打ち抜き工程で同時に面取りを施
すことができるのであり、なんら特別の工程を必要とし
ないのである。That is, these conductive posts 4 are generally manufactured by punching out a flat metal plate, and in this punching process, the receiver should have a chamfered shape on the part 7 side as shown in FIG. 8. Chamfering can be performed at the same time during the punching process, and no special process is required.
ま次、し他の実施例にあっては、第9図に示すごとく、
面取りした外側にさらに平坦部4cを形成した構造とな
してもよく、さらに他の実施例にあっては、第10図に
示すごとく、導電ポスト4の外周縁近傍KV溝4dを形
成した構造となしてもよいものである。In other embodiments, as shown in FIG.
A structure may be adopted in which a flat portion 4c is further formed on the outside of the chamfered surface, and in another embodiment, a structure in which a KV groove 4d is formed near the outer periphery of the conductive post 4 as shown in FIG. It is acceptable to do nothing.
これら実施例の導電ポスト4を用いると、第11図に示
すごとく、黒色帯状部分の外側Kまた白色部分があられ
れることとなるが、この場合マーカーml 、m2 、
I 1 、12の設定位置は、内側白色部分と、黒色
帯状部分との境界領域となしてもよいが、黒色帯状部分
とその外側の白色部分との境界領域となしてもよいもの
である。When the conductive post 4 of these embodiments is used, as shown in FIG. 11, the outer side K of the black band-shaped part and the white part are scoured, but in this case, the markers ml, m2,
The setting positions of I 1 and 12 may be set in the boundary area between the inner white part and the black band-shaped part, or may be set in the boundary area between the black band-shaped part and the outer white part.
また、第9図に示すごとき構造の導電ポスト4を製造す
るには、上記した実施例の場合と同様に、打ち抜きの際
の受は部の型を第12図に示すごとく、面取シ部分の外
側に平坦部を形成した断面形状となしておけばよく、第
10図に示すごとき構造の導電ポストを製造するKは、
413図に示すごとく、打ち抜くパンチ8側に断面形状
が三角形の突起8af:形成しておくことにより、何ら
特別の工程を付加することなく容易に製造できるもので
ある。In addition, in order to manufacture the conductive post 4 having the structure shown in FIG. 9, as in the case of the above-mentioned embodiment, the shape of the receiving part during punching is changed to the shape of the chamfered part as shown in FIG. 12. It is sufficient to have a cross-sectional shape with a flat part formed on the outside of the conductive post.
As shown in FIG. 413, by forming a protrusion 8af with a triangular cross-sectional shape on the side of the punch 8 to be punched, it can be easily manufactured without adding any special process.
発明の効果
以上の説明により明らかなごとく、本発IJK係る混成
集積回路装置くよれば、金属細線t−メンディングする
際の基板上における導電ポストの位置の確認が正確かつ
迅速に行なえるのであ〕、もってポ′ンディング作業の
大いなるスピード化が図れるものである。Effects of the Invention As is clear from the above explanation, according to the hybrid integrated circuit device of the IJK of the present invention, it is possible to accurately and quickly confirm the position of the conductive post on the substrate when performing thin metal wire T-mending. ], thereby greatly speeding up the bonding work.
第1図は本発明の実施例を示す部分平面図、第2図は縦
断面図、第3図は導電ポストの斜視図、第4図は2値化
映像信号を示す説明図、第5図は光の反射状WAt−示
す説明図、wIG図は2値化前の映像信号を示す説明図
、第7図は2値化後の映像信号を示す説明図、第8図は
受は部のl!部を示す縦断面図、第9図は他の実施例の
導電ポストを示す斜視図、第10図は、さらに他の実施
例の導電ポストを示す斜視図、第11図は2値化した映
像信号に重畳したマーカーを示す説明図、第12図は受
は部の縦断面図、第13図はパンチ側の縦断面図、第1
4図は従来例を示す平面図、第15図は2値化前の映像
信号を示す説明図、第16図は2値化した映像信号を示
す説明図、917図及び第18図は映像信号に畳重した
マーカーを示す説明図である。
1・・・基板、2・・・、2a、2b・・・導電ランド
、3・・・半導体集積回路素子、4・・・導電ポスト、
5・−金属細線。
第13図
第17図 第18図Fig. 1 is a partial plan view showing an embodiment of the present invention, Fig. 2 is a vertical sectional view, Fig. 3 is a perspective view of a conductive post, Fig. 4 is an explanatory diagram showing a binary video signal, and Fig. 5 is an explanatory diagram showing the shape of light reflection WAt, wIG diagram is an explanatory diagram showing the video signal before binarization, Fig. 7 is an explanatory diagram showing the video signal after binarization, and Fig. 8 is an explanatory diagram showing the video signal after binarization. l! FIG. 9 is a perspective view showing a conductive post according to another embodiment, FIG. 10 is a perspective view showing a conductive post according to another embodiment, and FIG. 11 is a binarized image. An explanatory diagram showing the marker superimposed on the signal, Fig. 12 is a longitudinal cross-sectional view of the receiving part, Fig. 13 is a longitudinal cross-sectional view of the punch side,
Figure 4 is a plan view showing a conventional example, Figure 15 is an explanatory diagram showing a video signal before binarization, Figure 16 is an explanatory diagram showing a binarized video signal, and Figures 917 and 18 are video signals. FIG. 3 is an explanatory diagram showing markers superimposed on each other. DESCRIPTION OF SYMBOLS 1... Substrate, 2..., 2a, 2b... Conductive land, 3... Semiconductor integrated circuit element, 4... Conductive post,
5.-Thin metal wire. Figure 13 Figure 17 Figure 18
Claims (1)
子部品ならびに導電ポストを載置し、前記電子部品と前
記導電ポストとを金属細線で電気的に接続したものにお
いて、前記導電ポストの上面周縁近傍に傾斜面を形成し
たことを特徴とする混成集積回路装置。An electronic component including a semiconductor element and a conductive post are placed on a conductive land formed on a substrate, and the electronic component and the conductive post are electrically connected by a thin metal wire, in the vicinity of the periphery of the upper surface of the conductive post. A hybrid integrated circuit device characterized in that a sloped surface is formed on the surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60065799A JPS61224336A (en) | 1985-03-28 | 1985-03-28 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60065799A JPS61224336A (en) | 1985-03-28 | 1985-03-28 | Hybrid integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61224336A true JPS61224336A (en) | 1986-10-06 |
Family
ID=13297434
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60065799A Pending JPS61224336A (en) | 1985-03-28 | 1985-03-28 | Hybrid integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61224336A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012129305A (en) * | 2010-12-14 | 2012-07-05 | Denso Corp | Electronic apparatus |
JP2012129306A (en) * | 2010-12-14 | 2012-07-05 | Denso Corp | Electronic apparatus |
-
1985
- 1985-03-28 JP JP60065799A patent/JPS61224336A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012129305A (en) * | 2010-12-14 | 2012-07-05 | Denso Corp | Electronic apparatus |
JP2012129306A (en) * | 2010-12-14 | 2012-07-05 | Denso Corp | Electronic apparatus |
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