JPS61220478A - Manufacture of thin film solar battery - Google Patents
Manufacture of thin film solar batteryInfo
- Publication number
- JPS61220478A JPS61220478A JP60060824A JP6082485A JPS61220478A JP S61220478 A JPS61220478 A JP S61220478A JP 60060824 A JP60060824 A JP 60060824A JP 6082485 A JP6082485 A JP 6082485A JP S61220478 A JPS61220478 A JP S61220478A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode layer
- grooves
- thin film
- film solar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010409 thin film Substances 0.000 title claims description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000003754 machining Methods 0.000 claims abstract description 9
- 238000007650 screen-printing Methods 0.000 claims abstract description 6
- 239000011347 resin Substances 0.000 claims abstract description 3
- 229920005989 resin Polymers 0.000 claims abstract description 3
- 238000000605 extraction Methods 0.000 claims description 12
- 238000007639 printing Methods 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 35
- 239000002184 metal Substances 0.000 abstract description 35
- 239000004020 conductor Substances 0.000 abstract description 3
- 238000000053 physical method Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract 1
- 238000001771 vacuum deposition Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 99
- 239000010408 film Substances 0.000 description 11
- 238000000151 deposition Methods 0.000 description 7
- 229920000139 polyethylene terephthalate Polymers 0.000 description 6
- 239000005020 polyethylene terephthalate Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 229920006254 polymer film Polymers 0.000 description 4
- 238000005096 rolling process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000010935 stainless steel Substances 0.000 description 3
- 229910001220 stainless steel Inorganic materials 0.000 description 3
- CIWBSHSKHKDKBQ-JLAZNSOCSA-N Ascorbic acid Chemical compound OC[C@H](O)[C@H]1OC(=O)C(O)=C1O CIWBSHSKHKDKBQ-JLAZNSOCSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910002065 alloy metal Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- 230000032823 cell division Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000001017 electron-beam sputter deposition Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920006290 polyethylene naphthalate film Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229940071182 stannate Drugs 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022433—Particular geometry of the grid contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
- H01L31/035281—Shape of the body
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
Description
【発明の詳細な説明】
［利用分野Ｊ
本発明は非晶質シリコン層を光起電力層とする薄膜太陽
電池の製造方法に関する。更に詳細には絶縁性基板上に
積層された下部電極Ｉｆ／非晶非晶質シリコ２上／上極
層の下部電極層に電流取り出し用電極を接続させる薄膜
太陽電池の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application J] The present invention relates to a method for manufacturing a thin film solar cell using an amorphous silicon layer as a photovoltaic layer. More specifically, the present invention relates to a method of manufacturing a thin film solar cell in which a current extraction electrode is connected to a lower electrode layer of the lower electrode If/amorphous silicon 2/upper electrode layer laminated on an insulating substrate.
［従来技術］
非晶質シリコン半導体膜はシランガス等のグロー放電分
解法によって低い基板温度で、広い面積に均一に堆積で
き、基板もガラス、高分子フィルム、セラミック板、金
属フォイル等の各種基板が選択できる為、太陽電池用半
導体膜として広く研究されている。[Prior art] Amorphous silicon semiconductor films can be deposited uniformly over a wide area at low substrate temperatures by glow discharge decomposition using silane gas, etc. Various substrates such as glass, polymer films, ceramic plates, and metal foils can be used. Because it can be selected, it is widely studied as a semiconductor film for solar cells.
非晶質シリコン太陽電池の基本構造としては上記各種基
板上に設けられた金属電穫層／非晶質シリコン半導体層
／透明電極層の積層構造が用いられている。The basic structure of an amorphous silicon solar cell is a laminated structure of a metal electroplating layer/amorphous silicon semiconductor layer/transparent electrode layer provided on the various substrates mentioned above.
非晶質シリコン層堆積の特徴を生かし特開昭５９−３４
６６８号公報に開示されたロールツーロール方式やＪａ
ｐａｎ Ｊｏａｒｎａｌ ｏｆ ＡＥ）Ｄｌｉｅ
ｄ Ｐｈｙｓｉｃｓ誌２１巻３号４１３ページ（１９
８２）に掲載されている３室分離形成法などを用いて金
属電極層を設けた大面積の長尺基板上に非晶質シリコン
層を堆積することは容易である。Utilizing the characteristics of amorphous silicon layer deposition, JP-A-59-34
The roll-to-roll method disclosed in Publication No. 668 and Ja
pan Journal of AE) Dlie
d Physics magazine, Volume 21, No. 3, Page 413 (19
It is easy to deposit an amorphous silicon layer on a large-area elongated substrate provided with a metal electrode layer using the three-chamber separation formation method described in 82).
又、もう一方の電流取り出し電極の透明電極層を大面積
に設ける事も容易である。しかしながら太陽電池として
上記積層体を働かす為には金属電極層と透明電極層とに
リード端子を取り付ける事が必要である。さらに、実用
化に必要な数十Ｖ以上の出力電圧を得る為には、上記大
面積基板上に設けた太陽電池をレーザスクライブ法等で
分割しその後隣接し合う金属電極層と透明電極層とを直
列接続する事が必要である。かかる場合最下層である金
属電極層を露出させる事が必須の要件となる。この方法
として
■ 非晶質シリコン層堆積時に金属マスクを用いる方法
、
■ 非晶質シリコン層堆積後、湿式あるいは乾式のエツ
チング法を用いシリコン層を除去する方法、
■ 非晶質シリコン層堆積後、レーザ照射によってシリ
コン層のみを選択的に溶融、蒸発させて除去する方法
などが用いられてきた。Further, it is also easy to provide the transparent electrode layer of the other current extraction electrode over a large area. However, in order for the above-mentioned laminate to function as a solar cell, it is necessary to attach lead terminals to the metal electrode layer and the transparent electrode layer. Furthermore, in order to obtain an output voltage of several tens of volts or more, which is necessary for practical use, the solar cell provided on the large-area substrate is divided by a laser scribing method, etc., and then the adjacent metal electrode layer and transparent electrode layer are separated. It is necessary to connect them in series. In such a case, it is essential to expose the metal electrode layer, which is the lowest layer. These methods include: ■ Using a metal mask during deposition of the amorphous silicon layer; ■ After depositing the amorphous silicon layer, removing the silicon layer using a wet or dry etching method; ■ After depositing the amorphous silicon layer, A method has been used in which only the silicon layer is selectively melted and evaporated by laser irradiation to remove it.
これらの方法の中で、■の方式は長尺、大面積のロール
ツーロール方式に適さないばかりか３室分離形成法にお
いても、非晶質シリコン堆積時の加熱過程において、基
板とマスクの熱膨張率の違いによる密着性の悪化の為、
非晶質シリコン成分の回り込みが生じ良好なパターンが
得られず且つ、電気的に良好な金属層表面を露出させる
ことがむつかしい。Among these methods, method (2) is not only unsuitable for long, large-area roll-to-roll methods, but also in the three-chamber separation method, the heating process during amorphous silicon deposition causes heat loss between the substrate and mask. Due to poor adhesion due to the difference in expansion rate,
The amorphous silicon component wraps around, making it impossible to obtain a good pattern, and it is difficult to expose the electrically good surface of the metal layer.
■の方式はレジスト塗付とエツチングの組み合わせによ
って可能であるが、レジスト塗付、露光。Method (2) is possible by combining resist coating and etching, but resist coating and exposure.
洗浄、エツチング等の多数の工程が必要であり、安価に
大量に太陽電池を製造するには適さない。It requires many steps such as cleaning and etching, and is not suitable for producing large quantities of solar cells at low cost.
又■の方式においてはシリコン層溶融に必要な高温発生
の為、高融点金属を用いた金属電極層においても損傷が
生じ電気的に良好な金属層表面を露出させる事が出来な
いばかりか、Ａｌｌのごとき低融点金属ではシリコン層
のみを選択的に除去する事も出来ないのが実状である。In addition, in method (2), due to the high temperature required to melt the silicon layer, the metal electrode layer made of a high-melting point metal is also damaged, making it impossible to expose the electrically good surface of the metal layer. The reality is that it is not possible to selectively remove only the silicon layer with low melting point metals such as.
［発明の目的］
・本発明は、上記現状に鑑みなされたもので、大面積基
板上でのリード端子取り出し又は、分離されたセルの直
列接続を可能にする為の電流取り出し用電極を下部の電
極面に簡単に接続できるｓｍ太陽電池の製造方法を提供
することを目的とするものである。[Object of the invention] - The present invention has been made in view of the above-mentioned current situation, and it is possible to take out lead terminals on a large-area board or connect separated cells in series by connecting current extraction electrodes to the lower part. The object of the present invention is to provide a method for manufacturing an SM solar cell that can be easily connected to an electrode surface.
［発明の構成及び作用］ 上述の目的は以下の本発明により達成される。[Structure and operation of the invention] The above objects are achieved by the invention as follows.
すなわち、本発明は、電気絶縁性の基体上に下部電極層
、非晶質シリコン層からなる光起電力層。That is, the present invention provides a photovoltaic layer comprising a lower electrode layer and an amorphous silicon layer on an electrically insulating substrate.
上部電極層を順次積層したｉｉｌ！太陽電池の下部電極
層へ上部から電流取り出し用電極を接続するに際し、機
械加工により上部から下部電極層に達する溝若しくは穴
を設け、該溝若しくは穴を介して下部電極層に電流取り
出し用電極を電気接続することを特徴とする薄膜太陽電
池の製造方法である。Iil! upper electrode layers are sequentially laminated! When connecting the current extraction electrode to the lower electrode layer of the solar cell from the upper part, a groove or hole is formed by machining that reaches the lower electrode layer from the upper part, and the current extraction electrode is connected to the lower electrode layer through the groove or hole. This is a method for manufacturing a thin film solar cell characterized by electrical connection.
上述の本発明は、機械加工により、下部電極層上の光起
電力層、上部電極層を穿設して下部電極層に達する溝あ
るいは穴を設け、該溝あるいは穴に導電性材を埋め込み
電流取り出し用電極とするものであり、前述した特定の
パターン化等が不要で、且つ簡単に機械加工と、スクリ
ーン印刷等の組合せで所望の電気接続が形成でき、非常
に生産性が良く且つ歩留りも良い製造プロセスを実現す
るものである。In the present invention described above, a photovoltaic layer on a lower electrode layer and an upper electrode layer are formed by machining to provide a groove or a hole reaching the lower electrode layer, and a conductive material is filled in the groove or hole to allow current flow. It is used as an electrode for extraction, and does not require the above-mentioned specific patterning, and the desired electrical connection can be easily formed by a combination of machining and screen printing, resulting in very high productivity and low yield. It realizes a good manufacturing process.
以下本発明の詳細を具体的に説明する。The details of the present invention will be specifically explained below.
第１図は、本発明の対象となる薄膜太陽電池の一例の側
断面図である。FIG. 1 is a side sectional view of an example of a thin film solar cell to which the present invention is applied.
図において、■は電気絶縁性の基板、■は下部電極層の
金Ｒ電極層、■は起電力層の非晶質シリコン層、■は上
部電極層の透明電極層であり、周知の非晶質シリコン薄
膜太陽電池が示しである。In the figure, ■ is an electrically insulating substrate, ■ is a gold R electrode layer as a lower electrode layer, ■ is an amorphous silicon layer as an electromotive force layer, and ■ is a transparent electrode layer as an upper electrode layer. A high quality silicon thin film solar cell is an example.
なお、本発明は、図示のものに限定されず、下部電極層
を透明電極層とし上部電極層を金属電極層としたもの、
あるいは上下の両電極層を透明電極層としたものにも適
用できる。Note that the present invention is not limited to what is shown in the drawings, but includes a structure in which the lower electrode layer is a transparent electrode layer and the upper electrode layer is a metal electrode layer,
Alternatively, it can also be applied to a structure in which both the upper and lower electrode layers are transparent electrode layers.
ところで、本発明の電気絶縁性の基板■としては電気絶
縁材からなる全ての基板が適用でき、具体的には高分子
フィルム、セラミック板、あるいは絶縁性層を表面に設
けた金属フォイル等が使用出来るが、好ましくはロール
ツーロール法によって構成層を順次長尺の走行する基板
上に堆積出来、大量生産に適した高分子フィルムが使用
される。By the way, as the electrically insulating substrate (2) of the present invention, any substrate made of electrically insulating material can be used, and specifically, a polymer film, a ceramic plate, or a metal foil with an insulating layer provided on the surface can be used. However, preferably a polymeric film is used which allows the constituent layers to be deposited one after another on a long running substrate by a roll-to-roll method and is suitable for mass production.
高分子フィルムとしては、非晶質シリコン堆積に必要な
耐熱性を有する高分子フィルムなｄどれでも良いが、好
ましくは機械的特性面の優れたポリエチレンテレフタレ
ート（ＰＥＴ）フィルム、ポリエチレンナフタレートフ
ィルム、ポリイミドフィルムなどが用いられる。The polymer film may be any polymer film that has the heat resistance necessary for amorphous silicon deposition, but preferably polyethylene terephthalate (PET) film, polyethylene naphthalate film, or polyimide film, which has excellent mechanical properties. Film etc. are used.
下部電極層若しくは上部電極層として用いられる金属電
極層■としては、ＡｆＬ、ＡＱ 、Ｔｉ 、Ｗ。The metal electrode layer (2) used as the lower electrode layer or the upper electrode layer includes AfL, AQ, Ti, and W.
Ｐｔ、Ｎｉ、Ｇｏ、 Ｃｒ、ニクロム、ステンレスなど
の単体金属９合金金属の単層膜、あるいは多層膜が用い
られるが好ましくは／１．Ａｌ）を主成分とした電極層
が用いられる。又、これらの金属電極層は、その電気抵
抗の低下及び機械的強度の観点から０．３μ雇以上の厚
みが望ましい。A single layer film or a multilayer film of single metal 9 alloy metals such as Pt, Ni, Go, Cr, nichrome, and stainless steel is used, but preferably /1. An electrode layer containing Al) as a main component is used. Further, these metal electrode layers preferably have a thickness of 0.3 μm or more from the viewpoint of reducing electrical resistance and mechanical strength.
非晶質シリコン層■は、光起電力能を有するものであれ
ば特に限定されないが、具体的には既に公知のシランガ
ス、ジシランガス等のグロー放電分解を用いたプラズマ
ＣｖＤ法を用いて形成されたｐｉｎ形の積層光起電力層
等がある。なお、かかる非晶質シリコン光起電力層とし
ては、ｐｉｎ ／ ｐｉｎ、 ｐｉｎ ／Ｉ）ｉｎ ／
ｐｉｎ等の多層タンデム構造はもちろんのこと非晶質シ
リコンゲルマニウム、非晶質シリコンカーバイトなどの
す０−バンドギャップあるいはワイドバンドギャップ半
導体層を適時用いる事も出来る。The amorphous silicon layer (2) is not particularly limited as long as it has photovoltaic ability, but specifically, it is formed using a plasma CVD method using glow discharge decomposition of a known silane gas, disilane gas, etc. There are pin-shaped laminated photovoltaic layers and the like. In addition, as such an amorphous silicon photovoltaic layer, pin/pin, pin/I)in/
Not only a multilayer tandem structure such as PIN, but also a 0-bandgap or wide bandgap semiconductor layer such as amorphous silicon germanium or amorphous silicon carbide can be used as appropriate.
上部電極層又は下部電極層に用いられる透明導電層■も
特に限定されず、公知のものが全て適用できる。例えば
酸化インジューム、酸化スズ、スズ酸カドニウム等の酸
化物導電体を電子ビーム蒸着あるいはスパッタリング法
によって堆積したもの等が適用できる。更に透明導電性
接着層を介して、前述の金属電極層／非晶質シリコン層
の積層体表面に透明導電膜を接合させた薄膜太陽電池に
も適用できる。The transparent conductive layer (2) used for the upper electrode layer or the lower electrode layer is also not particularly limited, and all known ones can be used. For example, an oxide conductor such as indium oxide, tin oxide, or cadmium stannate deposited by electron beam evaporation or sputtering can be used. Furthermore, it can also be applied to a thin film solar cell in which a transparent conductive film is bonded to the surface of the aforementioned metal electrode layer/amorphous silicon layer laminate via a transparent conductive adhesive layer.
機械加工としては、溝若しくは穴が形成できるものであ
れば良いが、先の尖った加工部材を用いるものが好まし
い。かかる加工部材としては、ナイフや針状体等が利用
できる。そして例えばこれら加工部材を非晶質リンコン
層上において機械的に移動ないし殴打させる事によって
下部電極層に達する溝あるいは穴を形成する。この溝又
は穴は電気接続の低抵抗化及び高信頼化面から所定部所
の全面に亘って複数個形成することが好ましい。As for machining, any method that can form grooves or holes may be used, but it is preferable to use a sharp-edged member. As such a processing member, a knife, a needle-like object, etc. can be used. For example, a groove or a hole reaching the lower electrode layer is formed by mechanically moving or striking these processed members on the amorphous phosphor layer. It is preferable to form a plurality of these grooves or holes over the entire surface of a predetermined location in order to reduce resistance and increase reliability of electrical connection.
加工の際の加工部材の接圧は非晶質シリコン層を除去す
るのに十分でかつ電気絶縁性の基体に到達しない程度が
好ましく、そのつど最適値を選択して行なうことが望ま
しい。The contact pressure of the workpiece during processing is preferably sufficient to remove the amorphous silicon layer but does not reach the electrically insulating substrate, and it is desirable to select the optimum value each time.
例えば、ナイフのごとき先の尖った加工部材で下部金属
電極層■上に非晶質シリコン層■を積層後加工する場合
は、加工部材を非晶質シリコン層■上で機械的に所定接
圧下で繰り返し移動させると、第２図（Ａ）のごとく、
複数条のＶ字状溝■が形成できその溝側面で下部金属電
極層■を露出させることができる。次に、該露出金属層
部位からの電流取り出し用電極■は、このｖ字状溝■上
に真空蒸着法、スパッタリング法の物理的方法によって
所定の金属を堆積したりあるいは導電性樹脂層をスクリ
ーン印刷法等で設ける事によって第２図（８）のごとく
、下部電極■に溝■を介して電気接続した状態で形成で
きる。なかでも、導電性ｍＷｉ層をスクリーン印刷法で
設ける方法は、該工程が大気雰囲気で、しかもマスクレ
スで行なわれるため本発明主旨の点からも好ましい。な
お、溝又は穴の形状は前述のＶ字に限定されないがこれ
ら製造法で良好な電気接続を得るためには、上述の溝又
は穴は、断面がｖ字状のものが好ましい。For example, when processing the amorphous silicon layer ■ on the lower metal electrode layer ■ using a sharp workpiece such as a knife, the workpiece is mechanically placed on the amorphous silicon layer ■ under a predetermined contact pressure. If you move it repeatedly, as shown in Figure 2 (A),
A plurality of V-shaped grooves (2) can be formed, and the lower metal electrode layer (2) can be exposed on the side surfaces of the grooves. Next, the electrode (2) for taking out current from the exposed metal layer portion is formed by depositing a predetermined metal on this V-shaped groove (2) by a physical method such as vacuum evaporation or sputtering, or by screening a conductive resin layer. By providing it by a printing method or the like, it can be formed in a state where it is electrically connected to the lower electrode (2) via the groove (2) as shown in FIG. 2 (8). Among these, the method of providing the conductive mWi layer by screen printing is preferable from the point of view of the gist of the present invention, since the process is carried out in an air atmosphere without a mask. Note that the shape of the groove or hole is not limited to the above-mentioned V-shape, but in order to obtain a good electrical connection using these manufacturing methods, the above-mentioned groove or hole preferably has a V-shape in cross section.
又その開口部の幅は電流取り出し用電極の形成法に応じ
て適宜選定される
下部金属電極層／非晶質シリコン層／透明電極層堆積後
の場合も同じ方法で下部金属電極層よりの電流取出し電
極を堆積できる。The width of the opening is appropriately selected depending on the method of forming the current extraction electrode.The same method can be used to control the current flow from the lower metal electrode layer after the lower metal electrode layer/amorphous silicon layer/transparent electrode layer is deposited. Extraction electrodes can be deposited.
［実施例］
基板■として１００μｍ厚のポリエチレンテレフタレー
トフィルム（ＰＥＴ）を用いた。まず該フィルム基板■
をマグネトロンスパッタ装置に装着し、ｉｏ’ ｔｏｒ
ｒ台のＡｒ雰囲気中でアルミニウム層（ＡＵ） ０．
４ｕＴｒＬ、及びステンレス層（ＳＳ）１００人を連続
して順次堆積し、金属電極層■を長尺フィルム基板１上
に設けた。さらにこのＰＥＴ／Ａ！／８８堆積体上に非
晶質シリコンのｐｉｎ型の光起電力ｌ１Ｉ３を特開昭５
９−３４６６８号公報に開示されている０−ルツーロー
ル方式によって長尺で大面積に連続的に堆積した。同一
基板上で３個のセルが直列接続された太陽電池モジュー
ルを形成する為に大面積の上記ＰＥＴ／Ａｆｉ／ＳＳ／
非晶賀シリコン層上第３図に黒帯Ｂで示すような分割パ
ターンの電気絶縁層をスクリーン印刷し、その後第３図
の斜線部分Ｓに金属マスクを設は電子ビーム蒸着で酸化
インジュームの透明導電層■を堆積した。さらに黒帯Ｂ
上をＹＡＧレーザーで照射するレーザースクライプ法に
よって前記分割パターンに沿う１個当たり２４．５ｍの
面積を有する３個のセルＣに分割加工した。[Example] A 100 μm thick polyethylene terephthalate film (PET) was used as the substrate (2). First, the film substrate■
attached to the magnetron sputtering device, and
Aluminum layer (AU) 0.
4uTrL and 100 stainless steel layers (SS) were successively deposited one after another, and a metal electrode layer (2) was provided on the long film substrate 1. Furthermore, this PET/A! /88 A pin-type photovoltaic force l1I3 of amorphous silicon was deposited on the deposited body in Japanese Patent Laid-Open No. 5
It was continuously deposited in a long length over a large area by the 0-rutu roll method disclosed in Japanese Patent No. 9-34668. In order to form a solar cell module in which three cells are connected in series on the same substrate, the above PET/Afi/SS/
On the amorphous silicon layer, an electrical insulating layer with a divided pattern as shown by the black stripes B in Figure 3 is screen printed, and then a metal mask is placed in the shaded area S in Figure 3, and indium oxide is removed by electron beam evaporation. A transparent conductive layer ■ was deposited. Furthermore, black belt B
It was divided into three cells C each having an area of 24.5 m along the division pattern by a laser scribing method in which the upper part was irradiated with a YAG laser.
この分割された３個のセルＣを直列接続する為、各セル
の所定部所すなわち第３図の斜線部Ｓの金属電極層■を
露出させる為ステンレス製のナイフを用い、斜線部分Ｂ
のセルＣの上面に対して垂直に保持した状態で所定接圧
で押圧しつつ繰返し水平方向に移動させることにより、
金属電極層／非晶質シリコン層を除去してその全面に亘
り数１００μ肌幅のｖ字状溝を均一密度で形成し、その
後電流取り出し用電極として第３図に示すパターンＰの
銀ペースト層をスクリーン印刷により透明導電層上及び
露出した金属電極層上に設け、セル０間接続と収集電極
とを兼用させた。In order to connect these three divided cells C in series, a stainless steel knife was used to expose the metal electrode layer 2 at a predetermined portion of each cell, that is, the shaded area S in FIG.
By repeatedly moving the cell C in the horizontal direction while pressing it with a predetermined contact pressure while holding it perpendicularly to the top surface of the cell C,
The metal electrode layer/amorphous silicon layer is removed and V-shaped grooves with a skin width of several hundred micrometers are formed at a uniform density over the entire surface, and then a silver paste layer of pattern P shown in FIG. 3 is used as a current extraction electrode. was provided on the transparent conductive layer and the exposed metal electrode layer by screen printing to serve both as a cell 0 connection and as a collection electrode.
この３直列モジュールの性能をＡＭｌ （１００ｍＷ／
ｄ）ソーラシミュレータ光下で測定した結果を表１に示
した。The performance of this 3-series module is AMl (100mW/
d) Table 1 shows the results measured under solar simulator light.
比較の為、金属電極層、非晶質シリコン層、透明電極層
をそれぞれ金属マスクを用いて形成した同じ構成の３直
列モジュールのＡＭ１ソーラ、シミュレータ光下の測定
結果を示した。For comparison, the measurement results under AM1 solar and simulator light of a three-series module with the same configuration in which a metal electrode layer, an amorphous silicon layer, and a transparent electrode layer were each formed using a metal mask are shown.
表１の結果は、両者には有意差が見られず本発明の製造
方法によって、低抵抗の金属電極−透明導電層上の直列
接続が得られる事を示している。、The results in Table 1 show that there is no significant difference between the two, indicating that the manufacturing method of the present invention provides a series connection between a metal electrode and a transparent conductive layer with low resistance. ,
第１図は本発明の対象の薄膜太陽電池の一例の側断面図
、第２図（Ａ）、（Ｂ）は本発明を説明するための各ス
テップでの薄膜太陽電池の側断面図、第３図は実施例の
セルの分割パターンを示す平面図、第４図は実施例の電
流取り出し電極のパターンを示す平面図である。
■二基 板 ■：金属電極層
■：非晶質シリコン層 ■：透明電極層■：溝 Ｃ
：セ ル
すＺ１図FIG. 1 is a side sectional view of an example of a thin film solar cell to which the present invention is applied; FIGS. 2(A) and 2(B) are side sectional views of the thin film solar cell at each step for explaining the present invention; FIG. 3 is a plan view showing the cell division pattern of the example, and FIG. 4 is a plan view showing the pattern of the current extraction electrode of the example. ■Two substrates ■: Metal electrode layer ■: Amorphous silicon layer ■: Transparent electrode layer ■: Groove C
: Cell Z1 diagram
Claims (1)
からなる光起電力層、上部電極層を順次積層した薄膜太
陽電池の下部電極層へ上部から電流取り出し用電極を接
続するに際し、機械加工により上部から下部電極層に達
する溝若しくは穴を設け、該溝若しくは穴を介して下部
電極層に電流取り出し電極を電気接続することを特徴と
する薄膜太陽電池の製造方法。 ２、先の尖った加工部材で機械加工し、Ｖ字状断面の溝
又は穴を形成する特許請求の範囲第１項記載の薄膜太陽
電池の製造方法。 ３、前記溝若しくは穴を所定部所の全面に亘って複数個
配設した特許請求の範囲第１項若しくは第２項記載の薄
膜太陽電池の製造方法。 ４、前記電流取り出し用電極をスクリーン印刷法により
導電性樹脂を印刷して設ける特許請求の範囲第１項、第
２項若しくは第３項記載の薄膜太陽電池の製造方法。[Claims] 1. For extracting current from above to the lower electrode layer of a thin film solar cell in which a lower electrode layer, a photovoltaic layer consisting of an amorphous silicon layer, and an upper electrode layer are sequentially laminated on an electrically insulating substrate. Manufacture of a thin film solar cell characterized in that when connecting electrodes, a groove or hole is provided by machining that reaches from the upper electrode layer to the lower electrode layer, and a current extraction electrode is electrically connected to the lower electrode layer through the groove or hole. Method. 2. The method for manufacturing a thin film solar cell according to claim 1, which comprises machining with a pointed processing member to form a groove or hole with a V-shaped cross section. 3. The method for manufacturing a thin film solar cell according to claim 1 or 2, wherein a plurality of the grooves or holes are provided over the entire surface of a predetermined portion. 4. The method for manufacturing a thin film solar cell according to claim 1, 2 or 3, wherein the current extraction electrode is provided by printing a conductive resin using a screen printing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60060824A JPH0620149B2 (en) | 1985-03-27 | 1985-03-27 | Method of manufacturing thin film solar cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60060824A JPH0620149B2 (en) | 1985-03-27 | 1985-03-27 | Method of manufacturing thin film solar cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61220478A true JPS61220478A (en) | 1986-09-30 |
| JPH0620149B2 JPH0620149B2 (en) | 1994-03-16 |
Family
ID=13153487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60060824A Expired - Fee Related JPH0620149B2 (en) | 1985-03-27 | 1985-03-27 | Method of manufacturing thin film solar cell |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0620149B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5753986A (en) * | 1980-07-25 | 1982-03-31 | Eastman Kodak Co |
-
1985
- 1985-03-27 JP JP60060824A patent/JPH0620149B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5753986A (en) * | 1980-07-25 | 1982-03-31 | Eastman Kodak Co |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0620149B2 (en) | 1994-03-16 |
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