JPS61218246A - Multiplex transmitter - Google Patents

Abstract

PURPOSE:To transmit a data in high speed without causing high frequency noise by obtaining an intermediate correcting synchronous signal in a time slot of an address clock signal and transmitting data of plural bits in the NRZ code while synchronizing the data with the signal by each quantity split into prescribed quantity. CONSTITUTION:A signal S11 becomes an intermediate correction synchronous signal synchronous with the intermediate position at a period T of each code of an address clock signal S4 at an address recovery circuit 13. Parity check is applied in a receiver 11 via a parity check circuit 25 based on a reception signal L8 outputted from an oscillation synchronizing circuit 17R, the serial data of the NRZ code received via a serial/parallel exchange circuit 27, a reception data is latched by an output data latch circuit 29 and given/received to/ from a reception processing circuit (not shown) via a data output line OUT, the reception processing circuit applies a prescribed processing to light a front light of an automobile, for example, or activate a prescribed actuator.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplex transmission device that can efficiently transmit and receive data of multiple bits between a large number of transmitters and receivers.

[Description of Prior Art] As an example of a conventional multiplex transmission device, for example,
There is one as shown in Japanese Patent No.-13367.

The multiplex transmission device disclosed in Japanese Patent Publication No. 52-13367 includes time series code generating means for generating M-sequence time series codes, demodulating the time series codes generated by the time series code generating means, and demodulating, for example, It is mainly composed of a transmitting/receiving means that can transmit/receive one bit of data once when a 3-bit code string pattern matches a 3-bit address assigned to itself, and each transmitting/receiving means can transmit and receive one address. Based on a match, one bit of data can be sent and received only once.

However, in general, in a multiplex transmission device, there are cases in which a parity bit is added in addition to the on/off information of the switch information, or in addition to the on/off information, it is desired to transmit information such as strength or timing as multiple bits of data. . In such a case, if such data is to be transmitted using the multiplex transmission device, it must be transmitted in such a manner that address matching is performed multiple times, and multiple addresses are required to transmit one data. There is a problem in that matching must be performed and a lot of transmission time is required.

As an improvement on the above-mentioned problem, there is a method that allows multiple bits of data to be transmitted at once using a width modulation method based on a single address match.

Therefore, in this multiplex transmission device, for example, 512Hz
For example, 4 bits of data can be transmitted at once within the reference time of the synchronization signal, which means that data can be transmitted at a higher speed.Furthermore, it is also possible to include a so-called parity bit in the 4 bits, making it possible to It can also improve reliability.

However, in recent years, with the aim of further expanding the scope of application of multiplex transmission equipment, there has been a desire for a multiplex transmission equipment that can multiplex transmit multiple bits of data at higher speed. When attempting to transmit these data in the & position, there is a problem in that since the data is transmitted using the width modulation method, the transmission frequency at the time of data transmission becomes high and high frequency noise is generated.

On the other hand, as a measure to prevent high frequency noise, the NRZ code (
Non Return to Zero Co
A transmission method using the NRZ method is considered, but if this NRZ method is to be adopted, extremely high precision clocks are required for both the transmitter and receiver, and this is especially true for multiplex transmission equipment equipped with a large number of transmitters and receivers. However, even if a high-precision clock is prepared, the error will increase as the number of data bits increases, so it is impossible to ignore the price. In data transmission of multiple bits, there is a problem in that it is difficult to prevent synchronization errors during data transmission.

[Objective of the Invention] This invention improves the above-mentioned problems and enables multi-bit data to be transmitted at high speed using an NRZ code without generating high-frequency noise from the transmission line, and does not necessarily require a high-precision clock. The purpose of the present invention is to provide a multiplex transmission device without

[Summary of the Invention] In order to achieve the above object, the present invention provides a time series code that generates a predetermined series of time series codes by providing a multiplex transmission device with a plurality of synchronization signals for data transmission and reception within a time slot of a unit code. a generation means, a time series code transmission line for transmitting the time series code, a data transmission line installed in parallel with the time series code transmission line, and a time series code of the predetermined series connected to the time series code transmission line. code string pattern detection means for detecting a current code string pattern of predetermined bits from a code string pattern; pattern/address matching means for matching the detected code string pattern with an address assigned to itself; data transmission/reception signal output means for outputting a data transmission/reception signal for transmitting/receiving predetermined bits of data in the NRZ code for each of the plurality of data transmission/reception synchronization signals when the addresses assigned to the data transmission and reception synchronization signals match. and a data transmitting/receiving means connected to the data transmission path and transmitting/receiving a plurality of bits of data to/from the data transmission path based on the data transmission/reception signal, The data is divided into predetermined bits within a range that is not affected by errors, and data transmission is performed multiple times within the time slot using the NRZ code in synchronization with one or more synchronization signals.

[Description of Examples] Hereinafter, this invention will be described in detail with reference to two Examples.

First, FIG. 1, which is commonly used in the first and second embodiments, will be explained.

The multiplex transmission device 1 has an address clock line (time series code transmission line) 3 and a data line (data transmission line) 5.
An address clock generator (time series code generating means) 7 is connected to the address clock line 3. Transmitter 9 is connected to address clock line 3 via line L1 and connected to line L2.
It is connected to the data line 5 via. Similarly receiver 1
1 is connected to the address clock line 3 via the line L3 and to the data line 5 via the line L4.

Although only one transmitter/receiver is shown in the figure, in reality, an appropriate number of transmitters/receivers are connected and predetermined addresses are assigned to these transmitters/receivers. Predetermined data transmission is performed between machines.

The transmitter 9 is connected to the address clock line 3 via the line L1.
Address reproducing circuit (code string pattern detection means) connected to 13. Address matching circuit (pattern/code string matching means) 15. connected to the circuit 13 via line L5. 17 oscillation/synchronization circuits (data transmission/reception signal forming means) connected to the circuit 15 and the address reproduction circuit 13 via lines L6 and L7, and the circuit 17T and line L.
8 and is connected to the data line 5 through the circuit 11m.
Parity pit generating means 19.2 connected via parity pit generating means 19. The line L8 and the parity pit generation circuit 19 and the line 1
Parallel-serial conversion circuit 2 connected via 1L9
1. The input buffer circuit 23 is connected to the circuit 21 via a line L10. Here, a parity pit generation circuit 19, a parallel-serial conversion circuit 21. The input cover sofa circuit 23 together forms a transmitting means.

The reception 111 is the transmission! Address regeneration circuit 13 similar to I9, address matching circuit 15, and oscillation/synchronization circuit 1
7R, and a parity check circuit 25.
In addition, receiving means formed by a serial-to-parallel conversion circuit 27 and an output data latch circuit 29 are added. The serial-parallel conversion circuit 27 and the output data latch circuit 29 are connected via a line 111, and the parity check circuit 25 and the output data latch circuit 29 are connected via a line L12.

Note that the arrow IN shown at the bottom of the figure of the transmitter 9 indicates a data input line from an encoder circuit (not shown), and the arrow 0LJT shown at the bottom of the figure of the receiver 11 indicates an output line of transmission data. There is.

The data flow in the multiplex transmission apparatus having the above configuration will be explained in detail later in the first embodiment.

(First example) FIG. 2 shows a circuit diagram of the address clock generator 7.

FIG. 3 is a time chart showing signal states of each part.

The address clock generator 7 includes a reference clock generator 31 that generates a reference clock signal S3 with a predetermined period T as shown in FIG. 3(C), and a clock signal S from the generator 31.
3, the M-sequence signal generator 33.3 generates an M-sequence code signal S1 as shown in FIG. 3(a). Similarly, it has a pulse generator 35 which receives the clock signal $3 and generates a pulse signal S2 having a pulse width of t as shown in FIG. 3(b). As described above, the reference clock signal S3 is highly synchronized and has a redundancy of 50%. The M-sequence signal generator 33 has a shift register, an exclusive OR gate, etc. therein, and generates a signal based on the clock signal S3.
．． 0 code is a 5th order M-sequence code, and this is the code string signal S.
1 and output in chronological order. The pulse generator 35 has a rising synchronization one-shot circuit having a time width Δt inside thereof, and generates a pulse signal S2 having a pulse width Δt9 and a cycle T/2 in synchronization with the rising timing of the clock signal.

The address clock generator 7 has a switching gate circuit 37.

The switching gate circuit 37 includes an inverter 39 for inverting the M-sequence code string signal @S1;
an AND gate 41 to which the inverted signal and the pulse signal S2 are input; and an AND gate 43 to which the reference clock signal S3 and the code signal S1 are input. and,
The output of the AND gate 43 and the OR gate 45 input the output of the AND gate 41, and the input signals 4s1, 82 . The S3 signal is switched at a predetermined timing, and the output address clock signal S4 is sent to the address clock line 3.

The address clock signal S4 is composed of a pulse signal at sign O formed by the AND gate 41 and a pulse signal at the symbol O formed by the AND gate 41.
3 and the reference clock signal of code 1 formed by code 1 are superimposed by an OR gate 45, resulting in a signal in which a signal for obtaining a synchronization signal for intermediate correction, which will be described later, is added to the time series code.

FIG. 4 shows a circuit diagram of the address reproducing circuit 13. Fifth
The figure is a time chart showing the signal states of each part of the circuit.

The address regeneration circuit 13 includes a resistor 47a and a capacitor 47.
It consists of an integrating circuit 47 consisting of a diode 47c and a diode 47c, three flip-flops 49.51.53, three logic gates 55, 57.59, and a shift register 61. A delay circuit τ connected to one end of each logic gate 55, 57, and 59 is composed of a resistor and a capacitor with one end grounded, and delays the phase by a minute time.

A line L1 connected to the address clock line 3 connects the clock input terminal CK of the flip-flop 49, the cathode side of the diode 47c and the resistor 47a of the integrating circuit 47, one input terminal of the exclusive OR gate, and the delay circuit τ. and the clock input terminal CK of the flip 70 knob 53, respectively.

The anode side of the diode 47C, the other end of the resistor 47a, and the other end of the capacitor 47b whose one end is grounded are connected together, and the flip-flops 49 and 51 are connected to this junction.
The data input terminals are connected to each other. The output terminal of the exclusive OR gate 55 is connected to the clock input terminal GK of the flip-flop 51. The output terminal Q of the flip-flop 51 is connected at one end to the logic gate 57 via the delay circuit τ, and the output terminal of the logic gate 57 is the data input terminal of the flip-flop 53. connected to.

The output terminal Q of the flip-flop 53 is connected to each clock input terminal GK of the shift register 61, and the first bit of the shift register 13 is connected to the flip-flop 70.
The output terminal Q of the knob 49 is connected, and each bit of the register 61 is connected to the line L5 (see FIG. 1). The output terminal Q of the flip 70 tube 53 is connected to one end of the logic gate 5 via a delay circuit τ at the other end.
The output terminal of the logic gate 59 is connected to the line L7.

In the address reproducing circuit 13 having the above configuration, the times JIIL
Address clock signal 84 (fifth
(see figure (a')) is integrated by the integrating circuit 47, so the output of the integrating circuit is the code 1 of the address clock signal S4.
It becomes a triangular wave whose level increases with time in the high level section of S5, and the state of the triangular wave signal S5 is shown in Fig. 5(b)
The result will be as shown in . The output of the output terminal Q of the flip-flop 49 receives the triangular wave signal S5 at its data input terminal, and also receives the triangular wave signal S5 at its clock input terminal as shown in FIG.
) is receiving the address clock signal S4 shown in FIG. The signal S6 becomes high level.

This signal S6 becomes a demodulated signal of a code string signal obtained by delaying the code string of the address clock signal S4 by Δt and converting it into NRZ code.

The output signal S7 of the exclusive OR gate 55 is
Since the address clock signal S4 and a signal obtained by delaying the address clock signal S4 by a minute amount of time by the delay circuit τ are input to the input terminal, the timing when the levels of these input signals are different, that is, the address clock signal S4 The signal becomes a sharp pulse signal as shown in FIG. 5(d), which is at a high level for a short period of time at the rising or falling timing of the signal.

The flip-flop 51 receives the output signal S5 of the integrating circuit 47 at its data input terminal, and also receives the output signal S7 of the exclusive OR gate 55 at its clock terminal GK. is the fifth
As shown in Figure (e), the signal remains at a high level from the peak of the triangular wave of the triangular wave signal S5 until the time when the next sharp pulse signal S7 appears. This signal S8 is a 50% duty signal having a rising edge at the center of one symbol of the address clock signal.

The logic gate 57 receives the signal S8 through the delay circuit τ at the other input terminal on the side provided with the inverter, so that the output signal S9 is output from the logic gate 57.
As shown in Fig. 5 <f>, is a minute time Δt determined by the delay circuit at the rise time of the signal shown in Fig. 5 (e').
It becomes a pulse signal that becomes high level.

The flip 70 knob 53 receives the signal S9 at the reset terminal R and the address clock signal S4 at the clock input terminal CK, so that the clock signal S4 is input to the clock input terminal GK as shown in FIG. At the time corresponding to the code 0 of the address clock signal S4, a signal with a different signal level is formed at each rising edge, and at the time corresponding to the code 1 represented by a pulse wave with a duty of 50%, the center A demodulated signal of the reference clock signal S3 is formed by converting the level at each position.

The logic gate 59 inputs the demodulated signal S10 directly to the input terminal on the side provided with the inverter, and inputs the demodulated signal S10 to the other input terminal via the delay circuit τ, so that the output signal 811 is as shown in FIG. As shown in (h), at the falling edge of the signal 810, a signal S11 having a sharp pulse with a time width determined by the delay circuit τ is output. This signal 811 becomes an intermediate correction synchronization signal for performing intermediate correction, which will be described later, in synchronization with the intermediate position of the period T of each code of the address clock signal S4.

The shift register 61 receives the demodulated signal S6 of the code string at its data input terminal, and also receives the demodulated signal 810 of the reference clock signal at each clock input terminal GK, so it uses this signal S10 as the clock signal. The demodulated signal S6 of the code string is sequentially read into the first bit in synchronization with the rising timing of this signal, and the read contents are sequentially shifted to the right in the figure. Therefore, now assume that the code string is a fourth-order M sequence, and the shift register 6
1 is composed of a 4-bit register, the shift register 61 receives an address clock signal S.
A code string pattern as shown in FIG. 5(i) appears at the beginning of each of the four time slots. Note that in the fourth-order M series as described above, the number of bits n of the shift register can be determined freely.

As described above, the address reproducing circuit 13 shown in FIG.
From line L5 to code string pattern 0 shown in Figure 5 (+>
001.0000.1000. .

Note that the address-number circuit 15 shown in FIG. . . . and the four-digit address assigned to the self, and if they match, the data match signal 512 (Fig. 8(a) This time T is the same length as the time T shown in FIG.

FIG. 6 is a circuit diagram of the oscillation synchronization circuit 11' provided in the transmitter I19. FIG. 8 is a time chart showing the signal states of each part, which is also used in FIG. 7, which will be described later.

The oscillation synchronization circuit 17T is configured so that the data transmission means described later is NR.
It is for forming a synchronization signal when outputting data with Z code, and has three logic gates 63, 65, 67,
A counter 69 configured by combining three flip-flops and a reset set flip 70 with set priority
It consists of a knob 71 and an oscillator 73.

The oscillator 73 includes a resistor 73a and two capacitors 73b, 7
3c and three inverters 73b and 73e.

It is composed of 73f and Nantes gate 73a,
When a high level signal appears at one input terminal of the Nandt gate 73g, a pulse signal of a predetermined frequency is output from the output terminal of the inverter 73[.

The intermediate correction synchronization signal 811 inputted via the line L7 in the upper left of FIG.
and is input to one input terminal of the OR gate 63. Further, an address match signal 812 input via line L6
are each reset terminal R of the counter 69 and the AND gate 6
It is input to one input terminal of 7.

It is assumed that initially the address match signal 812 is at a low level and the output terminal Q of the flip 70 knob 71 is at a high level. Therefore, the AND gate 67 is
) When the high-level data match signal 812 shown in FIG.

Then, the oscillator 73 starts oscillating and outputs the transmission clock signal 813 shown in FIG. 8(b) to the line L8. At this time, assuming that the transmission data is 10 bits including the start and parity pits, these data are sequentially converted into NRZ codes from the first bit through the transmission means in synchronization with the rising edge of the transmission clock signal 813. It is being sent. The transmitting means is the parity pit generating circuit 19. shown in FIG. It includes a parallel-to-serial conversion circuit 21.

On the other hand, the counter 69 receives the transmission clock signal 813.
is received at its clock input terminal CK via the OR gate 63, and its number is counted in synchronization with the rise of the transmission clock signal S13. When the count value reaches 6, that is, the contents of the counter 69 are 011 in the illustrated array.
Then, the AND gate 65 outputs the high-level transmission stop signal 814 shown in FIG. 8(C), and
Reset the flip 70 knob 71. As a result, the AND gate 67 outputs a low level signal and stops the oscillation of the oscillator 73. As a result, the transmission of 10-bit data is temporarily interrupted when 5-bit data is transmitted.

Next, the synchronizing signal 511 for intermediate correction shown in FIG. 8(f) is sent to the OR gate 63 from the line L7.
(See Figure 5 (h)) is input, so the counter 69
is counted up by 1, and the output signal S14 of the AND gate 65 is set to low level again. At the same time, since the synchronizing signal S11 for intermediate correction is input to the set terminal S of the flip-flop 71, the flip-flop 70 knob 71 is set and outputs a high-level signal to one input terminal of the AND gate 67. And at this time, and gate 6
Since a high-level address match signal is currently input to the other input terminal of gate 7, the gate 67 outputs a high-level signal.

Therefore, the oscillator 73 is operated at the eighth
Oscillation is started again in synchronization with the signal S11 shown in FIG. 5(f). Then, from line L8, as shown in Fig. 8(b)
The transmission clock shown in is outputted, and the remaining 5 bits are transmitted in synchronization with the falling edge of this transmission signal. Note that FIG. 8(0) shows a transmission status DB of data bits in transmission and reception.

FIG. 7 is a circuit diagram showing the oscillation synchronization circuit of the receiver.

The oscillation synchronization circuit 17R of the receiver is the oscillation synchronization circuit 1 of the transmitter.
In addition to 7T, it has a flip-flop 75° and an AND gate 77. The data input terminal of the flip 70 and the knob 75 are connected to the line L6, and the reset terminal R is connected to the line L.
Further, the output terminal Q is connected to one input terminal of the AND gate 77, and the output terminal Q is connected to the address clock line 3. The other input terminal of the AND gate 77 is connected to the output terminal of the oscillator 73, and its output terminal is connected to the line L8.

Oscillator 73 starts oscillating upon receiving address match signal 812, similar to oscillator 73 shown in FIG.

However, since the address match signal S12 of the flip 70 and the knob 75 is initially at a low level, the output terminal Q is reset and is at a low level. Therefore, in the oscillation synchronization circuit shown in FIG. 7, the clock signal of the oscillator 73 is not output the first time, as shown in FIG. 8(d), and the data shown in FIG. 8(a) is output. Start bit It starts outputting after receiving the "start" signal. Then, in synchronization with the rise of this receiving signal 815, the first
Parity check circuit 25 shown in the figure. Serial-parallel conversion circuit 27. It is received by a receiving means consisting of an output data latch circuit.

The effect of the clock stop signal S14 shown in FIG. 7 is also similar to that shown in FIG. That is, when the content of the counter 69 reaches 011, a stop signal is sent to the oscillator 73, and the oscillator 73 stops oscillating.

Then, when the synchronizing signal S11 for intermediate correction is inputted to the oscillator 73 via the line L7, it starts oscillating again in the same manner as shown in FIG. This means that even if there is a phase shift in the 5th bit reception signal, this will be reflected in the 6th bit.
This means that the deviation is not introduced into the bit-th reception signal. In other words, the reception clock, that is, the oscillator 7
This means that 3 is being corrected.

The receiving means receives the receiving signal 815 shown in FIG.
At the rising edge of this signal, the data from the 6th bit onwards is sequentially received, and after receiving the 10th bit, the parity bit, the reception ends at the rising edge of the end signal of the received data.

The receiver 11 shown in FIG. The received data is latched by the output data latch circuit 29 and sent to the data output line O.
The signal is passed to a reception processing circuit (not shown) via the UT, and the reception processing circuit performs predetermined processing, such as turning on a vehicle headlight or operating a predetermined actuator.

As described above, according to the embodiments shown in FIGS. 1 to 8, it is possible to divide 10-bit data into data of 5 bits each and perform intermediate correction of the transmitting/receiving clock (oscillator) using the intermediate correction synchronization signal. Therefore, 10-bit data can be transmitted to Nissin without synchronization.

(Second Embodiment) Next, another embodiment in which an arbitrary number of synchronization signals for intermediate correction can be obtained will be described with reference to FIGS. 9 to 13.

This example differs from the first example described above only in the address clock generator and the address regeneration circuit.
The oscillation synchronization circuit shown in the overall diagram, FIGS. 6 and 7 can be used as is. Note that in this example, a third-order M-sequence code is used as the code string.

FIG. 9 is a circuit diagram of the address clock generator, and FIG. 10 is a time chart of signal states of various parts.

As shown in FIG. 9, the address clock generator 7 includes a reference clock generator 79 that generates the reference clock signal S16 shown in FIG. 10<a>, and a reference clock generator 79 that generates the reference clock signal S16 shown in FIG. ).

(llj), 1/2.1/4.1/ as shown in (d)
It has a frequency divider 81 that divides the frequency into 8. Then, the output signal S17.8 of the first frequency dividing stage and the second frequency dividing stage of the frequency divider
The OR gate 83 and the AND gate 85 input 18 and output the signal 820.821, and the output signal 819 of the third frequency divider with a period T is input, and the signal 822 of the third-order M sequence code is input every period . It has an M-sequence signal generator 87 that generates an M-sequence signal.

Further, the address clock generator 7 includes an AND gate 89 inputting the signals S22 and S20, and an AND gate 89 inputting the signals S22 and S20.
is inputted to one input terminal via an inverter 91, and the signal S21 is inputted to the other input terminal, and the output signals of these AND gates 89 and 91 are inputted, and the address clock signal S23 is inputted to the address clock line 3. It has an OR gate 95 that outputs to. ANDGATE89. Inverter 91. ANDGATE93. The OR gate 95 forms a switching gate circuit 97.

OR gate 83 receives clock signal 817. In response to S18, a signal S20 with a period T/2 and a wide high level width as shown in FIG. 10(e) is generated.

The AND gate 85 similarly receives the signal S17.818, and generates a signal 821 with a period T/2 and a wide low level width as shown in FIG. 10 (Cf).

Since the AND gate 89 receives the M-sequence signal 322 shown in FIG. 10(a) and the signal S20, it becomes low level in the region where the sign of the M-sequence signal 822 is O.
In the region marked @1, the state of the signal S20 is output as is. In addition, in the AND gate 93, FIG.
Since the inverted signal of the M-sequence signal S22 shown in a) and the signal 821 are received, the M-sequence signal 822 is at a low level in the area of code 1, and the signal S20 is in the area of code 0.
The state will be output as is. Therefore, the address clock signal output from the OR gate 95 becomes a signal 820 with a wide high level width when the M sequence code is 1, and becomes a signal 323 with a wide low level width when it is O.

FIG. 11 shows a circuit diagram of the address reproduction circuit 11i13. FIG. 12 is a time chart showing signal states of each part.

This address reproducing circuit 13 includes an integrating circuit 47. similar to that shown in FIG. The Noritub flop 49 has a shift register 61a, and in addition, it receives the output signal S25 of the flip 70 and the address clock signal S2.
A 6-bit shift register 99 that sequentially shifts from right to left in the figure in synchronization with 3, and three exclusive ops that receive the output signals of each bit ■ to ■ of the shift register as shown in the figure. Agate 101,103゜1
05, a NOR gate 107 that inputs the output signals of these three exclusive OR gates, and a synchronization circuit for intermediate correction that receives the output signal S26 of the NOR gate through a delay circuit 109 on one side and an inverter on the other side. signal 827
It has an AND gate 111 that outputs. The output signal 826 of the NOR gate 107 is input to the clock input terminal of the shift register 61.

In this example, since the code string is a third-order M sequence, the shift register 61a is shown as a 3-bit example.

The address clock signal 823 is shown at No. 1251 (a). This signal 823 is passed through the integration circuit 47 to the 12th
The signal is replaced with the signal S24 shown in Figure (b). This signal 824 is read into the flip 70 knob 49 at the falling edge of the address clock signal 823, so the flip 70
The output signal of the 0 knob 49 is as shown in FIG. 12 <C>.
A demodulated signal S25 of a code string is output in such a manner that the state of code 1.0 can be read twice at the midpoint of each time slot of the data clock signal and at the end. Here,
A little earlier means the period Δt of the reference clock shown in FIG. 10<a).

The shift register 99 reads the demodulated signal S25 of the code string at the rising edge of the address clock signal 823. That is,
The same signal is read twice in each time slot. Therefore, the contents of the 6-bit shift register 99 at each time are as follows.

t6 → 000001 [7 → 000011 t8 → oooii.

t9 → 001100 tlo -* 011001 t It → 110011 t 12 → 100111 As shown above, for example, at time t6, the content of the shift register 99 is 000001, and at time t7
Then it is 000011. At this time, the exclusive OR gates 101, 103, and 105 are 001 at time t8 and 000 at time t7.

In this way, three exclusive or gates 101.1
03, 105 (7) output (g No. BT/2m, it repeats matching and mismatching. Therefore, the NOR gate 107 that inputs the output signals of these three exclusive OR gates 101, 103, and 105 is T In other words, a demodulated signal of the clock signal shown in FIG. 10(d) is formed.

The OR gate 827 receives the demodulated signal S26 through the delay circuit τ at one end and through the inverter at the other end.
A signal 8 having a pulse width determined by the delay circuit at exactly the midpoint of each time slot of the code string with respect to these input signals.
27 is output to line L7. This signal S27 is shown in FIG.
h) is the same type of synchronization signal for intermediate correction shown in the first embodiment.

Note that the output signal 826 of the NOR gate 107 is input to the clock input terminal of the shift register 61a, and the first
In synchronization with the rise of the demodulated signal 826 shown in FIG. 2(d), the demodulated signal of the address clock signal shown in FIG. 12(C) is sequentially read into the shift register 61a.

The contents of the shift register 61a at each time are shown in FIG. 12 (Cf).

Synchronization signal 827 for intermediate correction shown in the above second embodiment
The operation is exactly the same as that shown in the first embodiment, and intermediate correction of the oscillator 73 is performed in the same manner as explained using FIGS. It is possible to transmit 5 bits at a time using the NRZ code.

In the above description of the second embodiment, the number of bits of the shift register 99 was set to six stages, but in general, it is set to 20 stages for a zero-order M-sequence signal.

Also, as is clear from FIGS. 10 and 12,
The demodulated signal 826 shown in FIG. 12(d) is
If the number of rising signals at the O code and falling signals at the 1 code of the code string signal in a) is set to an appropriate number, a synchronizing signal for intermediate correction similar to that shown in Fig. 12(e) can be applied within the time slot. You can make it so that you only get a number. For this purpose, FIG. 10(e).

The signals 820 and 821 shown in (d) must be made appropriate, but this can be easily done by making the frequency division stages of the frequency divider 81 appropriate.

Thus, if the synchronization signal 827 for intermediate correction shown in FIG. 12<e> can be obtained every 1/3 or every 1/4 of the time slot, the results of FIGS. A plurality of bits of data are divided into predetermined amounts according to the accuracy of the oscillator 73 shown in FIG. 7, and NRZ code data transmission can be performed without synchronization.

[Effects of the Invention] As described above, the present invention obtains one or more intermediate correction synchronization signals within a time slot of an address clock signal, and divides multiple bits of data into predetermined amounts while synchronizing with these signals. Since the data can be transmitted using the NR2 code, multiple bits of data can be transmitted at high speed without generating high frequency noise from the transmission path.

Furthermore, because the present invention does not necessarily require high precision in the transmitting/receiving clock, it is possible to provide a multiplex transmission device that is correspondingly inexpensive.

[Brief explanation of drawings]

The drawings all show embodiments, and FIG. 1 is a schematic block diagram of a multiplex transmission device shared by each embodiment. 2 to 8 show the first embodiment, FIG. 2 is a circuit diagram of the address clock generator, FIG. 3 is a time chart showing signal states of each part of the circuit, and FIG. 4 is an address regeneration circuit. 5 is a time chart showing the signal status of each part of the circuit, FIG. 6 is a circuit diagram of the oscillation synchronous circuit located at the transmitting station, and FIG. 7 is the oscillation synchronous circuit located at the receiving station. The circuit diagram of Figure 8 is similar to Figures 6 and 7.
5 is a time chart showing signal states of each part shared in the figure. 9 to 12 show the second embodiment, FIG. 9 is a circuit diagram of the address clock generator, FIG. 10 is a time chart showing signal states of each part of the circuit, and FIG. 11 is an address regeneration circuit. FIG. 12 is a time chart showing the signal states of each part of the circuit. Note that FIGS. 6 to 8 are shared by the second embodiment. 1... Multiplex transmission device 3... Address clock line 5... Data line 7... Address clock generator 9... Transmitter 11... Receiver 13... Address regeneration circuit 15...・Address-number circuit 17T...Transmitter oscillation synchronization circuit 17R...Receiver oscillation synchronization circuit 811.327...Synchronization signal for intermediate correction Patent applicant Nissan Motor Co., Ltd. Figure 2 Figure 3 Figure 4 Figure 5 "90/" Figure 10 (h) S23T/2T/2 Figure 11 7゛. (f)----on 01100010101110
m --- Procedural Authorization (Spontaneous) July 1, 1985 Manabu Shiga, Director General of the Patent Office 1, Indication of Case 1985 Patent Application No. 58271
No. 2, Title of the invention Multiplex transmission device 3, Relationship to the amended person's case Patent applicant address (residence) 2, Takaracho, Kanayō-ku, Yokohama, Kanagawa Prefecture Name (name) (399) Representative of Nissan Motor Co., Ltd.
Shun Ishihara 4, Agent address: 1-2-3 Toranomon, Minato-ku, Tokyo 105
No. Toranomon No. 5th Floor, Building (Date of shipment: Month, Day, Showa) 6, Subject of amendment (1) Side number of "Detailed Description of the Invention" for specification (2)
Drawing 7, Contents of amendment (1) In the specification, page 10, line 2, the statement "...synchronization is the king..." has been replaced with "...the period is the king...""..." I corrected myself. (2) In the specification, page 10, line 9, the phrase "...at the rising edge of the clock signal..." has been replaced with "...at the rising edge and falling edge of the clock signal."・
"..." I corrected myself. ) In the specification, page 12, line 19, the phrase [...at the data input terminal...] is corrected to read, "...at the data input terminal R...". (4) In the specification, page 13, line 3, "...of the shift register 13..." has been replaced with "...of the shift register 61..." to correct. (5) In the specification, page 14, line 6 to line 8 of the same page, it is stated that ``This signal 86 is a code string signal obtained by delaying the code string of the address clock signal S4 by Δt and converting it into NRZ code. It becomes a demodulated signal.'' is deleted. (6) In the specification, page 15, line 8 to line 9 of the same page, it is stated that ``...an inverter is directly connected to one input terminal of A...''
・" is replaced with ``...leave the - input terminal as it is and connect the inverter.
"..." I corrected myself. (7) Specification, page 17, line 3, “...4
The phrase "This is the next M-sequence..." is corrected to read, "...This is the fifth-order M-sequence..." (8) In the specification, page 17, line 4, the statement ``...4-bit register...'' is corrected to ``...5-bit register...''. (9) In the specification, page 17, line 8, "...J of the 4th order as above..." is replaced by "...J of the 5th order as above..." and correct it. Tsukuda) Akira I, page 18, line 15 to page 19
The line ``The oscillator 73 includes a resistor 73a, two capacitors 73b,
730 and three inverters 73b and 73e. It is composed of 73f and Nantes gate 730,
When a high level No. 1m appears at one input terminal of the Nant gate 73 (I), the oscillator 73 consists of a resistor 73a and two capacitors 73b.
, 73c, and two inverters 73d. 73e and a Nandts gate 73f, and when a high level signal appears at the - input terminal of the Nandts gate 73, the inverter 73e corrects . (11) Specification, page 19, line 20, “...
・Correct the phrase ``At the rising edge...'' to ``...At the falling edge...'' (12) In the specification, page 20, line 9, the statement "...the count value is 6..." is amended to read "...the count value is 5...". Qll Specification, page 20, line 10, "...
``If the array is 011,'' is corrected to ``...If the array is 101,''. (2) In the specification, page 23, line 7, the statement "...the contents are 011..." is amended to read "...the contents are 101...". (In the 19th specification, page 28, line 12, "...shift register 61" is corrected to "...shift register 61a"). (g) Specification, page 30, line 17 to page 18
In the first line, the statement "The OR gate 827 that receives..." is corrected to "The AND gate 111 that receives...". 0 Figures 4, 5, 6, 7, and 12 will be corrected as shown in the attached sheet. 8. Catalog of attached documents Drawings Figure 4, Figure 5, Figure 6, Figure 7, Figure 12
1 or more copies each Fig. 5 Fig. 12 (f) ----111011001100010101
110---Procedure Nef11 official document (spontaneous) July 6, 1985 Manabu Shiga, Commissioner of the Patent Office 1, Indication of the case 1985 Patent Application No. 58271
No. 2, Title of the invention Multiplex transmission device 3, Relationship to the amended person's case Patent applicant address (residence) 2, Takaracho, Kanayō-ku, Yokohama, Kanagawa Prefecture Name (name) (399) Representative of Nissan Motor Co., Ltd.
Yutaka Kume 4, Agent address: 1-2-3 Toranomon, Minato-ku, Tokyo 105
Toranomon No. 5 Building 5th Floor Telephone: Tokyo (504) 3075, 3076, 3077
No. 6. Drawings to be amended (Figures 6 and 7) 7. Details of the amendment Figures 6 and 7 will be revised as shown in the attached sheet. 8. At least one catalog drawing of attached documents (Figures 6 and 7)

Claims (1)

[Claims] a time series code generation means for generating a predetermined series of time series codes by providing a plurality of synchronization signals for data transmission and reception within a time slot of a unit code; a time series code transmission path for transmitting the time series codes; and a time series code transmission path for transmitting the time series codes; a data transmission path installed in parallel with the code transmission path; a code string pattern detection means connected to the time series code transmission path for detecting a current code string pattern of a predetermined bit from the time series code of the predetermined sequence; a pattern/address matching means for comparing a code string pattern with an address assigned to itself; and a pattern/address matching means for comparing a code string pattern with an address assigned to itself; a data transmission/reception signal output means for outputting a data transmission/reception signal for transmitting/receiving a predetermined bit of data in an NRZ code for each synchronization signal; and a data transmission/reception signal output means connected to the data transmission path based on the data transmission/reception signal. 1. A multiplex transmission device comprising: data transmitting/receiving means for transmitting/receiving multiple bits of data to/from.