JPS61218158A - Rectifier circuit - Google Patents
Rectifier circuitInfo
- Publication number
- JPS61218158A JPS61218158A JP5834585A JP5834585A JPS61218158A JP S61218158 A JPS61218158 A JP S61218158A JP 5834585 A JP5834585 A JP 5834585A JP 5834585 A JP5834585 A JP 5834585A JP S61218158 A JPS61218158 A JP S61218158A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- layer
- rectifier circuit
- voltage
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000006641 stabilisation Effects 0.000 description 3
- 238000011105 stabilization Methods 0.000 description 3
- 230000000087 stabilizing effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 241000282806 Rhinoceros Species 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0761—Vertical bipolar transistor in combination with diodes only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Rectifiers (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、各種電子機器に多用されている整流回路に関
し、特にトランスレスの整流回路を半導体集積回路内に
構成する際に用いて好適な回路技術に関する、
〔背景技術〕
通常の電子機器においては、商用電源からフロートし、
かつ所望の電圧レベルの直流電源を得るために、変圧器
（以下においてトランスという）、整流回路、平滑回路
、電源安定化回路からなる電源装置が用いられている。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to rectifier circuits that are frequently used in various electronic devices, and in particular to circuit technology suitable for configuring transformerless rectifier circuits in semiconductor integrated circuits. ] In normal electronic equipment, it floats from the commercial power supply,
In order to obtain a DC power source at a desired voltage level, a power supply device consisting of a transformer (hereinafter referred to as a transformer), a rectifier circuit, a smoothing circuit, and a power supply stabilizing circuit is used.
一方、電子機器は小型かつ軽量であることが望ましく、
この観点からみると上記トランスは重量がある上に、電
流容量に対応して大型になり易く、しかもコスト高であ
る、等の問題点を有している。On the other hand, it is desirable for electronic devices to be small and lightweight.
From this point of view, the above-mentioned transformer has problems such as being heavy, tending to be large in proportion to the current capacity, and being expensive.
このため整流回路を電子機器に内蔵できれば、小型化が
できるがこの場合は整流回路を構成するため高耐圧の整
流素子、換言すればダイオードが必要になる、しかも、
上記ダイオードは電子機器の小型かつ軽量化を計る上で
、他の電子回路、すなわち負荷回路と一体に同一半導体
基板内に構成することが望ましい、
本発明者は上記技術的問題点ならびに技術的動向に鑑み
、トランスレスかつ高耐圧の整流回路を半導体集積回路
にて構成すべく種々の検討をおこなった。For this reason, if a rectifier circuit can be built into an electronic device, it can be miniaturized, but in this case, a high voltage rectifier element, in other words a diode, is required to configure the rectifier circuit.
In order to reduce the size and weight of electronic equipment, it is desirable that the above diode be constructed on the same semiconductor substrate together with other electronic circuits, that is, load circuits. In view of this, various studies were conducted to construct a transformerless, high-voltage rectifier circuit using semiconductor integrated circuits.
その結果、ノーマルサイズのＮＰＮ トランジスタのペ
ース・エミッタ接合を用いたダイオードでは、５ｖ〜７
ｖ程度の耐圧しか得られないことが明らかになった。As a result, a diode using a normal-sized NPN transistor pace-emitter junction will have a voltage of 5V to 7V.
It has become clear that only a withstand voltage of about V can be obtained.
また、ＮＰＮ）ランジスタのペース・コレクタ接合を用
いたダイオードでは、１５Ｖ〜２０Ｖ程度の耐圧が得ら
れるが、基板電流が大のとき基板電圧が持ち上がり、こ
れに起因して他の半導体素子との間に寄生サイリスクが
形成されやすいことが明らかになった。In addition, a diode using a pace-collector junction of an NPN transistor can achieve a withstand voltage of about 15V to 20V, but when the substrate current is large, the substrate voltage rises, which causes problems between the semiconductor element and other semiconductor elements. It has become clear that parasitic rhinoceros is more likely to form.
そし、・て・ＰＮＰ ）ランジスタのベース・エミッタ
接合を用いたダイオードでは、１５Ｖ〜２０Ｖの耐圧が
得られ、しかも寄生ダイオードが発失しにくいことが明
らかになった。It has also been revealed that a diode using the base-emitter junction of a PNP transistor can achieve a withstand voltage of 15V to 20V, and is less likely to generate parasitic diodes.
なお、上記トランジスタを用いたダイオードについては
、「集積回路工学１」（昭和５７年５月１５日、初版第
５刷発行、発行所コロナ社、ｐ１６９ ）に記載されて
いる。Note that a diode using the above-mentioned transistor is described in "Integrated Circuit Engineering 1" (May 15, 1980, first edition, 5th edition, published by Corona Publishing, p. 169).
ところで、我国の商用電源を例に述べると、実効値が１
００Ｖであり、最大値は１４１ｖである。By the way, taking the commercial power supply in Japan as an example, the effective value is 1.
00V, and the maximum value is 141V.
従って、整流回路に使用されるダイオードは、少なくと
も１４１Ｖ以上の耐圧を有していなければならない。Therefore, the diode used in the rectifier circuit must have a withstand voltage of at least 141V or more.
そこで本発明者は、上記ＮＰＮトランジスタのペース・
コレクタ接合を使用したダイオード、ＰＮＰ）ランジス
タのベース・エミッタ接合を使用したダイオードを半導
体基板内に形成し、しかも耐圧を向上させるべく検討を
おこなった。Therefore, the inventors of the present invention have developed
Diode using collector junction (PNP) A diode using the base-emitter junction of a transistor was formed in a semiconductor substrate, and studies were conducted to improve the withstand voltage.
そして、半導体集積回路を高耐圧プロセスとして知られ
たデバイスプロセスにて形成すると、１００Ｖ〜２０Ｏ
Ｖもの耐圧を有するダイオードが得られ、これＫよりト
ランスレスかつ半導体集積回路化された整流回路を構成
し得ることが判明した、
〔発明の目的〕
本発明の目的は、半導体基板内にトランスレス且つ高耐
圧の整流回路を構成することにある。If a semiconductor integrated circuit is formed using a device process known as a high-voltage process,
It was found that a diode having a withstand voltage as high as V was obtained, and that it was possible to construct a rectifier circuit that was transformerless and integrated into a semiconductor circuit. Another object of the present invention is to configure a rectifier circuit with high withstand voltage.
本発明の上記ならびにその他の目的と新規７．ｃ％徴は
、本明細書の記述及び添付図面から明らかになるであろ
う。7. The above and other objects and novel objects of the present invention. The c% characteristics will become clear from the description herein and the accompanying drawings.
本願において開示される発明の概要を簡単に述べれば、
下記の通りである、
すなわち、半導体基板内に高耐圧プロセスにてＮＰＮ
トランジスタのベース・コレクタ接合を使用した整流素
子としてのダイオード、ＰＮＰ ）ランジスタのペース
・エミッタ接合を使用した整流素子としてのダイオード
を形成し、高耐圧の上記各ダイオードを用いて半導体集
積回路内忙他の電子回路と一体に整流回路を構成するこ
とにより、トランスレス且つ高耐圧の整流回路を得る、
という本発明の目的を達成するものである。A brief summary of the invention disclosed in this application is as follows:
The process is as follows: In other words, NPN is formed in the semiconductor substrate using a high voltage process.
A diode as a rectifying element using the base-collector junction of a transistor (PNP) A diode as a rectifying element using the base-emitter junction of a transistor is formed, and each of the above diodes with high withstand voltage is used to create a bus inside a semiconductor integrated circuit. By configuring the rectifier circuit integrally with the electronic circuit of
This achieves the object of the present invention.
〔実施例−１〕
以下、第１図及び第２図を参照して、本発明を適用した
整流回路の第１実施例を説明するＣなお、第１図は整流
回路を含む電源装置全体の回路図、第２図は整流回路の
一部を構成するダイオードのデバイス構造を示す断面図
である、
本実施例の特徴は、高耐圧プロセスで形成したＰＮＰ
）ランジスタのペース・エミッタ接合を使用したダイオ
ードにより、整流回路を構成したことにある。[Embodiment 1] Hereinafter, a first embodiment of a rectifier circuit to which the present invention is applied will be explained with reference to FIGS. 1 and 2. Note that FIG. The circuit diagram and FIG. 2 are cross-sectional views showing the device structure of diodes constituting a part of the rectifier circuit.
) The rectifier circuit is composed of diodes using the pace-emitter junction of transistors.
１は半導体集積回路（以下においてＩＣという）であり
、その内部には整流回路２、電源安定化回路３、負荷回
路４が一体に構成されている。そして、外部接続端子３
．４に接続されたコンデンサＣ３は、コンデンサインプ
ット型の平滑回路５を構成する。なお、電源安定化回路
３は説明の便宜のため簡単な回路構成のものを図示した
ものであり、上記回路構成に限足されない。また、負荷
回路４についてもその目的、回路構成は限足されず、高
゛電圧レベルの電源を使用する回路であればよい。Reference numeral 1 denotes a semiconductor integrated circuit (hereinafter referred to as IC), in which a rectifier circuit 2, a power supply stabilization circuit 3, and a load circuit 4 are integrally constructed. And external connection terminal 3
．． A capacitor C3 connected to the capacitor C3 constitutes a capacitor input type smoothing circuit 5. Note that the power supply stabilizing circuit 3 is illustrated with a simple circuit configuration for convenience of explanation, and the circuit configuration is not limited to the above circuit configuration. Further, the purpose and circuit configuration of the load circuit 4 are not limited, and any circuit that uses a high voltage level power supply may be used.
ＰＮＰトランジスタスタへＱ４は高耐圧プロセスにて形
成され、そのベース・コレクタが接続されているので、
ペース・エミッタ接合を使用したダイオードとなる。Q4 to the PNP transistor star is formed using a high voltage process, and its base and collector are connected, so
This is a diode using a pace emitter junction.
従って、上記ＰＮＰ ）ランジスタＱ、〜Ｑ４は、それ
らの近傍に図示した極性を有するダイオードＶＣＴｘす
、いわゆるダイオードブリッジに接続して整流回路２が
構成される、
１番端子、２番端子には商用電源が供給され、１番端子
が正極性のとき、点線で示す経路で電流Ｉ、が流れる。Therefore, the above-mentioned PNP) transistors Q and ~Q4 are connected to diodes VCTx having the polarities shown in the figure in their vicinity, so-called diode bridges to form the rectifier circuit 2. When power is supplied and the No. 1 terminal has positive polarity, a current I flows through the path shown by the dotted line.
また、２番端子が正極性のとき、一点鎖線で示す経路で
電流■２が流れる、整流回路２の出力電圧Ｖ、は脈流で
あるが、コンデンサＣ１によって平滑され、はぼ直流化
される。Furthermore, when the No. 2 terminal has positive polarity, current 2 flows through the path shown by the dashed-dotted line, and the output voltage V of the rectifier circuit 2 is a pulsating current, but it is smoothed by the capacitor C1 and becomes almost a direct current. .
電源安定化回路３において、トランジスタＱｕは制御用
トランジスタであり、トランジスタＱ□は誤差検出用ト
ランジスタである。抵抗Ｒ，，Ｒ１はブリーダ抵抗であ
り、出力電圧ｖ０の電圧変動を検出してトランジスタＱ
Ｉ！を介してトランジスタＱｏを駆動する。なお、ツェ
ナーダイオードＺｄは基準電圧を規足し、抵抗Ｒ３はト
ランジスタＱ■忙ベース電流を供給するものである。In the power supply stabilizing circuit 3, the transistor Qu is a control transistor, and the transistor Q□ is an error detection transistor. Resistors R,, R1 are bleeder resistors, which detect voltage fluctuations in the output voltage v0 and turn on the transistor Q.
I! The transistor Qo is driven through the transistor Qo. The Zener diode Zd regulates the reference voltage, and the resistor R3 supplies the base current of the transistor Q.
上記回路構成によれば、ダイオードとなるトランジスタ
Ｑ、 ＳＱ、が高耐圧であることから一次側にトランス
を設けず、他の電子回路、換言すれば負荷回路４と一体
に整流回路２をＩＣにて構成できる。According to the above circuit configuration, since the transistors Q and SQ, which serve as diodes, have a high withstand voltage, no transformer is provided on the primary side, and the rectifier circuit 2 is integrated with other electronic circuits, in other words, the load circuit 4, into an IC. can be configured.
次Ｋ、上記整流回路２を可能にするＩＣのデバイス構造
を説明する。Next, the device structure of the IC that makes the rectifier circuit 2 possible will be explained.
第２図に示す３１はＰサブストレートであり、３２はＮ
−エピタキシャル層である。31 shown in FIG. 2 is a P substrate, and 32 is an N substrate.
- It is an epitaxial layer.
ここで注目すべきは、Ｎ 埋込層３３の形成位置である
。What should be noted here is the formation position of the N 2 buried layer 33.
すなわち、ノーマルサイズのデバイス構造では、上記Ｎ
埋込層３３は一点鎖線で示す位置に形成される。しか
し、高耐圧デバイス構造では、実線で示すようＫＰ層３
１内に、言わば掘り下げられたよ５Ｋして形成される。That is, in a normal size device structure, the above N
The buried layer 33 is formed at a position indicated by a dashed line. However, in a high voltage device structure, the KP layer 3 is
1, it is formed by digging 5K so to speak.
この結果、Ｎ＋埋込層３３とコレクタとなるＰ 層３４
．エミッタとなるＮ−７１３５との間隔が大になり、両
者の間のＮ−エピタキシャル層３２が厚くなり、上記高
耐圧のトランジスタＱ、〜Ｑ、が構成される。As a result, the N+ buried layer 33 and the P layer 34 which becomes the collector
．． The distance between the emitter and the N-7135 becomes large, and the N-epitaxial layer 32 between them becomes thick, thereby forming the high-voltage transistors Q, -Q.
なお、Ｎ＋層３６はベースになり、このＮ＋層は上記コ
レクタ、エミッタを囲った構造になっている。そして、
Ｐ 層３７はいわゆるアイランドを構成し、表面酸化膜
３８を挿通してアルミニウム端子３９が設けられている
。また、第１絶縁層４１、第２絶縁層４２は、それぞれ
ポリイミド、イソ、インドロキナゾリンジオンにて形成
されている。Note that the N+ layer 36 serves as a base, and this N+ layer has a structure surrounding the collector and emitter. and,
The P layer 37 constitutes a so-called island, and an aluminum terminal 39 is provided through the surface oxide film 38. Further, the first insulating layer 41 and the second insulating layer 42 are formed of polyimide, iso, and indoroquinazolinedione, respectively.
上記高耐圧デバイス構造のトランジスタＱ１〜Ｑ４によ
り、上記整流回路２を構成したので、１４１ｖ以上の電
圧が各トランジスタＱ、〜Ｑ４に印加されてもこれらが
破壊されることがなく、所望の電圧レベルの直流電圧を
同一ＩＣ内の負荷回路に供給することができる。Since the rectifier circuit 2 is constituted by the transistors Q1 to Q4 having the high voltage device structure, even if a voltage of 141 V or more is applied to each transistor Q, to Q4, these will not be destroyed, and the desired voltage level will be maintained. DC voltage can be supplied to a load circuit within the same IC.
〔実施例−２〕
次に、本発明の第２実施例を第３図及び第４図を参照し
て説明する。[Embodiment 2] Next, a second embodiment of the present invention will be described with reference to FIGS. 3 and 4.
なお、第３図は整流回路の回路図を示し、第４図はデバ
イス構造を示すものである。Note that FIG. 3 shows a circuit diagram of the rectifier circuit, and FIG. 4 shows the device structure.
本実施例の特徴は、高耐圧デバイス構造によって形成さ
れたＮＰＮトランジスタスタ＋〜Ｑ３４を用いて整流回
路２を構成したことにある、なお、実施例の説明にあた
っては、上記第１実施例と同一の部分には同一の符号を
付し、説明の重複を避けるものとする、
１番端子が正極性のとき電流工、が流れ、２番端子が正
極性のとき電流工、が流れる。上記整流回路２を構成す
る各ＮＰＮ）ランジスタＱ１〜Ｑ４は、ベース・エミッ
タ間が短絡され、ベース・コレクタ接合を使用してダイ
オードが構成されている。The feature of this embodiment is that the rectifier circuit 2 is constructed using NPN transistors Q34 formed with a high voltage device structure. The same reference numerals are given to the parts to avoid duplication of explanation.When the No. 1 terminal has positive polarity, the electric current flows, and when the No. 2 terminal has positive polarity, the electric current flows. Each of the NPN transistors Q1 to Q4 constituting the rectifier circuit 2 has its base and emitter short-circuited, and forms a diode using a base-collector junction.
そして、上記ＮＰＮトランジスタＱ、〜Ｑ４は、第４図
に示すようなデバイス構造になされている。The NPN transistors Q, -Q4 have a device structure as shown in FIG. 4.
高耐圧になすためのＮ＋埋込ＩｗＩ３３の構造は上記同
様であるが、Ｎ 層５１で形成されたベースは、いわゆ
るグラフトベース構造になされていることが特徴である
。なお、ＰＪｉ５２はベースとなり、Ｎ 層３６はコレ
クタとなる。The structure of the N+ buried IwI 33 for achieving a high breakdown voltage is the same as described above, but the base formed of the N layer 51 is characterized by having a so-called graft base structure. Note that the PJi 52 serves as a base, and the N layer 36 serves as a collector.
上記デバイス構造によれば、ダイオードとして使用され
る各トランジスタＱ１〜Ｑ４が高耐圧になり、１００ｖ
の商用電源をトランスを用いて降圧することなく整流す
ることができる。従って。According to the above device structure, each transistor Q1 to Q4 used as a diode has a high withstand voltage,
commercial power can be rectified without step-down using a transformer. Therefore.
電源装置全体をＲ１として示した負荷回路と一体に半導
体集積回路内に構成することができ、電子機器全体の小
型かつ軽量化を行うことができる。The entire power supply device can be integrated with the load circuit shown as R1 in a semiconductor integrated circuit, and the entire electronic device can be made smaller and lighter.
〔実施例−３〕
以下、第５図を参照して本発明の第３実施例を説明する
。[Embodiment 3] Hereinafter, a third embodiment of the present invention will be described with reference to FIG.
なお、第５図は倍電圧整流回路の一例を示す回路図であ
る。Note that FIG. 5 is a circuit diagram showing an example of a voltage doubler rectifier circuit.
本実施例の特徴は、上記デバイス構造で形成された２個
のＮＰＮ）ランジスタを用いて倍電圧整流回路を構成し
たことにある。The feature of this embodiment is that a voltage doubler rectifier circuit is constructed using two NPN transistors formed with the above device structure.
２番端子が正極性のときトランジスタＱｓ＋を介してコ
ンデンサＣＩＩＶＣ充電電流が流れ、Ｅｍの電圧レベル
に充電する。そして、１番端子が正極性のときは、商用
電源の電圧レベルＥｍとコンデンサＣ１１に充電されて
いた電圧レベルＥｍとによって充電される。従って、Ｒ
Ｌとして示した負荷回路４には無負荷電圧として２Ｅｍ
の出力電圧ｖ０がかかることＫなる。When the No. 2 terminal has positive polarity, a charging current flows through the capacitor CIIVC through the transistor Qs+, and the capacitor CIIVC is charged to the voltage level of Em. When the No. 1 terminal has positive polarity, it is charged by the voltage level Em of the commercial power supply and the voltage level Em charged in the capacitor C11. Therefore, R
The load circuit 4 shown as L has a no-load voltage of 2Em.
The output voltage v0 of K is applied.
本実施例によれば、整流回路ｌを負荷回路４と一体に半
導体集積回路化できるとともＫ、トランスを用いること
す＜、商用電源よりも昇圧された直流電圧を得ることが
できる。According to this embodiment, the rectifier circuit 1 can be integrated with the load circuit 4 into a semiconductor integrated circuit, and by using a transformer, it is possible to obtain a DC voltage higher than that of the commercial power source.
（１） 高耐圧デバイス忙より形成されたＮＰＮ ト
ランジスタのベース・コレクダ接合を利用したダイオー
ド、ＰＮＰ）ランジスタのベース・エミッタ接合を利用
したダイオードにより整流回路を構成したので、高耐圧
のｘｉ回路を負荷回路と一体に同一ＩＣ内に設けること
ができる。(1) A rectifier circuit is configured with a diode that uses the base-collector junction of an NPN transistor formed from a high-voltage device, and a diode that uses the base-emitter junction of a PNP transistor, so a high-voltage xi circuit is loaded. It can be provided integrally with the circuit in the same IC.
（２）上記（１）Ｋより、電子機器の小型かつ軽量化が
容易になる。(2) From (1) K above, electronic devices can be easily made smaller and lighter.
（３）上記高耐圧トランジスタを用いて倍電圧整流回路
をＩＣ内圧構成することができ、トランスを用いること
なく、商用電源よりも高電圧レベルの直流電圧を簡単な
回路構成で得ることができる。(3) A voltage doubler rectifier circuit can be constructed using the above-described high breakdown voltage transistor, and a DC voltage at a higher voltage level than that of a commercial power source can be obtained with a simple circuit configuration without using a transformer.
（４）上記（３）Ｋより、多種の電圧レベルが得られる
ので、整流回路の利用範囲を拡大することができる。(4) Since a variety of voltage levels can be obtained from the above (3) K, the range of use of the rectifier circuit can be expanded.
以上に本発明者によってなされた発明を実施例にもとづ
き具体的に説明したが、本発明は上記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることは言うまでもない。例えば、電源安定化
回路は各種回路構成のものを利用し得る、
整流回路は全波整流回路に限定されず、半波整流回路で
あってもよい。Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. stomach. For example, the power supply stabilization circuit can utilize various circuit configurations. The rectifier circuit is not limited to a full-wave rectifier circuit, but may be a half-wave rectifier circuit.
整流回路を構成する各トランジスタの耐圧をより一層向
上させることにより、３倍圧、４倍圧の整流回路を構成
することが可能になる。By further improving the withstand voltage of each transistor constituting the rectifier circuit, it becomes possible to configure a triple-voltage or quadruple-voltage rectifier circuit.
以上の説明では、主として本発明者によってなされた発
明をその背景となった利用分野である整流回路に適用し
た場合について説明したが、それに限定されることなく
、例えば検波回路にも利用できる。In the above description, the invention made by the present inventor is mainly applied to a rectifier circuit, which is the background field of application, but the invention is not limited thereto, and can also be applied to, for example, a detection circuit.
第１図及び第２図は本発明を適用した整流回路の第１実
施例を示すものであり、
第１図は電源装置の回路図、
第２図は整流回路を構成するトランジスタのデバイス構
造を示す断面図、
第３図及び第４図は本発明の第２実施例を示すものであ
り、
第３図は整流回路の回路図、
第４図はデバイス構造を示す断面図、
第５図は本発明の第３実施例を示す倍電圧整流回路の回
路図を示す。
１・・・ＩＣ１２・・・整流回路、３・・・電源安定化
回路、４・・・負荷回路、３１・・・Ｐサブストレート
、３２・・・Ｎ−エピタキシャル層、３２・・・Ｎ１埋
込Ｎ、Ｑｔ〜Ｑｓｚ・・・トランジスタ、Ｉ、、Ｉ、・
・・電流。
第 １ 図
第 ２ 図
第 ５ 図1 and 2 show a first embodiment of a rectifier circuit to which the present invention is applied. 3 and 4 show a second embodiment of the present invention, FIG. 3 is a circuit diagram of a rectifier circuit, FIG. 4 is a sectional view showing a device structure, and FIG. 5 is a sectional view showing a device structure. The circuit diagram of the voltage doubler rectifier circuit which shows 3rd Example of this invention is shown. DESCRIPTION OF SYMBOLS 1... IC12... Rectifier circuit, 3... Power supply stabilization circuit, 4... Load circuit, 31... P substrate, 32... N-epitaxial layer, 32... N1 buried Including N, Qt~Qsz...transistor, I,, I,...
...Current. Figure 1 Figure 2 Figure 5
Claims (1)
ランジスタのベース・コレクタ接合により形成されたダ
イオード、又はＰＮＰトランジスタのベース・エミッタ
接合により形成されたダイオードを設け、上記２種のダ
イオードを選択的に用いて構成したことを特徴とする整
流回路。1. Provide a diode formed by the base-collector junction of an NPN transistor or a diode formed by the base-emitter junction of a PNP transistor together with other electronic circuits in the same semiconductor substrate, and select the above two types of diodes. A rectifier circuit characterized in that it is configured using
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5834585A JPS61218158A (en) | 1985-03-25 | 1985-03-25 | Rectifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5834585A JPS61218158A (en) | 1985-03-25 | 1985-03-25 | Rectifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61218158A true JPS61218158A (en) | 1986-09-27 |
Family
ID=13081729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5834585A Pending JPS61218158A (en) | 1985-03-25 | 1985-03-25 | Rectifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61218158A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02108323A (en) * | 1988-10-18 | 1990-04-20 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
| JP2005348554A (en) * | 2004-06-04 | 2005-12-15 | Hitachi High-Technologies Corp | Voltage source circuit |
| EP1729345A3 (en) * | 2005-06-02 | 2008-04-23 | Fujitsu Limited | Semiconductor device having a diode for a rectifier circuit |
-
1985
- 1985-03-25 JP JP5834585A patent/JPS61218158A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02108323A (en) * | 1988-10-18 | 1990-04-20 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
| JP2005348554A (en) * | 2004-06-04 | 2005-12-15 | Hitachi High-Technologies Corp | Voltage source circuit |
| JP4496014B2 (en) * | 2004-06-04 | 2010-07-07 | 株式会社日立ハイテクノロジーズ | Voltage source circuit |
| EP1729345A3 (en) * | 2005-06-02 | 2008-04-23 | Fujitsu Limited | Semiconductor device having a diode for a rectifier circuit |
| US7750437B2 (en) | 2005-06-02 | 2010-07-06 | Fujitsu Semiconductor Limited | Semiconductor device having a diode for a rectifier circuit |
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