JPS61216472A - Manufacture of charge transfer device - Google Patents

Abstract

PURPOSE:To enable to suppress the irregularity of charge voltage conversion gain at every element by implanting an impurity to a floating diffused region with a field oxide film, a mask material and the electrode of a gate region at a semiconductor substrate, thereby suppressing the variation in the etching amount of the field oxide film. CONSTITUTION:After a field oxide film 31 is formed at the prescribed portion on a P-type silicon substrate 1, a gate oxide film 22 is formed, and an output gate 7 for forming a gate region and a transfer electrode 8 are formed on the film 22. Then, a mask material 33 having a hole 32 is formed near a floating diffused region forming portion partly inside of the film 31. Then, with the resist pattern 33, the film 31 and the output gate 7 as masks N-type impurity ions are implanted to the substrate to form a floating diffused region 34, the pattern 33 is separated, a charge transfer device is formed. Thus, the variation in the etching amount of the field oxide film is suppressed to suppress the irregularity in the charge voltage conversion gain at every element.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method of manufacturing a charge transfer device, and particularly improves the formation of a charge detection section.

[Technical background of the invention]

As is well known, the charge detection section of a charge transfer device has advantages such as a floating junction type detection circuit that accumulates signal charges in a floating diffusion region and detects the potential of the floating diffusion region. , is often used. Conventionally,
As a floating junction type detection circuit, for example, one shown in FIG. 5 is known.

1 in the figure is a P-type silicon substrate. This substrate 1 is provided with an N type region 2 for forming a buried channel, a floating diffusion region (N'' type region) 3, and an N+ type region 4 for resetting the potential of this floating diffusion region 3. , an N″″ type region 5 forming a barrier is provided in the N type region 2. A reset gate 6 for resetting the potential of the floating diffusion region 3 is provided on the substrate 1, and a constant voltage is applied thereto. Output gates 7, 211 and transfer electrodes 8, 9 and 10 of the embedded channel type COD register are respectively provided.In addition, 11 is a source follower circuit (N position detection means) for detecting the potential of the floating diffusion region 3, and 12 is a source follower circuit (N position detection means) for detecting the potential of the floating diffusion region 3. 1 and 2 respectively indicate a leader that generates a DC potential to be applied to the output gate 7.

In the detection circuit having such a structure, clocks Φ1 and Φ2 shown in FIG. 6 are applied to the transfer electrodes 8 to 10. In FIG. 6, (a) shows the pulse of Φ1, (b) shows the pulse of Φ2, and (C) shows the pulse of R3 (reset). Then, the potential distribution under the transfer electrodes 8 to 10 changes as shown in FIG. 7, and the signal charges are transferred from right to left.

When Φ1 is at a low level, the signal charge that has reached the transfer electrode 8 is
It passes through the output gate 7 and is accumulated in the floating diffusion region 3. At that time, the potential of the floating diffusion region 3 decreases in proportion to the signal charge, and the source follower circuit 11 detects the potential change.
Get the output signal. Here, the potential of the floating diffusion region 3 is Φ
This occurs between the falling edge of one pulse and the rising edge of the RS pulse.

Incidentally, the floating diffusion region of the detection circuit is conventionally formed as shown in FIGS. 3 and 4. Here, FIG. 4 is a sectional view taken along the line xx in FIG. 3. That is, first, a field oxidation film 121 and a gate oxide film 22 are formed on the substrate 1 by a conventional method, and then an output gate 7, a transfer gate 8, etc. are formed.

Here, the gate oxide film 22, output gate 7, transfer gate 8, etc. are collectively referred to as a gate region.

Subsequently, a resist pattern 24 is formed on the field oxide film 21 and the output gate 7, having an opening 23 a certain distance outward from the end of the portion where the floating diffusion region is to be formed. Next, using the field oxide film 11, resist pattern 14, and output gate 7 as masks, impurities are introduced into the substrate 1 to form a floating diffusion region 3.

[Problems with background technology]

However, according to the prior art, the floating diffusion region 3 is
The floating diffusion region is formed by introducing impurities into the substrate 1 using the resist pattern 24, the field oxide film 21, and the output gate 7 as masks, which have an opening a distance outward from the end of the part where the floating diffusion region is planned to be formed. The area of the diffusion region 3 depends on variations in the amount of etching of the field oxide film 21.

As a result, there is a problem in that the charge-voltage conversion gain of the output section varies from element to element.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for manufacturing a charge transfer device that can suppress variations in the amount of etching of a field oxide film and suppress variations in charge-voltage conversion gain from element to element. shall be.

[Summary of the invention]

In the present invention, a floating diffusion region that accumulates signal charges transferred from a charge transfer section is formed by a field oxide film and a mask material partially formed inside the field oxide film. By introducing impurities into the semiconductor substrate using an electrode in the gate region, this method attempts to suppress variations in charge-voltage conversion gain from element to element due to variations in the amount of etching of the field oxide film. .

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in order of manufacturing steps with reference to FIG. Here, only the vicinity of the floating diffusion region will be explained, and the same members as those of the conventional one will be given the same reference numerals and the explanation will be omitted.

First, at a predetermined location on a P-type silicon substrate 1
□"Field oxidation! After forming l131, a gate oxide film 22 is formed.Subsequently, this gate oxide film 2
2. On top of this is the output gate that forms the gate area.
A puff, a transfer electrode 8, etc. are formed (as shown in FIG. 1(a)). Then, a part of the field oxide film 31 is formed.
(-5 Resist pattern (mask material) having an opening 32 near the area where the floating diffusion region is planned to be formed
33 (as shown in FIG. 1(b)). After this attack, an n-type impurity was ion-implanted into the substrate using the resist pattern 33, field oxide film 31, and output gate 7 of the gate region as a mask to form a floating diffusion region (N+ type region 34). Thereafter, after peeling off the resist pattern 33, a charge transfer device was manufactured using a well-known technique (see Fig. 1 (
C) and as shown in Figure 2). Here, Figure 2 is Figure 1 (C)
In the plan view of , if Figure 2 is cut along the x-X line, the first
Figure (C) is shown. Note that the operation of this device is similar to that shown in FIG. 5 described above.

Therefore, according to the present invention, when forming the floating diffusion region 34, the resist pattern 33 having the opening 32 partially inside the field oxide film 31 near the part where the floating diffusion region is planned to be formed is used as a part of the mask. Therefore, a part of the boundary between the floating diffusion region 34 and the substrate 1 is defined by the resist pattern 33. Therefore, the area of the floating diffusion region 34 is less likely to change due to changes in the amount of etching of the field oxide film 33, and variations in charge-voltage conversion gain between devices can be suppressed. This is particularly effective in a shape defined by the field oxide film 31 that has a longer perimeter than the area of the floating diffusion region 34. In addition,
In this embodiment, mask displacement of the resist pattern 33 is added as a factor for variation in the area of the floating diffusion region 34;
With current technology, the mask shift is smaller than the etching amount of the field oxide film at 1 Bel.

〔Effect of the invention〕

As detailed above, according to the present invention, it is possible to provide a method for manufacturing a charge transfer device that can suppress variations in the amount of etching of a field oxide film, thereby suppressing variations in charge-voltage conversion gain with respect to the device throat. .

[Brief explanation of drawings]

1(a) to 1(C) are cross-sectional views showing the manufacturing method of a charge transfer device according to an embodiment of the present invention in the order of steps, and FIG.
FIG. 3 is a plan view for explaining the manufacturing of a floating diffusion region related to a conventional charge transfer device; FIG. 4 is a cross-sectional view taken along line X-X in FIG. 3; Figure 5 is a cross-sectional view of a 70-Ting junction type detection unit used in a charge detection unit of a charge transfer device, and Figure 6 is a cross-sectional view of Φ1 and Φ2 related to the detection circuit of Figure 5.
FIG. 7 is a timing diagram of each pulse of R8 and R8, and FIG. 7 is a potential distribution diagram of a transfer electrode related to the detection circuit. 1... P-type silicon substrate, 2... N-type region, 4...
...N4 type region, 6.-N- type region, 7..output gate, 8.9.10..transfer gate, 11..source follower circuit, 12..reader, 22..gate Oxide film, 31...Field oxide film, 32...Sekiguchi portion, 33-...Resist pattern, 34...Floating diffusion region (N+ type region. Applicant's representative Patent attorney Takehiko Suzue Figure 1) Figure 2 Figure 4 Figure 5 Figure 1ES Figure

Claims (1)

[Claims] A semiconductor substrate, a charge transfer section provided on the substrate for transferring signal charges, a floating diffusion region for accumulating signal charges transferred from the charge transfer section, and potential detection means for detecting the potential of the floating diffusion region. a field region that separates the floating diffusion region from other regions; and a gate region that is adjacent to the floating diffusion region and controls input and output of signal charges to the floating diffusion region. The floating diffusion region is formed by introducing impurities into the substrate using a field oxide film, a mask material partially formed inside the field oxide film, and an electrode in the gate region. A method for manufacturing a charge transfer device.