JPS61216343A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS61216343A
JPS61216343A JP60057130A JP5713085A JPS61216343A JP S61216343 A JPS61216343 A JP S61216343A JP 60057130 A JP60057130 A JP 60057130A JP 5713085 A JP5713085 A JP 5713085A JP S61216343 A JPS61216343 A JP S61216343A
Authority
JP
Japan
Prior art keywords
conductive path
earth
ground
inverting amplifier
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60057130A
Other languages
Japanese (ja)
Other versions
JPH0680671B2 (en
Inventor
Tetsuo Asano
哲郎 浅野
Takashi Otsuki
隆志 大槻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP60057130A priority Critical patent/JPH0680671B2/en
Publication of JPS61216343A publication Critical patent/JPS61216343A/en
Publication of JPH0680671B2 publication Critical patent/JPH0680671B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To realize a BTL connection in a stable operation by directly connecting the earth electrode with the earth bonding pad, and at the same time, to contrive to miniaturize the title circuit by stacking respectively the exclusive conductive path and the earth conductive path using a multilayer wiring. CONSTITUTION:An earth electrode 18, whereon an input signal to the inversion amplifier is impressed, is directly connected with an earth bonding pad 20 through an exclusive conductive path 19, and an earth conductive path 21 and the exclusive conductive path 19 and respectively stacked using a multilayer wiring. As each earth electrode of the noninversion amplifier and the inversion amplifier is not connected to the exclusive conductive path 19, unnecessary current does not run through the exclusive conductive path 19. Therefore, the fluctuations of the potential due to the resistance, which is caused by forming the exclusive conductive path 19 using an evaporating aluminum, can be nearly removed and the earth electrode 18 of a split resistor 3 can be fixed in nearly the same earth potential as that of the earth bonding path 20. As a result, a ripple component can be prevented from being included in the input signal to the conversion amplifier.

Description

【発明の詳細な説明】 (イ) 産業上の利用分野 本発明は半導体集積回路、特にBTL接続したアンプ回
路を内蔵する半導体集積回路の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in semiconductor integrated circuits, particularly semiconductor integrated circuits incorporating BTL-connected amplifier circuits.

(ロ) 従来の技術 半導体集積回路はその構造上高耐圧トランジスタを形成
するのが困難であり、アンプ回路を形成するにあたりB
TL接続による出力アップを図ることが良く用いられる
(b) Due to the structure of conventional semiconductor integrated circuits, it is difficult to form high voltage transistors.
It is often used to increase output through TL connection.

一般的にBTL接続は以下に説明する出力分割型(萬2
図)とNF70−ティング型(第亨図〕とがある。出力
分割型のBTL接続は非反転アンプ(1)の入力端子I
NK入力信号を印加し、帰還端子NFをコンデンサを介
して接地し、出力端子OUTより出力信号を得ている。
In general, BTL connections are of the output split type (man2
There are two types: the NF70-Ting type (Fig. 1) and the NF70-Ting type (Fig.
An NK input signal is applied, a feedback terminal NF is grounded via a capacitor, and an output signal is obtained from an output terminal OUT.

一方反転アンプ(2)の入力端子INを接地し、帰還端
子NFKは非反転アンプ(1)の出力信号を分割抵抗(
3)およびコンデンサを介して帰還させている。そして
負荷R1は両アンプ(1)(2)の出力端子間に接続さ
れて2倍の出力信号を得ている。
On the other hand, the input terminal IN of the inverting amplifier (2) is grounded, and the feedback terminal NFK connects the output signal of the non-inverting amplifier (1) to the dividing resistor (
3) and is fed back via a capacitor. A load R1 is connected between the output terminals of both amplifiers (1) and (2) to obtain twice the output signal.

NFフローティング屋のBTL接続は非反転アンプ(1
]の入力端子INK入力を印加し1反転アンプ(2)の
入力端子INを接地し1両アンプ(lバ2夛の帰還端子
NFをコンデンサと抵抗で接続し、両アンプ(1バ2)
の出力端子OUT間に負荷RLを接続している。
The BTL connection of the NF floating shop uses a non-inverting amplifier (1
], apply the input terminal INK input of 1 inverting amplifier (2), ground the input terminal IN of 1 inverting amplifier (2), connect the feedback terminal NF of 1 amplifier (1 bar 2) with a capacitor and a resistor, and connect both amplifiers (1 bar 2).
A load RL is connected between the output terminal OUT of the .

BTL接続は例えばステレオ再生装置、鈴本健著、日刊
工業新聞社、昭和45年11月発行、第189頁等で良
く知られている。
The BTL connection is well known, for example, in Stereo Reproduction Device, written by Ken Suzumoto, Nikkan Kogyo Shimbun, published November 1970, page 189.

斯上したBTL接続したアンプ回路を組み込んだ半導体
集積回路に於いては、反転アンプ(21の帰還端子NF
に入力信号を印加しているので帰還端子NFにリップル
成分を含んだ入力信号を入れると出力端子OUTよりハ
ムが出力される。これを防止するために出力分割型のB
TL回路では分割抵抗(3)を外付けとし、分割抵抗(
3)のアース電極をプリント基板のアースラインに直接
接続しており、NF70−ティング型のBTL回路でも
帰還端子NFに入力信号を印加する基準となるアース電
極を同様にプリント基板のアースラインに直結していた
In a semiconductor integrated circuit incorporating the above-mentioned BTL-connected amplifier circuit, the inverting amplifier (feedback terminal NF of 21
Since an input signal is applied to the feedback terminal NF, if an input signal containing a ripple component is applied to the feedback terminal NF, hum will be output from the output terminal OUT. To prevent this, output split type B
In the TL circuit, the dividing resistor (3) is externally connected, and the dividing resistor (
The ground electrode of 3) is directly connected to the ground line of the printed circuit board, and even in the NF70-Ting type BTL circuit, the ground electrode that serves as the reference for applying the input signal to the feedback terminal NF is also directly connected to the ground line of the printed circuit board. Was.

G/→ 発明が解決しようとする問題点しかしながら斯
る方法では安定化したBTL接続を実現できる反面外付
部品の増加および外部リードの増加となり、電子機器へ
の組み込み上望ましい状態とは言えなかった。
G/→ Problems to be Solved by the Invention However, although this method could achieve a stable BTL connection, it resulted in an increase in the number of external parts and external leads, which was not a desirable condition for incorporation into electronic equipment. .

に)問題点を解決するための手段 本発明は断点に鑑みてなされ、分割抵抗等をできるだけ
半導体集積回路に向風させ、反転アンプの入力信号を帰
還端子とアース電極間に印加し、入力信号の基準となる
アース電極を専用導電路σ9でアースボンディングパッ
ド■まで接続させ且つ専用導電路a9とアース導電路+
211とを多層配線で重ね合せたBTL接続に適した半
導体集積回路を提供するものである。
2) Means for Solving the Problems The present invention was made in view of the discontinuity, and the input signal of the inverting amplifier is applied between the feedback terminal and the ground electrode, and the input signal of the inverting amplifier is applied between the feedback terminal and the ground electrode. Connect the ground electrode, which is the reference of the signal, to the earth bonding pad ■ through the dedicated conductive path σ9, and connect the dedicated conductive path a9 and the earth conductive path +
The present invention provides a semiconductor integrated circuit suitable for BTL connection in which 211 and 211 are overlapped with multilayer wiring.

(ホ)作用 本発明に依れば1反転アンプの入力信号の印加されるア
ース電極が半導体集積回路内で一番安定なアースボンデ
ィングパッドに直結されるので、反転アンプの入力信号
にリップル成分が乗ることを最大限に抑制できるととも
に、専用導電路r19とアース導電路(211を多層配
線で重ね合わせて小型化を図ることを特徴としている。
(e) Function According to the present invention, the ground electrode to which the input signal of the inverting amplifier is applied is directly connected to the most stable ground bonding pad in the semiconductor integrated circuit, so that ripple components are not present in the input signal of the inverting amplifier. It is characterized by being able to minimize the risk of passengers getting on the ground, and by overlapping the dedicated conductive path r19 and the ground conductive path (211) with multilayer wiring to achieve miniaturization.

(へ)実施例 本発明の一実施例を第1図および第2図を参照して説明
する。
(F) Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 and 2.

第1図は本発明に依る半導体集積回路のチップ上面図を
示している。チップ中央には左右方向に電源ラインαυ
が延在され、チップを上下に第1領域α2および第2領
域α3とに2分している。上側の第1領域azには第3
図および第4図で示した非反転アンプ(1)を構成する
トランジスタ、−抗、コンデンサ等の回路素子を形成し
、下側の第2領域α3には同様に反転アンプ回路(2)
を形成している。ポンディングパッドαか・・α4は第
1領域α2および第2領域餞の周辺に適当な間隔で配置
される。各ポンディングパッドI・・・α供1対応する
リード(151・・・a9とボンディングワイヤαe・
・・(161で接続され、リードa9・・・a9はコン
デンサ等の外付部品が接続されている。
FIG. 1 shows a top view of a chip of a semiconductor integrated circuit according to the present invention. There is a power line αυ in the left and right direction in the center of the chip.
is extended, vertically dividing the chip into a first region α2 and a second region α3. The upper first area az has the third
Circuit elements such as transistors, resistors, and capacitors constituting the non-inverting amplifier (1) shown in FIGS.
is formed. The pounding pads α to α4 are arranged around the first region α2 and the second region at appropriate intervals. Each bonding pad I...α 1 corresponding lead (151...a9 and bonding wire αe/
...(connected at 161, and external parts such as capacitors are connected to leads a9...a9.

なお第1図で用いた各記号は第3図および第4図のもの
と対応している。
The symbols used in FIG. 1 correspond to those in FIGS. 3 and 4.

第1図に於いて実線で示した配線は多層配線の第1層目
配線であり、点線で示した配線は纂2層目配線を示して
いる。第1層目配線と第2層目配線の絶縁は周知のポリ
イミド樹脂等による層間絶縁膜を用いている。
In FIG. 1, the wiring shown by solid lines is the first layer wiring of the multilayer wiring, and the wiring shown by dotted lines is the second layer wiring. For insulation between the first layer wiring and the second layer wiring, an interlayer insulation film made of a well-known polyimide resin or the like is used.

本発明の特徴は反転アンプ(2)の入力信号が印加され
るアース電極u81を点線で示す専用導電路u9でアー
スボンディングパッド■と直結とし、アース導電路C1
1と専用導電路a9とを多層配線で積み重ねたことにあ
る。非反転アンプ(2)の出力端子OUTから反転アン
プ(1)の帰還端子NFへの帰還導電路顛は他回路との
影響を最少限とするために、チップの周端辺に沿って第
1層目電極としてポンディングパッドα4・・・Iの外
側を延在させている。そしてこの帰還導電路aηの内側
に沿ってアース導電路aδが延在されている。アース導
電路u8はチップの周辺に配置され、非反転アンプ(1
)および反転アンプ(2)の各アース電極(図示せず)
はすべて接続されてアースボンディングパッドCI!G
K導かれている。
The feature of the present invention is that the ground electrode u81 to which the input signal of the inverting amplifier (2) is applied is directly connected to the ground bonding pad ■ by a dedicated conductive path U9 indicated by a dotted line, and the ground conductive path C1
1 and the dedicated conductive path a9 are stacked in multilayer wiring. The feedback conductive path from the output terminal OUT of the non-inverting amplifier (2) to the feedback terminal NF of the inverting amplifier (1) is arranged along the periphery of the chip in order to minimize the influence with other circuits. The outer sides of the bonding pads α4...I are extended as layer electrodes. A ground conductive path aδ is extended along the inside of this feedback conductive path aη. The ground conductive path u8 is arranged around the chip and connects the non-inverting amplifier (1
) and each ground electrode of the inverting amplifier (2) (not shown)
are all connected to the earth bonding pad CI! G
K is being guided.

専用導電路0は第2図から明らかな様に半導体基板6υ
の酸化膜Q上に設けた一層目電極層より成るアース導電
wI(211上にポリイミド樹脂等の層間絶縁□□ 膜(至)を介して重ね合せて設けている。専用導電路(
19には反転アンプ(2)の入力信号を形成する分割抵
抗(3)のアース電極aδのみが接続されている。
As is clear from Figure 2, the dedicated conductive path 0 is located on the semiconductor substrate 6υ
A ground conductive layer consisting of the first electrode layer provided on the oxide film Q (overlaid on the ground conductive layer 211 via an interlayer insulating film made of polyimide resin, etc.).A dedicated conductive path (
19 is connected only to the ground electrode aδ of the dividing resistor (3) that forms the input signal of the inverting amplifier (2).

斯上した構造に依れば、専用導電路■には非反転アンプ
(17および反転アンプ(2Jの各アース電極は接続さ
れないので、専用導電路α9に不要の電流が流れない。
According to the above structure, the ground electrodes of the non-inverting amplifier (17) and the inverting amplifier (2J) are not connected to the dedicated conductive path (2), so no unnecessary current flows through the dedicated conductive path α9.

そのため専用導電路C19が蒸着アルミニウムで形成さ
れることに寄因する抵抗による電位の変動をほぼ除去で
き、分割抵抗(3)のアース電極u81をアースボンデ
ィングパッド■とほぼ同じアース電位に固定できる。こ
の結果反転アンプ(2)への入力信号にリップル成分を
含むことを防止できる。
Therefore, fluctuations in potential due to resistance due to the fact that the dedicated conductive path C19 is formed of vapor-deposited aluminum can be almost eliminated, and the ground electrode u81 of the divided resistor (3) can be fixed at substantially the same ground potential as the ground bonding pad (2). As a result, it is possible to prevent ripple components from being included in the input signal to the inverting amplifier (2).

また専用導電路a9はアース導電路(211と重ね合せ
て多層配線としているので、2系統のアースラインを設
けても実質的に余分なスペースを必要としない。
Furthermore, since the dedicated conductive path a9 is overlapped with the ground conductive path (211) to form a multilayer wiring, even if two systems of ground lines are provided, no extra space is required.

なおNF70−ティング型のBTL接続に於いても反転
アンプ(2)の帰還端子NFK印加される入力信号の基
準となるアース電極を同様に専用導電路でアースボンデ
ィングパッドと接続すれば良い。
In the case of the NF70-Ting type BTL connection, the ground electrode, which serves as a reference for the input signal applied to the feedback terminal NFK of the inverting amplifier (2), may be similarly connected to the ground bonding pad through a dedicated conductive path.

(ト)発明の効果 本発明に依れば、専用導電路α9により反転アンプ(2
)の入力端子として働く帰還端子NFとアース電極αδ
のうちアース電極σeをアースボンディングバク)−′
■と直結することによりアース電極u81のアース電位
を半導体集積回路内で低(且つ安定に保持されるので、
反転アンプ(21の入力信号にリップル成分が責ること
を防止でき安定な動作のBTL接続を実現できる。
(G) Effects of the Invention According to the present invention, the inverting amplifier (2
), the feedback terminal NF and the ground electrode αδ act as input terminals.
Among them, earth electrode σe is earth bonding back) −′
By directly connecting to
It is possible to prevent ripple components from being applied to the input signal of the inverting amplifier (21) and realize a BTL connection with stable operation.

また分割抵抗等の従来の外付は部品を内置できるので、
外付は部品の低減と外部リード本数の低減を図れ、大変
組み込みが容易となる。
In addition, conventional external parts such as dividing resistors can be placed internally, so
External mounting reduces the number of parts and external leads, making it very easy to integrate.

更に専用導電路α9とアース導電路O1とを重ね合せて
多層配線としている°ので余分なスペースを必要とせず
、専用導電路a9を帰還導電路aη上まで拡張するとシ
ールド効果を得られる。
Furthermore, since the dedicated conductive path α9 and the ground conductive path O1 are superimposed to form a multilayer wiring, no extra space is required, and a shielding effect can be obtained by extending the dedicated conductive path a9 onto the return conductive path aη.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のBTL接続したアンプを内置する半導
体集積回路を説明する上面図、第2図は第1図の■−■
線断面図、W43図及び第4図は一般的なりTL接続し
たアンプ回路を説明する回路図である。 主な図書の説明 (υは非反転アンプ、(2)は反転アンプ、(3)は分
割抵抗、 (171は帰還導電路、鰻はアース電極、σ
9は専用導電路、■はアースボンディングパッド、(2
11はアース導電路である。 出願人 三洋電機株式会社 外1名 代理人 弁理士  佐 野 靜 夫 l/+1  哨 第2図 第4図
FIG. 1 is a top view illustrating a semiconductor integrated circuit in which a BTL-connected amplifier of the present invention is installed, and FIG. 2 is a top view of the semiconductor integrated circuit of the present invention, and FIG.
The line sectional view, W43 diagram, and FIG. 4 are circuit diagrams illustrating a general TL-connected amplifier circuit. Explanation of the main books (υ is a non-inverting amplifier, (2) is an inverting amplifier, (3) is a dividing resistor, (171 is a feedback conductive path, eel is a ground electrode, σ
9 is a dedicated conductive path, ■ is a ground bonding pad, (2
11 is a ground conductive path. Applicant Sanyo Electric Co., Ltd. and 1 other agent Patent attorney Masao Sano l/+1 Figure 2 Figure 4

Claims (1)

【特許請求の範囲】[Claims] (1)非反転アンプと反転アンプでBTL接続したアン
プ回路を内蔵する半導体集積回路に於いて、反転アンプ
の帰還端子への入力信号の基準となるアース電極のみを
アースボンディングパッドまで接続する専用導電路と非
反転アンプ及び反転アンプの他のアース電極を前記アー
スボンディングパッドまで接続するアース導電路とを具
備し、前記専用導電路およびアース導電路を多層配線と
し且つ重ね合せることを特徴とする半導体集積回路。
(1) In a semiconductor integrated circuit that incorporates an amplifier circuit in which a non-inverting amplifier and an inverting amplifier are connected BTL, a dedicated conductor is used to connect only the ground electrode, which serves as the reference for the input signal to the feedback terminal of the inverting amplifier, to the ground bonding pad. and a ground conductive path connecting other ground electrodes of a non-inverting amplifier and an inverting amplifier to the ground bonding pad, the dedicated conductive path and the ground conductive path being multilayer wiring and overlapping each other. integrated circuit.
JP60057130A 1985-03-20 1985-03-20 Semiconductor integrated circuit Expired - Lifetime JPH0680671B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60057130A JPH0680671B2 (en) 1985-03-20 1985-03-20 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60057130A JPH0680671B2 (en) 1985-03-20 1985-03-20 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS61216343A true JPS61216343A (en) 1986-09-26
JPH0680671B2 JPH0680671B2 (en) 1994-10-12

Family

ID=13046974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60057130A Expired - Lifetime JPH0680671B2 (en) 1985-03-20 1985-03-20 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0680671B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7855447B2 (en) 2006-04-04 2010-12-21 Panasonic Corporation Semiconductor integrated circuit device, PDP driver, and plasma display panel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7855447B2 (en) 2006-04-04 2010-12-21 Panasonic Corporation Semiconductor integrated circuit device, PDP driver, and plasma display panel

Also Published As

Publication number Publication date
JPH0680671B2 (en) 1994-10-12

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