JPS6121564A - Process controller - Google Patents

Abstract

PURPOSE:To attain excellent control characteristic with simple software by providing an exclusive CPU for a processing to be executed repetitively in a short sampling period such as subtraction and PID to improve the data revision speed. CONSTITUTION:The CPU25 is provided newly. In this constitution, the CPU21 generates a set signal to be set as the reference state of the process and executes a program set in a setter 61. Further, the output of the setter 61 and an analog signal representing the process are inputted and a program generating the operation output outputted from the setting value 61 and while an analog signal representing the process is inputted, is executed. The operation in the CPU25 is repeated at a short sampling period required for the characteristic of process control. Thus, the data revising speed of the CPU5 is quickened sufficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital control device for controlling plant processes, and particularly to its arithmetic processing method.

[Prior art]

FIG. 1 is a block diagram showing a conventional device of this type. In the figure, the crests are processes, and (2) is a control device for controlling process (1). (3) is an analog input device (hereinafter abbreviated as AI) that converts the analog input signal from the process (1) into a digital signal; (41 is an operation station that generates a signal to operate the control device (2); , (5) is a digital input device (hereinafter abbreviated as DI) that converts the contact signal from the operation station (4) into a digital signal, and 16+ is a central processing unit (
+71 is an analog output device (hereinafter abbreviated as AO) that converts the digital signal output from the CPU +61 into an analog signal;
) is output to process (1) as the operation output,
It is used as a predetermined control signal, for example, an opening/closing signal for a control valve in the process (11).

FIG. 2 is a block diagram for explaining the arithmetic logic of the CPU t61 in FIG. 1, where the same reference numerals as in FIG.
) is a PID controller (hereinafter abbreviated as PID).

All processing within the CPU 161 is executed under program control, but the setting device (61) is controlled by the DI (5).
The setting value for process (1) (that is, the reference state of process at that time) is determined and output based on the input signal from AI (3) and the input value from AI (3).

The output of the subtracter (62) from which the input value from AI (3) is subtracted from this set value becomes an error signal (temporarily represented by ε), and feedback control is performed to make ε zero. 63) is ε to improve control characteristics.
is manually calculated, and the calculation determined by 2'-10 kaT)ε is performed on 5-ksε+, and the control No. 16 St is output.

Here, p represents the differential operator i'', and k□, 2゜k3
are each a proportional foot. The signal S is converted into a digital analog signal by the AU f7+ and becomes an operation output.

As described above, the control device (2) controls the process (1) according to operator commands given via the operating station (4).

Since the conventional device is configured as described above, it has the disadvantage that the data update period (ie, sampling period) of the operation output output from the control device 12) is long, resulting in poor controllability. It is setter (61), subtracter (62) under the program control of one CPU j61.
), the operation of the PID (63) is sequentially controlled, and the setting value in the setting device (bl) must be determined in relation to a lot of data, so the time required for this is large, and therefore Subtractor (62), PII) (63)
This is because the calculation repetition period in is also increased.

To eliminate this drawback, a subtractor (
Although it is possible to speed up the processing cycle of 62) and PID (63), this has the disadvantage that the program of the CPU 161 becomes complicated and the reliability of the software decreases.

[Summary of the invention].

This invention was made to eliminate the drawbacks of the conventional ones as described above, and in this invention, the subtracter (62) and the P
By providing a '22 CPU that processes only ID (63), the data update speed in the subtracter (62) and PID (63) is improved.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and (2o
) is the control device of the present invention, (21) is the first CPU, (
22) is AOl, (23) and (24) are AI, respectively.
(25) is the second CPU.

In the embodiment shown in FIG. 3, the CPU (21) and the CPU (
25), the CPU (
AI (23) which is converted into an analog signal by the output 'frAO (22) of 21) and connected to CPU' (25).
We have shown a design example that transmits data up to CPU (21) and C
If the PU (25) is nearby, the output of the CPU (21) may be input directly to the CPU (25).

Figure 4 shows the CPU (21) and CPU (2) in Figure 3.
5), in which the same reference numerals as in FIGS. 2 and 3 indicate the same parts. FIG. That is, C.P.
U (21) performs only the arithmetic processing corresponding to the setting device (61), and the CPU (25) performs the subtractor (62), PIL)
Since only the arithmetic processing corresponding to (63) is performed, the CPU (
25) In order to make the data update speed sufficiently fast,
can.

In addition, in the example shown in FIG.
AO (22) and AI to transmit data to (25)
(23), but the data transmission device may be covered with a gold film between them.

〔Effect of the invention〕

As described above, according to this invention, subtraction, PID, etc.
Since a dedicated CPU is provided for processing that must be repeatedly executed at short sampling intervals, good control characteristics can be obtained with a simple software configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional device, FIG. 2 is a block diagram for explaining the arithmetic logic of the CPU in FIG. 1,
FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a block diagram showing the division of operations between the two CPUs in FIG. (11...process, (41...operation station, ■...control device, (21)...first CPU, (
22)...Second CPU. (61)...Setter, (62)...Subtractor, (63
)...PID0 Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

[Claims] By inputting analog signals representing the state of the process and commands from an operator given by an operating station,
In a process control device that generates an operation output for the process by program control, a first central processing unit for executing a program that generates a setting signal to be set as a reference state of the process and sets it in a setting device; , a second central processing unit for executing a program that inputs the output of the setting device and an analog signal representing the state of the process and generates an operation output to be output to the process; A process control device characterized in that calculations in the second central processing unit are repeated at a short sampling period necessary for characteristics of process control.