JPS61214877A - Video signal processor - Google Patents
Video signal processorInfo
- Publication number
- JPS61214877A JPS61214877A JP60056752A JP5675285A JPS61214877A JP S61214877 A JPS61214877 A JP S61214877A JP 60056752 A JP60056752 A JP 60056752A JP 5675285 A JP5675285 A JP 5675285A JP S61214877 A JPS61214877 A JP S61214877A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- character
- circuit
- video signal
- electric potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Studio Circuits (AREA)
- Television Systems (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はビデオ信号の文字信号を挿入することができる
ビデオ信号処理装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processing device capable of inserting character signals into a video signal.
従来の技術
ビデオ信号に文字情報を挿入する場合、第4図に示すよ
うにビデオ信号aから水平同期信号すと垂直同期信号C
を分離し文字発生器3に入力して文字信号dを発生させ
ている。次に、ビデオ信号aに文字信号dを挿入する場
合、ビデオ信号色の輝度信号によってその直流電位が変
動するためにクランプ回路4によりビデオ信号aのペデ
スタル電位を第5図eに示すように0〔マ〕に固定させ
ておき、第6図に示すように加算回路6によってビデオ
信号aに文字信号dを挿入してオンスクリーン信号とし
ている。Conventional technology When inserting character information into a video signal, as shown in FIG.
is separated and input to a character generator 3 to generate a character signal d. Next, when character signal d is inserted into video signal a, the DC potential varies depending on the luminance signal of the color of the video signal, so the clamp circuit 4 sets the pedestal potential of video signal a to 0 as shown in FIG. 5e. [Ma] is fixed, and as shown in FIG. 6, a character signal d is inserted into a video signal a by an adder circuit 6 to produce an on-screen signal.
尚、第5図において、水平同期分離回路1より出力され
る水平同期信号すは、微分されて信号b1となり、信号
b1に閾値vthを設けて、時刻t、〜t2間の一定幅
をもつパルスb2を得、クランプ回路4に入力される。In FIG. 5, the horizontal synchronization signal S output from the horizontal synchronization separation circuit 1 is differentiated to become a signal b1, and a threshold value vth is provided for the signal b1 to generate a pulse with a constant width between times t and t2. b2 is obtained and input to the clamp circuit 4.
第7図(fL)および(b)に示すようにビデオ信号a
の輝度信号が+1.2〔マ〕で、文字信号dが+1.4
[:T:1である場合には両信号の輝度差が0.2[v
] であるので文字情報の解読は可能である。例えば
ビデオ信号色の輝度信号と文字信号dが共に同電位(+
1,4[マ〕)の時は第7図(C)および(d)に示す
ように文字情報の解読が困難であった。As shown in FIG. 7(fL) and (b), the video signal a
The luminance signal of is +1.2 [ma] and the character signal d is +1.4
[:T:1, the luminance difference between both signals is 0.2[v
] Therefore, it is possible to decipher the textual information. For example, the luminance signal of the video signal color and the character signal d are both at the same potential (+
1, 4 [ma]), it was difficult to decipher the character information as shown in FIGS. 7(C) and (d).
発明が解決しようとする問題点
上記問題点に鑑み本発明は、ビデオ信号の輝度信号がい
かなる電位にあフても文字情報を容易に解読できるビデ
オ信号処理装置を提供することを目的としている。Problems to be Solved by the Invention In view of the above-mentioned problems, an object of the present invention is to provide a video signal processing device that can easily decode text information no matter what potential the luminance signal of the video signal is at.
問題点を解決するだめの手段
本発明は上記問題点を解決するため、文字信号の変化点
を検出して微分パルスとし、ビデオ信号と文字信号を合
成した後に微分パルスによフて文字情報のエッヂ部分を
輝度信号の任意の電位に固定するものである。Means for Solving the Problems In order to solve the above problems, the present invention detects the change point of the character signal and uses it as a differential pulse, and after combining the video signal and the character signal, uses the differential pulse to extract the character information. The edge portion is fixed at an arbitrary potential of the luminance signal.
作用
本発明は上記した構成により、ビデオ信号の輝度信号が
所定の電位を越えると文字情報のエッヂ分の輝度を低く
抑えることにより文字の輪郭を強調させ、文字情報の解
読が容易になる。According to the above-described structure, the present invention suppresses the brightness of the edges of character information to a low level when the brightness signal of the video signal exceeds a predetermined potential, thereby emphasizing the outline of the character and making it easier to decipher the character information.
実施例
第1図は本発明のビデオ信号処理装置の一実施例を示す
ブロック図である。第1図において、1はビデオ信号a
から水平同期信号bl抽出する水平同期分離回路、2は
水平同期信号すから垂直同期信号ci油抽出る垂直同期
分離回路、3は水平同期信号すと垂直同期信号Cを入力
して映像信号期間に所定の文字信号dを発生する文字発
生器、4はビデオ信号色のペデスタル電位を例えば0〔
マ〕に固定するクランプ回路、5はペデスタル電位がO
〔マ〕に固定されたビデオ信号eに文字信号di挿入し
てオンスクリーン信号fとする加算回路、6は文字信号
dの変化点を検出して微分パルスgを発生する微分回路
、7はビデオ信号eに文字信号dが挿入されたオンスク
リーン信号fから微分パルスによって文字信号dの輪郭
部分を任意の電位に固定する減算回路である。Embodiment FIG. 1 is a block diagram showing an embodiment of the video signal processing apparatus of the present invention. In FIG. 1, 1 is a video signal a
A horizontal synchronization separation circuit extracts the horizontal synchronization signal BL from the horizontal synchronization signal, 2 a vertical synchronization separation circuit that extracts the vertical synchronization signal C from the horizontal synchronization signal, and 3 inputs the horizontal synchronization signal and the vertical synchronization signal C to the video signal period. A character generator 4 that generates a predetermined character signal d sets the pedestal potential of the video signal color to, for example, 0 [
5 is a clamp circuit that fixes the pedestal potential to O.
[Ma] is an addition circuit that inserts a character signal di into a fixed video signal e to produce an on-screen signal f; 6 is a differentiation circuit that detects a change point in the character signal d and generates a differential pulse g; 7 is a video This is a subtraction circuit that fixes the outline of the character signal d to an arbitrary potential using a differential pulse from the on-screen signal f in which the character signal d is inserted into the signal e.
微分回路6は例えば第2図に示すように論理素子で構成
され、第3図(IL)に示す微分パルスgを得る。減算
回路7は例えば第2図に示すようにトランジスタ回路で
構成され第3図(IL)に示すオンスクリーン信号fを
得る。文字信号dの輪郭部電位マは減算回路7のトラン
ジスタのコレクタ電位により任意に制御できる。The differentiating circuit 6 is composed of logic elements as shown in FIG. 2, for example, and obtains the differential pulse g shown in FIG. 3 (IL). The subtraction circuit 7 is constituted by a transistor circuit, for example, as shown in FIG. 2, and obtains the on-screen signal f shown in FIG. 3 (IL). The contour potential of the character signal d can be arbitrarily controlled by the collector potential of the transistor of the subtraction circuit 7.
まだ、本実施例においては水平方向にのみ微分パルスg
を発生させたために第3図(b)に示すように縦方向の
輪郭が強調されているが、水平同期信号の1ライン遅延
素子を用いて垂直方向の微分パルスを発生させると、第
3図(C)に示すように文字の全体に輪郭を得ることが
できる。However, in this embodiment, the differential pulse g is applied only in the horizontal direction.
As a result, the vertical contour is emphasized as shown in Figure 3(b), but if a vertical differential pulse is generated using a 1-line delay element for the horizontal synchronization signal, as shown in Figure 3(b), As shown in (C), an outline can be obtained over the entire character.
発明の効果
以上述べてきたように、本発明によればオンスクリーン
信号の文字輪郭部を任意の電位に設定することによりビ
デオ信号の映像信号電位と文字信号電位の差が小さい場
合においても、文字情報の解読が容易である。Effects of the Invention As described above, according to the present invention, by setting the character outline of the on-screen signal to an arbitrary potential, even when the difference between the video signal potential of the video signal and the character signal potential is small, the character Information is easy to decipher.
第1図は本発明の一実施例におけるビデオ信号処理装置
を示すブロック図、第2図は本発明の要部回路図、第3
図(IL)は本発明の各部の動作を示すタイムチャート
、第3図(b) 、 (C)は同画像状態を示す状態図
、第4図は従来のビデオ信号処理装置を示すブロック図
、第6図は同各部の動作を示すタイムチャート、第6図
は同装置の要部回路図、第7図(IL) 、 (0)は
従来例の各部の動作を示すタイムチャート、第7図中)
、 ((1)は同画像状態を示す状態図である。
1・・・・・・水平同期分離回路、2・・・・・・垂直
同期分離回路、3・・・・・・文字発生器、4・・・・
・・クランプ回路、5・・・・・・加算回路、6・・・
・・・微分回路、7・・・・・・減算回路。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名i1
図
、?
第2図
第3図
第4図
第50
第6図
b2 すV
第7図FIG. 1 is a block diagram showing a video signal processing device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of main parts of the present invention, and FIG.
FIG. 3(IL) is a time chart showing the operation of each part of the present invention, FIGS. 3(b) and 3(C) are state diagrams showing the same image state, and FIG. 4 is a block diagram showing a conventional video signal processing device. Fig. 6 is a time chart showing the operation of each part of the same device, Fig. 6 is a circuit diagram of the main part of the same device, Fig. 7 (IL), (0) is a time chart showing the operation of each part of the conventional example, Fig. 7 During)
, ((1) is a state diagram showing the same image state. 1...Horizontal sync separation circuit, 2...Vertical sync separation circuit, 3...Character generator , 4...
...Clamp circuit, 5... Addition circuit, 6...
...differentiation circuit, 7...subtraction circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person i1
figure,? Figure 2 Figure 3 Figure 4 Figure 50 Figure 6 b2 S V Figure 7
Claims (1)
分離回路と、水平同期信号を入力して垂直同期信号を発
生する垂直同期分離回路と、内部に発振回路を備え垂直
同期信号と水平同期信号を入力し、ビデオ信号の映像信
号期間に所定の文字信号を発生する文字発生器と、ビデ
オ信号と水平同期信号を入力しビデオ信号のペデスタル
電位を一定電位にするクランプ回路と、クランプされた
ビデオ信号に文字信号を重畳してオンスクリーン信号と
する加算回路と、文字信号の変化点で微分パルスを発生
する微分回路と、微分パルスによってオンスクリーン文
字の輪郭部電位を所定にする減算回路とを具備してなる
ビデオ信号処理装置。A horizontal synchronization separation circuit that inputs a video signal and extracts a horizontal synchronization signal, a vertical synchronization separation circuit that inputs a horizontal synchronization signal and generates a vertical synchronization signal, and an internal oscillation circuit that generates a vertical synchronization signal and a horizontal synchronization signal. a character generator that inputs the video signal and generates a predetermined character signal during the video signal period of the video signal; a clamp circuit that inputs the video signal and the horizontal synchronization signal and sets the pedestal potential of the video signal to a constant potential; An addition circuit that superimposes a character signal on a signal to produce an on-screen signal, a differentiation circuit that generates a differential pulse at a change point of the character signal, and a subtraction circuit that uses the differential pulse to set the potential of the outline of an on-screen character to a predetermined value. A video signal processing device comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60056752A JPH0614702B2 (en) | 1985-03-20 | 1985-03-20 | Video signal processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60056752A JPH0614702B2 (en) | 1985-03-20 | 1985-03-20 | Video signal processor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61214877A true JPS61214877A (en) | 1986-09-24 |
JPH0614702B2 JPH0614702B2 (en) | 1994-02-23 |
Family
ID=13036251
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60056752A Expired - Lifetime JPH0614702B2 (en) | 1985-03-20 | 1985-03-20 | Video signal processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0614702B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR960020404A (en) * | 1994-11-11 | 1996-06-17 | 김광호 | Video signal and digital character synthesis method and digital character address generator accordingly |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56106477A (en) * | 1980-01-30 | 1981-08-24 | Pioneer Video Corp | Circuit for inserting character in television screen |
-
1985
- 1985-03-20 JP JP60056752A patent/JPH0614702B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56106477A (en) * | 1980-01-30 | 1981-08-24 | Pioneer Video Corp | Circuit for inserting character in television screen |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR960020404A (en) * | 1994-11-11 | 1996-06-17 | 김광호 | Video signal and digital character synthesis method and digital character address generator accordingly |
Also Published As
Publication number | Publication date |
---|---|
JPH0614702B2 (en) | 1994-02-23 |
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