JPS61211878A - Envelope detector - Google Patents

Abstract

PURPOSE:To limit the number of parts to minimum and correctly detect an envelope for an alternating current signal of high frequency, by constituting of a comparator, a flip flop and an integrator. CONSTITUTION:A high frequency signal inputted from a high frequency signal source 9 is compared with an earth level in a comparator 12 and a clock signal is outputted as a true signal (a) and an auxiliary output (b) which are opposite to each other in phase. Accordingly, operations of S/R flip flops 17 and 18 are opposite, and output signals are opposite in phase. Synchronizing with the output (a) an up signal from a D flip flop 13 is outputted to an integrator to an integrator 14 to feed back a signal (g) to a comparator 10. In a comparator 11, a negative half cycle of the high frequency signal is compared with a feedback signal (j). An up signal from a D flip flop 15 is outputted. The signal (j) integrated in an integrator 16 coincides with a peak value of the high frequency, and an envelope of a neqative half wave of the high frequency is shown. Thus, a voltage V coinciding with an envelope of a half amplitude of the high frequency signal can be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] A signal read from a magnetic medium such as a magnetic disk device, which is an external storage device of an information processing system, contains many high frequency components and has a distorted waveform. The present invention relates to an envelope detector that continuously reads out such waveforms and detects the envelope by following up to high frequencies.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional envelope detector. 1 is an AC signal source such as a magnetic head that reads digital information from a magnetic disk device, 2.3 is a comparator, 4.5 is a flip-flop, 6 is an up/down counter, 7 is a D/A converter,
8 is an integrator.

When the AC signal from the AC signal source J is input as a comparison input signal to the comparator 2, it is compared with zero volts (earth), which is another comparison input, and when the AC signal crosses the earth level, the output of the comparator 2 at the so-called zero cross. Output is inverted.

The output of the comparator 2 is converted to a logic level by a flip-flop 4, and is sent to a terminal (A
) is output.

At the same time, the AC signal from the AC signal source 1 is also input as a comparison input to another comparator 3, and the output of the integrator 8, which is output as an envelope signal, is input to the comparator 3.
The AC signal is fed back as the other comparison input, and the two are compared to determine whether the peak value of the AC signal is larger or smaller than the fed back envelope signal.

If the output of the comparator 3 is positive when the peak value of the AC signal is smaller than the envelope signal, if the peak value of the AC signal is larger than the envelope signal, the output of the comparator 3 is inverted and becomes negative. The flip-flop 5 converts the output of the comparator 3 to a logic level, and when the output of the -1 comparator 3 is positive, it becomes a logic "
1', when it is negative, outputs logic "o" to 醔1子(B). The output signal of the flip-flow knob 5 controls the counting direction of the up/down counter 6 connected to the next stage, and when the terminal (B) is at the logic level "1°", that is, the peak value of the input AC signal. When is smaller than the envelope signal 11-, the up/down counter 6 performs an up-count operation and adds δ1 to the clock pulse output to the terminal (A). The output of the up/down counter 6 is converted into an analog value, and after being integrated with a constant time constant in an integrator 8, it is output to the terminal (C) as an envelope signal of the input AC signal, and at the same time is fed back to the comparator 3. and is successively compared with the peak value of the human AC signal.

Conversely, in the comparator 3, when the peak value of the input AC signal is larger than the envelope signal fed back from the integrator 8, the output of the flip-flop 5 is set to logic "0", and the up/down counter 6 is set to down-count operation. Count and subtract the clock pulses input from terminal (A), and calculate the digital amount subtracted from the previous level by D/A.
Output to converter 7. After being converted into an analog value by the D/Δ converter 7, it is integrated by the integrator 8, and an envelope signal whose level has decreased from the previous level is output to the terminal (C), and at the same time, it is fed back to the comparator 3 and compared with the input AC signal. , operates so that the difference disappears.

By repeating the above operations, a DC output that always follows the envelope of the input AC signal can be obtained from the output terminal (C).

[Problem that the invention seeks to solve]

In this way, the envelope detector according to the prior art is
To obtain the DC output signal corresponding to the envelope, the up/down counter 6 and the D/A converter 7 are used for digital processing. It is necessary to increase the number of bins 1 to 1 of the counter 6 and the D/converter 7, which is expensive.

Furthermore, if the frequency of the input AC signal becomes high (as the D/A converter 7 becomes difficult to follow), the frequency range is restricted by the performance of the D/A converter.

The technical problem of the present invention is to solve these problems with conventional envelope detectors, and to accurately detect envelopes even for high-frequency AC signals using an inexpensive circuit configuration with a minimum number of parts. It is about making it possible.

[Means for solving problems]

The technical measures taken by the present invention to solve this problem include: a first comparator that compares the positive peak of the high frequency signal with the feedback envelope; and a first comparator that compares the negative peak of the high frequency signal with the feedback envelope. and a third comparator that generates a clock signal from the high-frequency signal by zero crossing. The outputs of the first and second comparators are input to the flip-flops provided in the next stage, and an amplifier down pulse is generated in synchronization with the clock signal. In addition to integrating the output of the positive envelope and feeding it back to the corresponding comparator, an operational amplifier is provided in which the integral output of the positive envelope is connected to the positive input terminal, and the integral output of the negative envelope is connected to the negative input terminal, and the high-frequency signal is output from the output. The circuit configuration is such that the envelope is obtained.

[Effect]

According to this technical measure, the positive and negative envelopes fed back from each integrator and the positive and negative peaks of the input high-frequency signal are respectively compared in a comparator, and the positive envelope is lower than the peak of the input high-frequency signal. If the warpage is large, a down pulse is output, and if the warp is small to 1, an amplifier pulse is output. Further, if the negative peak is larger than the negative peak, a down pulse is applied, and if it is smaller than the negative peak, an up pulse is applied. Then, each corresponding flip-flop outputs an output to an integrator installed in the next stage, and in the case of a 7-nop pulse, the output of the integrator increases, and in the case of a down pulse, the output of the integrator decreases. As a result, positive and negative envelope voltages that follow the positive and negative peak values of the input high-frequency signal are obtained. Therefore, by inputting a positive envelope voltage to the positive input terminal of an operational amplifier and a negative envelope voltage to the negative input terminal of the operational amplifier, even if an offset voltage is superimposed on the input high frequency signal, it will not be affected by the offset voltage. It is possible to accurately detect the half-amplitude envelope of the input high-frequency signal without any interference.

〔Example〕

Next, how the envelope detector according to the present invention is actually implemented will be explained using examples. FIG. 1 is a circuit diagram showing an embodiment of an envelope detector according to the present invention. 9 is a high frequency signal source such as a read signal from a floppy disk device; 10 is a comparator that compares the positive peak value of the high frequency signal with the envelope;
1 is a comparator that compares the negative peak value of the high frequency signal with the envelope, and 12 is a comparator for creating a clock signal from the high frequency signal by zero crossing.

13 and 14 are flip-flops and integrators for generating an amplifier down pulse for positive envelope detection, and I5 and 16 are flip-flops and integrators for negative envelope detection. 17.18
19 is a flip-flop for generating a clock signal for timing the comparison, and 19 is an operational amplifier.

The high-frequency signal input from the high-frequency signal source 9 is first compared with the ground level in the comparator 12, and when the high-frequency signal crosses the ground level, the output is inverted. The true output a and the complementary output s are output. true output a
Output signal line number: 1, 5-11 Frisopf 11 knob provided in the next stage 170) S input terminal and R input terminal of S-R flip-flop 1B, D flip-flop 1
It is connected to one clock signal product of No. 3. Further, the output signal line of the auxiliary output is connected to the R input terminal of the S-R flip-flop 17, the S input terminal of the S-R flip-flop 18, and 1) the clock signal terminal of the flip-flop 15. Therefore, the operations of these S/R flip-flops 17 and 18 are opposite, and the output signals C and d have opposite phases.

At the same time, the high frequency signal is input from the high frequency signal source 9.
is input to the positive input terminal of the comparator 10, and the integrator I4
The output signal g of the comparator 10 is fed back to the negative input terminal of the comparator 10, and the two are compared. At this time, the output signal d of the 5-17 flip-flop 18 is input to the enable terminal e of the comparator 10, and the comparator 10 is made to function for a half period of logic "1" of the clock signal, and for a half period of logic "0" of the clock signal. stop that function. In other words, since the period of the high frequency signal from the high frequency signal source 9 and the period of the clock signal are the same, the comparator 10 uses the feedback signal g of the integrator 14 only for the positive half period of the high frequency signal.
compared to

If the peak value of the high-frequency signal is now lower than the feedback signal g, the output signal f from the comparator 10 becomes positive and is output to the D flip-flop 13, and the true output a from the comparator 12 is used as a clock signal to output the output a. An amplifier signal is outputted from the D flip-flop 13 to the integrator I4 in synchronization with the D flip-flop 13. The integrator 14 integrates the amplifier signal,
The output signal g is increased, fed back to the comparator 10, and compared again with the high frequency signal. Conversely, if the peak value of the high frequency signal is greater than the feedback signal g, the comparator 1
The output signal f of 0 becomes negative, and the D flip-flop 13 outputs a down signal, which is integrated by the integrator 14 and acts to lower the output signal g. By repeating the above operations, the output signal g will show a positive half-wave envelope of the high frequency signal. , With a configuration and operation similar to those described above, the S/R flip-flop The output C of the amplifier 17 is connected to the enable terminal of the comparator 11. Therefore, the comparator 11 functions when the output C is logic "1" and stops its function when the output C is logic "0". However, since the output C is inverted in phase to the output d, the comparator 11 performs a comparison operation with the feedback signal j for the negative half cycle of the high frequency signal.

The input terminals of the high frequency signal and the feedback signal j in the comparator 11 are connected in the opposite way to those of the comparator 10, so when the feedback signal is larger than the high frequency signal (that is, the absolute value G is smaller), the output signal i is It is output to the D flip-flop 15 as D flip-flop 1
5, the signal i is transferred to the output of the comparator 12 in synchronization with the complementary output of the comparator 12, but since the output is taken out from the inverted terminal compared to the case of the D flip-flop 13, the signal i is not positive. Regardless, the output from flip-flop 15 becomes the down signal at flip-flop 13. The integrator 16 attempts to integrate the down signal and lower its output signal j. Conversely, if the high frequency signal is smaller than the feedback signal, the up signal is output from the D flip-flop 15 and integrated by the integrator 16, and the output signal j is equal to the peak value of the high frequency signal, similar to the operation described above. It is meant to represent the negative half-wave envelope of the high-frequency signal.

Although the positive and negative waveforms of a high frequency signal are generally symmetrical and the absolute values of their envelopes are the same, the zero level may be offset, resulting in imbalance.

Therefore, the positive envelope signal g is sent to the negative input terminal of the operational amplifier 19, and the negative envelope signal j is sent to the operational amplifier 1.
Connect to the positive input terminal m of 9. Now the offset voltage Vo
The voltage of the envelope signal g to which ff is added is V + Vof
f, the voltage of the envelope signal j is −V+Vof
f, the output voltage of the operational amplifier 19 is Vout, the resistance value of the resistor 20.21 is 20 kΩ, and the resistance of the resistor 22.23 is =
13= If the resistance value is 10 kΩ, the potential at the negative input k is (V+Voff)/3. The operational amplifier has the function of equalizing the potentials of the negative input terminal and the positive input terminal, and the potentials of the negative input terminal and the positive input terminal m are equal. Therefore, if the current flowing through the resistor 22 is ■, then 10 T = Vout
−(V −1−Voff) /320 r =4V/3
-2 From Voff/3 or more, I = V/15-
Voff/3010 (V/15-Voff/30)
−Vout−(V+Voff) /3 Therefore, Vou
t=V From this, it is possible to detect the output voltage Vout of the operational amplifier 19 as the voltage V that matches the envelope of the half amplitude of the high frequency signal, regardless of the presence or absence of the offset voltage Voff.

〔Effect of the invention〕

As described above, according to the present invention, the envelope of a high-frequency signal is detected by using a comparator, a flip-flop, and an integrator without using an amplifier down counter or a D/A converter, thereby minimizing the number of components. This can be realized with an inexpensive circuit configuration, and the limit of the response frequency can be increased.

Furthermore, by providing an operational amplifier with a positive envelope signal connected to its negative input and a negative envelope signal connected to its positive input, the envelope of the high-frequency signal can be accurately detected regardless of the presence or absence of an offset voltage with respect to the high-frequency signal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an envelope detector according to the present invention, and FIG. 2 is a block diagram showing a conventional envelope detector. In the figure, 1.9 is a high frequency signal source, 2.3.10.11
．． 12 is a comparator, 4.5.13.15.17.1
8 is a flip-flop, 8.14.16 is an integrator, 19
indicate operational amplifiers, respectively.

Claims (1)

[Claims] A first comparator that compares the positive peak of the high frequency signal with the feedback envelope, and a second comparator that compares the negative peak of the high frequency signal with the feedback envelope.
and a third comparator that generates a clock signal by zero crossing from the high-frequency signal, and generates true and complementary clock signals having opposite phases to each other to operate the first and second comparators alternately. The outputs of the first and second comparators are input to the flip-flops provided in the next stage, and up-down pulses are generated in synchronization with the clock signal.The outputs are integrated by the integrating circuit provided after each flip-flop. In addition to feeding back to the corresponding comparator, an operational amplifier is provided in which the integral output of the positive envelope is connected to the positive input terminal and the integral output of the negative envelope is connected to the negative input terminal, and the circuit configuration is to obtain the envelope of the high frequency signal from the output. envelope detector.