JPS61211715A - Small electronic equipment with solar battery - Google Patents

Small electronic equipment with solar battery

Info

Publication number
JPS61211715A
JPS61211715A JP60052391A JP5239185A JPS61211715A JP S61211715 A JPS61211715 A JP S61211715A JP 60052391 A JP60052391 A JP 60052391A JP 5239185 A JP5239185 A JP 5239185A JP S61211715 A JPS61211715 A JP S61211715A
Authority
JP
Japan
Prior art keywords
circuit
capacitor
voltage
solar battery
charging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60052391A
Other languages
Japanese (ja)
Inventor
Haruo Ono
治夫 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP60052391A priority Critical patent/JPS61211715A/en
Publication of JPS61211715A publication Critical patent/JPS61211715A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/66Regulating electric power
    • G05F1/67Regulating electric power to the maximum power available from a generator, e.g. from solar cell
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/56Power conversion systems, e.g. maximum power point trackers

Landscapes

  • Engineering & Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Sustainable Energy (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

PURPOSE:To enable to execute normal operation at once by providing a resistance component between a solar battery and a capacitor, controlling to make resistance value large at the time of starting charging to the capacitor and stabilizing output voltage at a connecting point of the solar battery and resistance component to voltage for driving electronic circuit. CONSTITUTION:A charging circuit in which charging current flows from a solar battery 1 to a capacitor 2 is formed, and a reverse current preventing diode 3 that prevents loss current is provided. An N type MOS transistor 4 is used as a load, and the resistance value is variably controlled according to output of an operational amplifier 5 applied to the gate, and constitutes a quick starting circuit 6 that quick starts an electronic circuit 11 at the time of starting charging. Output voltage VIN from the connecting point of the solar battery 1 and N type MOS transistor 4 is applied to minus input terminal of an operational amplifier 9 that constitutes a voltage regulator circuit 8 through a P type MOS transistor 10 of insulating gate depression type. The voltage regulator circuit 8 stabilizes driving voltage supplied to the electronic circuit 11.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、太陽電池を電源とする太陽電池付小型電子
機器に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a small electronic device with a solar cell that uses a solar cell as a power source.

〔従来技術およびその問題点〕[Prior art and its problems]

従来、太陽電池を小型電子機器に使用する場合、太陽電
池に対して並列接続されたコンデンサを設け1.太陽電
池の起電力でコンデンサを充電し、コンデンサの両端に
かかる電圧で電子回路を駆動している。ここで、例えば
、太陽電池付小型電子機器として車上電子計算機(電卓
)を考えた場合、電卓は一般に明るい場所で常に使用さ
れるものであるため、元来、光により常時コンデンサを
充電できるため、コンデンサ容量は小さなものであって
も良い。これに対し、電子腕時計のような場合、夜間の
ようOこ光が当らない時でも駆動させなければならない
為、容量の大きなコンデンサを使用しなければならない
。しかしながら、コンデンサ容量を大きくした場合、コ
ンデンサが完全に放電してしまうと、再充電するのに時
間がかかり、すぐに計時動作を行なえないという難点が
あった。
Conventionally, when solar cells are used in small electronic devices, a capacitor is connected in parallel to the solar cells.1. The electromotive force from the solar cell charges the capacitor, and the voltage across the capacitor drives the electronic circuit. For example, if we consider an on-board electronic calculator (calculator) as a small electronic device with a solar battery, since calculators are generally used in bright places, the capacitor can be constantly charged by light. , the capacitor capacity may be small. On the other hand, in the case of an electronic wristwatch, a capacitor with a large capacity must be used because it must be driven even when there is no light, such as at night. However, when the capacitor capacity is increased, there is a problem in that once the capacitor is completely discharged, it takes time to recharge, making it impossible to perform a timekeeping operation immediately.

〔発明の目的〕[Purpose of the invention]

この発明は、上述した事情を背景になされたもので、そ
の目的とするところは、コンデンサの充電開始時に電子
回路の正常動作を即座に実行可能であると共に回路構成
の簡略化を図った太陽電池付小型電子機器を提供するこ
とにある。
This invention was made against the background of the above-mentioned circumstances, and its purpose is to provide a solar cell that can immediately perform normal operation of an electronic circuit when charging a capacitor starts, and that also has a simplified circuit configuration. Our goal is to provide small electronic devices with attached devices.

〔発明の要点〕[Key points of the invention]

この発明は、上述した目的を達成するために、太陽電池
の出力電圧で充電されるコンデンサを備えた太陽電池付
小型電子機器において、太陽電池とコンデンサとの間に
抵抗成分を設け、かつコンデンサへの充電開始時に前記
抵抗成分の抵抗値が大きくなるように制御する制御回路
および太@電池と抵抗成分との接続点の出力電圧を電子
回路駆動用電圧に安定化する電源安定化回路を設け、こ
れら制御回路および電源安定化回路に共用される基準電
圧発生回路を設けた点を要旨とするものである。
In order to achieve the above-mentioned object, the present invention provides a small electronic device with a solar cell equipped with a capacitor that is charged with the output voltage of the solar cell, in which a resistance component is provided between the solar cell and the capacitor, and a resistance component is provided between the solar cell and the capacitor. a control circuit that controls the resistance value of the resistance component to increase at the start of charging, and a power supply stabilization circuit that stabilizes the output voltage at the connection point between the thick battery and the resistance component to a voltage for driving the electronic circuit; The main point is that a reference voltage generation circuit is provided which is shared by these control circuits and power supply stabilization circuits.

〔実施例の構成〕[Configuration of Example]

以下、この発明を図面に示す一実施例に基づいて具体的
に説明する。第1図はこの発明を電子時計に適用した電
源部のブロック回路図である。図中1は、例えば、最大
起電力が−3,5Vの太陽電池で、この太@m池1には
大容五ノコンデンサ2が並列接続され、太陽電池1から
コンデンサ2に充電電流が流れる充電回路が形成されて
いる。この充電回路中には太陽電池1の電位がコンデン
サ2より低いときにコンデンサ2から太陽電池1に流れ
るロス電流を防止する逆流防止ダイオード3が設けられ
ている。また、太陽電池1とコンデンサ2との間にはN
型MOS)ランジスタ4が設けられ、このN型MO’S
)ランジスタ4のドレイン側はコンデンサ2、ソース佃
は太@電池1に接続されている。このN型MOS)ラン
ジスタ4は負荷として使用され、そのゲートに印加され
るオペアンプ5の出力に応じてその抵抗値が可変制御さ
れるよう6口なっている。しかして、N型MOS)ラン
ジスタ4およびオペアンプ5は、電子回路11を充電開
始にクイックスタートさせるグイツクスタート回路6を
構成する。そして、オペアンプ5はそのマイナス入力端
子に太陽電池1とN型MOSトランジスタ4の接続点か
らの出力電圧VINが被比較′電圧として印加され、ま
たそのプラス入力端子には基準電圧発生回路7から基準
電圧vr6、が印加され、両軍圧を比較した結果、信号
■Out を出力してN型MOSトランジスタ4のゲー
トに印加する。
Hereinafter, the present invention will be specifically described based on an embodiment shown in the drawings. FIG. 1 is a block circuit diagram of a power supply section in which the present invention is applied to an electronic timepiece. 1 in the figure is, for example, a solar cell with a maximum electromotive force of -3.5V, and a large-capacity five-capacitor 2 is connected in parallel to this thick @m pond 1, and a charging current flows from the solar cell 1 to the capacitor 2. A charging circuit is formed. This charging circuit is provided with a backflow prevention diode 3 that prevents loss current from flowing from the capacitor 2 to the solar cell 1 when the potential of the solar cell 1 is lower than that of the capacitor 2. Also, there is N between the solar cell 1 and the capacitor 2.
type MOS) transistor 4 is provided, and this N type MO'S
) The drain side of the transistor 4 is connected to the capacitor 2, and the source side is connected to the battery 1. This N-type MOS) transistor 4 is used as a load, and has six ports so that its resistance value can be variably controlled in accordance with the output of the operational amplifier 5 applied to its gate. Thus, the N-type MOS transistor 4 and the operational amplifier 5 constitute a quick start circuit 6 that quickly starts the electronic circuit 11 to start charging. The output voltage VIN from the connection point between the solar cell 1 and the N-type MOS transistor 4 is applied to the negative input terminal of the operational amplifier 5 as a voltage to be compared, and the reference voltage generation circuit 7 supplies the reference voltage to the positive input terminal of the operational amplifier 5. A voltage vr6 is applied, and as a result of comparing both voltages, a signal -Out is output and applied to the gate of the N-type MOS transistor 4.

基準電圧発生回路7は上記クイックスタート回路6に基
準電圧vro、を入力する他、ボルテージレギュレータ
回路8を構成するオペアンプ9のプラス入力端子(こ入
力する。このボルテージレギュレータ回路8を構成する
オペアンプ9のマイナス入力端子には太陽電池1とN型
MOS)ランジスタ4の接続点からの出力電圧■エヨが
絶縁ゲートデプレッション形のP型MO8)ランジスタ
10を介して印加され、そしてこのオペアンプ9から出
力される2値レベルの信号は上記P型MOSトランジス
タ10のゲートに印加される。しかして、ボルテージレ
ギュレータ回路8は電子回路(負荷)11に供給される
駆動電圧を安定化するもので、この電子回路11は時計
回路を構成し、ボルテージレギュレータ回路8からの駆
動電圧にしたがって計時動作を実行する。
In addition to inputting the reference voltage vro to the quick start circuit 6, the reference voltage generation circuit 7 also inputs the reference voltage vro to the positive input terminal of the operational amplifier 9 constituting the voltage regulator circuit 8. The output voltage from the connection point between the solar cell 1 and the N-type MOS transistor 4 is applied to the negative input terminal via the insulated gate depression type P-type MOS transistor 10, and is output from the operational amplifier 9. A binary level signal is applied to the gate of the P-type MOS transistor 10. Therefore, the voltage regulator circuit 8 stabilizes the driving voltage supplied to the electronic circuit (load) 11, and this electronic circuit 11 constitutes a clock circuit, and performs a timekeeping operation according to the driving voltage from the voltage regulator circuit 8. Execute.

第2図は、上記第1図のブロック回路図を詳細に示した
もので、クイックスタート回路8を構成するオペアンプ
5、基準電圧発生回路7、ボルテージレギュレータ回路
8を構成するオペアンプ9は、複数のN型MOS)ラン
ジスタとP型MQSトランジスタとを組合せてなるMO
8IOによる回路構成で、負荷MO8を設けた通常の構
成となっている。ここで、基準電圧発生回路7を構成す
る各MO8)ランジスタフ−1〜7−4のうち、MOS
)ランジスタフ−2と7−4とのドレインが共通接続さ
れている接続点からは基準電圧Vr6fが出力され、ク
イックスタート回路6のオペアンプ5を構成する各MO
8)ランジスタ5−1〜5〜7のうち、MOSトランジ
スタ5−3のゲートに印加され、また、MOS)ランジ
スタ5−5〜5−7のソースには電圧■0、が印加され
ている。一方、基M電圧発生回路6からの基準電圧■r
 6 fは、ボルテージレギュレータ回路8のオペアン
プ9を構成する各MO8)ランジスタ9−1〜9−7の
うち、MC)S)ランジスタ9−3のゲートに印加され
ている。
FIG. 2 shows in detail the block circuit diagram of FIG. MO consisting of a combination of an N-type MOS) transistor and a P-type MQS transistor
It has a circuit configuration using 8IO, and has a normal configuration with a load MO8. Here, among each MO8) Langisthu-1 to 7-4 constituting the reference voltage generation circuit 7, the MOS
) Reference voltage Vr6f is output from the connection point where the drains of Ranjistaf-2 and 7-4 are commonly connected, and each MO
8) Among the transistors 5-1 to 5-7, a voltage ``0'' is applied to the gate of the MOS transistor 5-3, and to the sources of the MOS transistors 5-5 to 5-7. On the other hand, the reference voltage ■r from the base M voltage generation circuit 6
6f is applied to the gate of the MC)S) transistor 9-3 among the MO8) transistors 9-1 to 9-7 constituting the operational amplifier 9 of the voltage regulator circuit 8.

〔実施例の動作〕[Operation of the embodiment]

第3図(a)、(b)は動作原理を説明する為の図で、
第3 m (a)はコンデンサ2に対する充電開始時、
第3図(b)は完全に充電された状態に対応している。
Figures 3 (a) and (b) are diagrams for explaining the operating principle.
3rd m (a) is when charging starts to capacitor 2,
FIG. 3(b) corresponds to a fully charged state.

いま、太陽電池1に光が照射されていない状態ではコン
デンサ2の放電が進み、そしてコンデンサ2が完全に放
電されている状態で太陽電池1に光を照射すると、太陽
電池1から起電力■B8が生ずる。ここで、コンデンサ
20二対する充電開始時にはコンデンサ2の両端の電位
差VDD−v。
Now, when the solar cell 1 is not irradiated with light, the discharge of the capacitor 2 progresses, and when the solar cell 1 is irradiated with light while the capacitor 2 is completely discharged, the electromotive force from the solar cell 1 ■B8 occurs. Here, at the start of charging the capacitor 202, the potential difference between both ends of the capacitor 2 is VDD-v.

は小さいので、v   −■  の電位差〉V工r θ
 f      DD N−VDDの電位差となる。ここで、vrefとvI、
Aは実際、負の電圧であるので、電位は■。
is small, so the potential difference of v − ■ 〉V r θ
The potential difference is f DD N-VDD. Here, vref and vI,
Since A is actually a negative voltage, the potential is ■.

ef<■INとなるが、VDD(こ対する電位差4こつ
いては、Vr e f  ’ D D > vI N 
 ’ D D  となる。この結果、クイックスタート
回路6を構成するオペアンプ5からはV  十IR=V
r、となるように所定の電圧をコンデンサ2に直列接続
されているN型MO8)ランジスタ4のゲートに与えて
N型MO8)ランジスタ4の抵抗、電流を制御する。こ
の場合、N型MO8)ランジスタ4のON抵抗は大きく
なり、流れる電流は少なくなるので、N型M08トラン
ジスタ4のソースとVDDとの電位差は大となり、N型
MO8)ランジスタ4のソースの電圧がボルテージレギ
ュレータ8を介して電子回路11【こ供給されるので、
充電開始後、すぐに電子回路11を動作させることがで
きる、(第3図(a)参照)。
ef<■IN, but VDD (if there is a potential difference of 4, then Vr e f' DD > vI N
' DD becomes. As a result, the operational amplifier 5 configuring the quick start circuit 6 outputs V +IR=V
A predetermined voltage is applied to the gate of the N-type MO transistor 4 connected in series to the capacitor 2 so that the resistance and current of the N-type MO transistor 4 are controlled so that the voltage becomes r. In this case, the ON resistance of the N-type MO8) transistor 4 increases and the flowing current decreases, so the potential difference between the source of the N-type M08 transistor 4 and VDD becomes large, and the voltage at the source of the N-type MO8) transistor 4 increases. The electronic circuit 11 is supplied via the voltage regulator 8, so
The electronic circuit 11 can be operated immediately after charging starts (see FIG. 3(a)).

しかして、コンデンサ2が完全に充電されてコンデンサ
2の両端の電位差vDD−Voの電位差が大きくなり、
vr8f−VDDの電位差<VIN’DDの電位差とな
ると、オペアンプ5の出力に応じてN型M’O8)ラン
ジスタ4が完全(こON状態となり、第3図(b)に示
すような回路構成と成り、N型MO8)ランジスタ4に
よる電圧降下がなくなる。
As a result, the capacitor 2 is completely charged and the potential difference vDD-Vo between both ends of the capacitor 2 becomes large.
When the potential difference of vr8f-VDD becomes less than the potential difference of VIN'DD, the N-type M'O8) transistor 4 becomes completely turned on according to the output of the operational amplifier 5, and the circuit configuration as shown in FIG. 3(b) is established. Therefore, the voltage drop caused by the N-type MO transistor 4 is eliminated.

このようにコンデンサ2が完全に放電されている状態で
太陽電池1に光が照射される充電の開始時であっても、
所定の電圧を電子回路11に供給できるので、充電開始
と共に電子回路11の正常動作を保障することができる
。また、単一の基準電圧発生回路7からの基準電圧V 
  をタイツr θ f クスタート回路6およびボルテージレギュレータ8に夫
々供給する構成であるので、即ち、基準電圧発生回路7
を共用する構成であるので、回路構成を簡素化すること
ができる。
Even at the start of charging when the solar cell 1 is irradiated with light while the capacitor 2 is completely discharged,
Since a predetermined voltage can be supplied to the electronic circuit 11, normal operation of the electronic circuit 11 can be ensured at the start of charging. Further, the reference voltage V from the single reference voltage generation circuit 7
Since the configuration is such that the tights r θ f are supplied to the start circuit 6 and the voltage regulator 8, respectively, that is, the reference voltage generating circuit 7
Since the configuration is such that the circuit configuration is shared, the circuit configuration can be simplified.

なお、この発明は上記実施例に限定されず、この発明を
逸脱しない範囲内において細々変形応用可能である。
It should be noted that the present invention is not limited to the above-mentioned embodiments, and may be modified and applied without departing from the scope of the present invention.

〔発明の効果〕〔Effect of the invention〕

この発明は以上詳細に説明したように、太陽電池の出力
電圧で充電されるコンデンサを備えた太陽電池付小型電
子機器において、太陽電池とコンデンサとの間に抵抗成
分を設け、かつこの抵抗成分のこの抵抗値がコンデンサ
への充電開始時に大きくなるように制御する制御回路と
、太11!池と抵抗成分との接続点の出力電圧を電子回
路駆動用電圧に安定化する電源安定化回路を設け、これ
ら制御回路および電源安定化回路に単一の基準電圧発生
回路の出力を供給して基準電圧発生回路を共用するよう
にしたから、コンデンサの充電開始時に電子回路の正常
動作を即座に実行可能となると共に、回路構成の簡略化
が可能となる。
As explained in detail above, the present invention provides a small electronic device with a solar cell equipped with a capacitor that is charged with the output voltage of the solar cell, in which a resistance component is provided between the solar cell and the capacitor, and this resistance component is A control circuit that controls this resistance value to increase when charging starts to the capacitor, and a 11! A power supply stabilization circuit is provided to stabilize the output voltage at the connection point between the battery and the resistance component to a voltage for driving the electronic circuit, and the output of a single reference voltage generation circuit is supplied to these control circuits and the power supply stabilization circuit. Since the reference voltage generating circuit is shared, the electronic circuit can immediately operate normally when the capacitor starts charging, and the circuit configuration can be simplified.

【図面の簡単な説明】[Brief explanation of drawings]

図面はこの発明の一実施例を示し、第1図はブロック回
路図、第2図は詳細な回路構成図、第3図’(a)、(
b)は動作原理を示した図である。 1・・・・・・太陽電池、2・・・・・・コンデンサ、
4・・・・・・N型MO8)ランジスタ、5・・・・・
・オペアンプ、8・・・・・・ボルテージレギュレータ
回路、11・・・・・・電子回路。 特許出願人 カシオ計算機株式会社 1、’i、 ;、’、::’、’;、、L刀第1図
The drawings show an embodiment of the present invention; FIG. 1 is a block circuit diagram, FIG. 2 is a detailed circuit configuration diagram, and FIG. 3'(a), (
b) is a diagram showing the operating principle. 1...Solar cell, 2...Capacitor,
4...N-type MO8) transistor, 5...
- Operational amplifier, 8...Voltage regulator circuit, 11...Electronic circuit. Patent applicant Casio Computer Co., Ltd. 1, 'i, ;, ', ::', ';, L sword Figure 1

Claims (1)

【特許請求の範囲】[Claims] 太陽電池と、この太陽電池の出力電圧で充電されるコン
デンサと、前記太陽電池とコンデンサとの間に設けられ
た抵抗成分と、基準電圧発生回路と、この基準電圧発生
回路の出力と前記コンデンサの出力とを比較して前記抵
抗成分の抵抗値を可変制御する制御回路と、前記基準電
圧発生回路の出力に基づいて前記太陽電池と前記抵抗成
分との接続点の出力電圧を電子回路駆動用電圧に安定化
する電源安定化回路とを具備してなる太陽電池付小型電
子機器。
A solar cell, a capacitor charged with the output voltage of the solar cell, a resistance component provided between the solar cell and the capacitor, a reference voltage generation circuit, and an output voltage of the reference voltage generation circuit and the capacitor. a control circuit that variably controls the resistance value of the resistance component by comparing the output with the output; and an output voltage at the connection point between the solar cell and the resistance component based on the output of the reference voltage generation circuit as a voltage for driving an electronic circuit. A small electronic device with a solar battery equipped with a power supply stabilization circuit that stabilizes the power supply.
JP60052391A 1985-03-18 1985-03-18 Small electronic equipment with solar battery Pending JPS61211715A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60052391A JPS61211715A (en) 1985-03-18 1985-03-18 Small electronic equipment with solar battery

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60052391A JPS61211715A (en) 1985-03-18 1985-03-18 Small electronic equipment with solar battery

Publications (1)

Publication Number Publication Date
JPS61211715A true JPS61211715A (en) 1986-09-19

Family

ID=12913501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60052391A Pending JPS61211715A (en) 1985-03-18 1985-03-18 Small electronic equipment with solar battery

Country Status (1)

Country Link
JP (1) JPS61211715A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6355176U (en) * 1986-09-30 1988-04-13
US7288450B1 (en) 1991-12-31 2007-10-30 Stmicroelectronics S.A. General protection of an integrated circuit against permant overloads and electrostatic discharges

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6355176U (en) * 1986-09-30 1988-04-13
US7288450B1 (en) 1991-12-31 2007-10-30 Stmicroelectronics S.A. General protection of an integrated circuit against permant overloads and electrostatic discharges

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