JPS61210963A - Logic analyzer device - Google Patents

Abstract

PURPOSE:To allow an investigator to recognize properly a signal having an unstable logical state by comparing and discriminating an input signal with two high and low thresholds. CONSTITUTION:By setting a signal level indicating switch 2, a threshold circuit 11 generates a high level threshold signal and a low level one and transmits them to a probe 3. It compares the input signal with high and low level threshold signals and stores the discriminated signals in a high level memory 12 and a low level memory 13, respectively, by setting a memory clock switch 4. In order to investigate the logical state of a device to be tested, the probe 3 is set, and a clock period to be stored is also set by the memory clock switch 4, after which the logical signal level is set. Then the levels of signals, which are inputted to the preset probe when the device to be tested operates, are discriminated by their thresholds, and stored in the signal level memory circuits 12 and 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to input signal discrimination of a logic analyzer device, and particularly to discrimination of a logic level using two threshold values.

[Conventional technology]

Conventionally, this type of device has a signal level indicating switch that allows
one signal level threshold value (e.g., TTL
The input signal level was determined as 1 or 0 based on the input signal level (-+1.4V), and was stored in the memory using the set storage clock.

[Problem that the invention seeks to solve]

Therefore, in the above-mentioned state, when the input signal level is unstable, for example, when the package constituting the device under test is in an open state due to a broken pattern, or in a high impedance state due to the characteristics of the elements constituting the package, Since the state is sampled using a memory clock, there is a drawback that it may be mistakenly recognized as a normal signal level.

The present invention provides a device that solves the above-mentioned problems. [Means for solving the problems] The logic analyzer device of the present invention has a signal level indicating switch that allows a high-level threshold signal and a low-level threshold signal to be set. A probe that has a built-in threshold circuit that generates signals and sends each signal to the probe, a comparator that compares and discriminates the input signal with high and low level threshold signals, and a circuit that transfers the discriminated signals to memory. The present invention is characterized in that it has a high signal level memory and a low signal level memory that respectively store probe outputs according to a set storage clock.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit constituting a logic analyzer device 1 according to the present invention. The signal level indication switch 2 is a switch that is set according to the logic signal level of the device under test, and the setting indication line 2 causes the threshold circuit 11 to switch between the high level threshold signal line 22 and the low level threshold signal line. 23 set the threshold voltage value, and the probe 3 that receives the signal compares the signal level input from the input terminal line 24 set in the device under test with the preset threshold voltage value 22.23. Then, each discrimination result is sent to the high level input signal line 2.
A memory circuit 12 for a high signal level and a memory circuit 13 for a low signal level are connected to each other by a clock value line 27 set by a storage clock switch 4 via a low level input signal line 26 and a memory circuit 12 for a high signal level.
and display each stored result on the display tube through the display line section. By setting the probe 3 to investigate the logic state of the device under test, setting the clock cycle to be memorized with the memory clock switch 4, and setting the logic signal level, the existing state when the device under test operates is set. The signal levels input to the setting probes are determined according to their respective threshold values and stored in the memory circuits 12 and 13 for each signal level. The conditions for stopping memory and the points to be displayed are the same as in conventional logic analyzers, so
It is omitted here.

〔Effect of the invention〕

As described above, the present invention has the effect of preventing an investigator from misrecognizing a signal with an unstable logic state by comparing and determining input signals using two threshold values, high and low.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. l...Logic analyzer device, 2...Signal level indication switch, 3...Probe, 4...Memory clock switch, 11...Threshold circuit', 1
2...Memory circuit for high signal level, 13...Memory circuit for low signal level, 21...Setting instruction line, n...
High level threshold signal line, 23...Low level threshold signal line, 24...Input terminal line,
25...High level input signal line, 26...Low level input signal line, 27...Clock value line, 28...Display line

Claims (1)

[Claims] (1) The logic state of the input signal is set to 1 or 0 by the signal level threshold specified by the signal level indication switch.
In a logic analyzer device, the signal is synchronized with a preset stored clock, stored in a storage memory, and the status is displayed on a display tube as a timing chart or hexadecimal code. A threshold circuit that generates a high level threshold signal and a low level threshold signal using a level indication switch and sends each signal to a probe, and a comparator and a discriminator that compare and discriminate the input signal with the high and low level threshold signals respectively. Logic characterized in that it has a probe that has a built-in circuit that transfers the output signal to the memory, and a high signal level memory and a low signal level memory that respectively store the probe output according to a set storage clock. Analyzer equipment.