JPS6121027B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention provides a conference call that allows effective and flexible conference calls by dynamically setting conference groups and the number of conference participants between a plurality of conference participants connected by a time division digital exchange. Regarding the method. In recent years, the demand for conference calls using multiple telephones has increased. Conventionally, this type of conference call system has generally configured a transmitting highway and a receiving highway in a time-division manner, and performs conference calculations on the call signals on the receiving highway and sends them out via the transmitting highway at respective predetermined time slots. was. However, in this type of conventional system,
It is very difficult to dynamically and flexibly determine the number of conference groups and conference participants, and furthermore, it requires a fairly large and expensive conference processing device. For this reason, it was very difficult to apply it to the current exchange control system. The present invention has been made in consideration of these circumstances, and its purpose is to provide flexible conference formats, enable effective conference calls with simple control, and simplify the use of the device. Another object of the present invention is to provide a conference call system that can be realized at low cost. An embodiment of the method of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram of a conference call device to which the same system is applied. Call signals from a plurality of telephones (not shown) are inputted via the receiving highway 1 in a time-division manner. Further, the call signal (conference signal) subjected to conference calculation processing by this device is sent out in a time-division manner via the transmission highway 2, and is supplied to each of the above-mentioned telephones. The receiving highway 1 and the sending highway 2
The data format of the call signal sent to the telephone is a one-frame n-channel time-division signal sequence, as shown in Figure 2a and b, respectively, and each telephone transmits the call signal in its assigned time slot. Sending and receiving. The telephone device is composed of two buffer memories 4 and 5 which are switched every frame by switches 3a and 3b, and a conference calculation circuit 6. That is, the buffer memories 4 and 5 have a double buffer configuration, and when the buffer memory 4 is connected to the highways 1 and 2 by the switches 3a and 3b, the buffer memory 5 is connected to the conference calculation circuit 6 by the switches 3c and 3d. It's becoming like that. Conversely, when the buffer memory 5 is connected to the highways 1 and 2, the buffer memory 4 is connected to the conference calculation circuit 6. However, the conference calculation circuit 6
Conference calculation processing is performed on one frame of a call signal that is not involved in transmission and reception with the telephone. Transmission and reception of call signals to and from the telephone set and conference calculation processing of the call signals are controlled by various control signals supplied from a frame counter 7, a highway channel counter 8, and an oscillator 9. Thus, according to such a device with a double buffer configuration, call signals from a plurality of telephones are written over one frame in one buffer memory 4, 5 by address designation by the highway channel counter 8. At the same time, from the buffer memories 4 and 5, one frame of the previous call signal, which has been subjected to conference arithmetic processing and rewritten, is read out over one frame and sent to each of the telephones. In addition, at this time, the call signal written in the buffer memories 5 and 4 one frame before is still stored in the highway channel counter 8.
The address is designated by a signal determined based on the address information of , and is supplied to the conference calculation circuit 6 over one frame, where conference calculation processing is performed.
The conference call signal obtained by the conference calculation process is rewritten into the buffer memories 5 and 4, and sent to the telephone set in the next frame. Now, the conference calculation circuit 6 is configured as shown in FIG. 3, for example. Incidentally, FIG. 3 shows a case where the call signal stored in the buffer memory 4 is used for conference calculation processing, and here the switch 3a,
3b, 3c, and 3d are omitted. As explained above, the connection switching between the buffer memories 4 and 5 is performed by the frame counter 7, and this switching control will be explained later. Buffer memories 4 and 5 are each address selector 1
1 and 12, or the output of the conference control memory 13. This conference control memory 13 is addressed by the output of the highway channel counter 8 which is input via an address conversion circuit 14. This address conversion will be explained later with reference to FIG. But here,
The buffer memory 5 is addressed by the output of the highway channel counter 5, and the buffer memory 4 is addressed by the output data of the conference control memory 13. The conference control memory 13 scans the buffer memory 4 twice in succession for each conference group during a period in which one frame of conversation signals is transmitted and received in the buffer memory 5, and sequentially reads out the stored conversation signals. The speech signal stored in the buffer memory 4 is generally a compressed code, and is therefore linearly converted via the decompression circuit 15. This linearly converted speech signal is input to the addition/subtraction circuit 16,
Addition processing or subtraction processing is performed according to the conference calculation control signal supplied from the address conversion circuit 14. This calculation output signal is supplied to the accumulator 17, and is subjected to signal processing in response to control signals such as an addition clock signal and a clear signal. Further, the output (added value) of the accumulator 17 is fed back to the addition/subtraction circuit 16 and is subjected to addition/subtraction processing. However, buffer memory 4
The call signals sequentially read out from the call signals are linearly converted, and then those participating in the conference are sequentially added up over the same conference group. Then, the total value is set in the accumulator 17. Then, in the second scan, each call signal read out from the buffer memory 4 is sent to the accumulator 17.
The compression circuit 18
has been entered. The compression circuit 18 again compresses the signal on which the conference calculation has been performed, restores it to the original call signal form, and then stores it in the buffer memory 4.
I am rewriting it. Therefore, the conference call signal rewritten in the buffer memory 4 becomes, for example, as follows. Table 1 shows the format of conference calculations in the buffer memories 4 and 5, and shows the data stored before the conference calculation and the data stored after the conference calculation corresponding to the address in comparison. Table 2 shows an example of the configuration of the conference control memory 13 that controls conference calculation processing for the buffer memories 4 and 5, and each address includes a ``conference member channel address'' and a ``3'' indicating the number of conference participants.
This shows how the "person/6 person flag" are stored as data related to conference control. Furthermore, Tables 3 and 4 show that conference control memory 1
3 shows the form of conference calculation processing when data as shown in Table 2 mentioned above is stored. Table 3 shows addresses of buffer memories 4 and 5, where call signals are input and output between call highways 1 and 2, and calls that are input and output between call highways 1 and 2, according to the value of the highway channel counter. This shows the data. Further, Table 4 shows the addresses of the buffer memories 4 and 5 that are input/output to/from the conference calculation circuit 6 according to the value of the conference control memory address, and the format of the conference calculation processing.

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【table】

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[Table] That is, the conference arithmetic circuit 6 scans and reads out the call signals stored in the buffer memory 4 twice in succession, the first time calculates the total value of the call signals for participation in the conference, and the second time the call signals stored in the buffer memory 4 are read out. By subtracting its own call signal from the above-mentioned total value, it obtains the sum of the call signals from other conferees, that is, the combined call signal. What is shown in Table 1 above is a three-person meeting with conference participant data D ₁ , D ₄ , and D ₅ , and conference participant data D ₂ , D ₃ , D ₇ , D ₁₀ , D ₁₃ , and D ₁₄ . This shows a six-person meeting being held, and a three-person meeting using meeting participant data D ₆ , D ₉ , and D ₁₁ . These conference call data are sequentially and regularly written into the predetermined addresses of the buffer memory 4 in the format shown in FIG. 2b. Therefore, the call signal (data
A conference call signal (data _{D 1 =} D ₄ + D ₅ ) is inserted into the time slot where the call signal (data D 1 ) has been sent, and a conference call signal (data D _{2 ) is inserted into the time slot where the call signal (data D 2} ) has been sent. D′ ₂ = D ₃ + D ₇ + D ₁₀ + D ₁₃ +
D ₁₄ ) is inserted. Therefore, each telephone can obtain a conference call signal by transmitting and receiving the call signal in the time slot assigned to it. Next, addressing for the buffer memories 4 and 5 will be explained. FIG. 4 is a control system diagram for address designation, which shows a part of the above-mentioned FIG. 3 in detail. That is, highway channel counter 8
inputs the reference clock signal from oscillator 9,
The same clock signal is counted. The count value of the channel counter 8 indicates the channel of the signal transmitted to the highways 1 and 2. The frame counter 7 receives the output of the carry signal from the channel counter 8, in this case the most significant bit, and performs a binary operation to count frames in binary. The output of the frame counter 7 is used as a frame switching signal, and on the other hand, the address selector 11
On the other hand, the signal is supplied to the address selector 12 via an inverter circuit 19. These address selectors 11 and 12 are configured such that, for example, the frame switching control signal for the address selector 11 is
When the level is HIGH, the output data of the highway channel counter 8 is selected, and when the level is LOW, the output data of the conference control memory 13 is selected. Therefore, when the address selector 11 selects the output data of the channel counter 8, the address selector 12 selects the output data of the conference control memory 13. Conversely, when the address selector 11 selects the output data of the conference control memory 13, the address selector 12 selects the output data of the highway channel counter 8. The operations of these address selectors 11 and 12 are alternately switched by the frame counter 7 each time one frame ends. Therefore, the buffer memories 4 and 5 are addressed in units of one frame so that one side transmits and receives call signals to and from the telephone set, and the other side performs conference calculations with the conference calculation circuit 6. By the way, highway channel counter 8,
The address conversion circuit 14 is configured as shown in FIG. 5, for example. Also conference control memory 1
3, as shown in Table 2, are written conference member channel addresses and identification flags indicating whether there are 3 or 6 people in each group conference. still,
These pieces of information are designated and written by a signal processing device (not shown). As shown in Table 2, if a three-person meeting is held, 4r, 4r
Conference member channel addresses (indicating buffer memory addresses) and a three-person conference flag are set at addresses +1, 4r+2 (r=0, 1, 2, 3...). Also, if a six-person meeting is held,
4r, 4r+1, 4r+2, 4(r+1), 4(r+
1)+1,4(r+1)+2(r=0,2,4,...
…) The address contains the conference member channel address, and 6
The meeting flag is set. These conference member channel addresses are selectively read and output as address information of the buffer memories 4 and 5 by the output of the address conversion circuit 14. Now, with respect to the conference control memory 13 which stores the address information and flags as described above, the highway channel counter 8 is composed of n-ary counters arranged in cascade. That is, the counter 8 includes a ternary counter 8a at the first stage and binary counters (flip-flops) 8b and 8b at the subsequent stages.
c, ~, 8n. The bit outputs of these counters 8a, 8b, . It is something. On the other hand, the output of the highway channel counter 8, that is, the counters 8a, 8b,
, 8n each output 2 ⁰ , 2 ¹ , 2 ^j , 2 ⁰
The output of 2 ¹ bit and each output of 2 ⁴ bits to 2 ^j bits are sent directly to addresses 2 ⁰ , 2 ¹ and 2 of the conference control memory 13 without being subjected to any signal processing through the address conversion circuit 14 . ³ , 2 ⁴
~2 Output as information of ^j-1 . Furthermore, the outputs of 2 ² and 2 ³ bits are output by AND circuits 21 and 23, respectively.
22 is input. The AND circuit 21 is controlled by the 6-person flag set in the conference control memory 13, and sends the 22-bit output to the ²² bits of the conference control memory 13 via the OR circuit 23 ^.
It is output as bit address information. The gate of the AND circuit 22 is opened by the three-person flag similarly set in the conference control memory 13, and the ^23- bit output is sent to the OR circuit 23.
It is given to the conference control memory 13 via. That is, the address designation signal consisting of (j+1) bits outputted from the highway channel counter 8 is applied to the conference control memory 13 via the address conversion circuit 14 as a j-bit signal reduced by 1 bit according to the conference flag. . In the circuit 8, the ²² and ²³ bit output data are input to AND circuits 24 and 25. This AND circuit 24 is controlled by the 3-person flag and takes out a ^22- bit output, and the AND circuit 25 is controlled by the 6-person flag and takes out a ^23- bit output. The output data of these AND circuits 24 and 25 is outputted via an OR circuit 26 as a write control signal for the conference arithmetic processed signal to the buffer memories 4 and 5. Further, a signal obtained by inverting the output of the OR circuit 26 via the inverter circuit 27 is outputted as an addition/subtraction control signal for the aforementioned addition/subtraction circuit 16. According to such address conversion, as shown in Table 4, the address signal of the conference control memory 13 is generated by converting the address signal of the highway channel counter 8, and the address of the memory 13 is specified. At the same time, conference calculation control signals for "addition" and "subtraction" and buffer memory write control signals are output. Therefore, the buffer memories 4 and 5 are each independently addressed on the one hand by the output of the highway channel counter 8 to transmit and receive call signals to and from the telephone set, and on the other hand by the conference control memory 13. The received information is then used for conference calculation processing. An example of this conference arithmetic processing will be described. At timing "1", address "0" of the buffer memory 4 is designated and data _D1 is read out. Next, at timing "2", address "4x1+0" is specified, data _D4 is read out, and added to the data _D1 . Then, at timing "3", address "4×1+1" is specified and data _D5 is read out and added. Therefore, the accumulator 17 obtains an added total value (D ₁ +D ₄ +D ₅ ). Then, at timing "4", address "0" is designated again and data _D1 is read out. This data D ₁ is subtracted from the previous total value, and the data D′ ₁ (=D ₄ +
D ₅ ) and is rewritten to address "0" in the buffer memory. Similarly, timing “5”,
Data D ₄ and D ₅ are each subtracted from the above total value to "6", and each subtracted value D' ₄ and D' ₅ is obtained from the address "4×
1+1" and "4×1+1", respectively. A similar conference calculation process is performed in the case of a six-person flag. The results of this treatment are shown in Table 1 above. FIG. 6 shows the operation timing of the above conference arithmetic processing. FIG. 6a shows an operation timing block, and FIG. 6b shows the output of the highway channel counter 8 determined corresponding to the block. Based on the output data of the highway channel counter 8, the addition/subtraction control signal (FIG. 6c) and the clear signal for the accumulator 17 (FIG. 6d) are generated as described above. Further, e in the figure is an addition clock signal supplied to the accumulator 17, which is also generated based on the output of the counter 8. Furthermore, the same figure f
is a rewrite control signal to the buffer memory, and g is a rewrite clock signal. These signals are also generated in synchronization with the channel, and although the generation circuit thereof is not shown in the drawings, it is easily constructed from addition/subtraction control signals output from the address conversion circuit. As described above, according to this method, conference calculation processing can be performed effectively with extremely simple control. Furthermore, a three-person conference or a six-person conference can be arbitrarily switched and controlled by flag information set in the conference control memory 13, and separate conference circuits corresponding to the number of conference participants are not required. For example, if the device is capable of holding a conference with a total of 24 people in all groups, it is possible to use 8 3-person conference groups, and 4 3-person conference groups and 2 6-person conference groups. It is also easy to hold a conference call. Further, since the address information stored in the conference control memory 13 is specified by a signal obtained by address conversion of the output of the highway channel counter 8, it is extremely difficult to perform repeated scanning twice in succession. It is economical. Moreover, since the conference calculation is completed by repeating these two times, the processing efficiency is extremely high. In addition, in the case of a 5-person meeting or a 4-person meeting, 6
By flagging the conference and assigning the addressing of the conference computing memory 13 to a specific silence value for the remaining channels, this purpose is sufficiently achieved. Now, in the explanation so far, a double buffer was constructed using two individual buffer memories. However, the operating speed of the buffer memory, conference calculation circuit, etc. is sufficiently fast, and as a result, the time for one channel can be sufficiently divided into the signal input/output time for communication highways 1 and 2 and the conference time, as shown in FIG. In this case, the buffer memory can be divided into two areas to form a double buffer as shown in FIG. What is shown in Figure 7 is 1
The first half of the channel is defined as the communication highway input/output time, and the second half is defined as the conference calculation time.
Further, the buffer memory may be divided into two areas based on the 1-bit address signal, for example, using 1 bit of data that specifies the address of the buffer memory. However, in a device configured in this way, the ninth
As shown, only one address selector 31
This can be realized using the buffer memory 32 and the buffer memory 32. In this case, the selection operation of the address selector 31 may be controlled using, for example, MSB information of the output data of the highway channel counter 8. At the same time, the area of the buffer memory 32 can be specified using a signal obtained by exclusive ORing the MSB information and the output of the frame counter 7 via an exclusive OR circuit 33. According to the device configured in this manner, the address information and the control area of the buffer memory 32 are alternately selected for each first half and second half of the channel, as shown in the time chart of FIG. Furthermore, the order of designation of the above areas is reversed each time the frame changes. To briefly explain Figure 10, (a)
shows the channel, (b) shows the highway input/output period, and (c) shows the conference calculation time. That is, the first half of the channel performs input/output with the highway, and the second half performs conference calculations. Also, (d) in the same figure shows information for addressing the buffer memory 32, and HCC is output data from the highway channel counter,
CCM shows output data from conference control memory. Further, (e) shows an area of the buffer memory 32 that is addressed by the above data. The order of the motion areas is reversed for each frame. (f) is the MSB of the highway channel counter.
Output data, (g) is frame counter output, and
(h) shows an area designation signal (output of the exclusive OR circuit 33) determined by each of the above data. There is no need to describe these operations again, but the above-described transmission and reception of call data and conference calculations are performed spatially and time-divisionally. Thus, even with this type of device, the present system exhibits the same effects as the previous embodiment, and its advantages are tremendous. Next, to describe the effects of the method of the present invention, it is found that it has the following characteristic advantages. (i) Three-person conferences and six-person conferences can be easily performed simply by specifying flags, and no special signal processing is required. (ii) In the case of a three-person conference and a six-person conference, the circuit required for the conference arithmetic processing can be shared as is, and the circuit configuration (device) does not become complicated. (iii) Therefore, compared to conventional devices with a three-person conference function, six
It can provide services for people meetings and has great economic advantages. (iv) In addition, the circuit configuration is simple because the output of the highway channel counter is converted into an address and used effectively for control. (v) Therefore, the conference device can be realized very simply and at low cost. As described in detail above, according to the present invention, it is possible to dynamically set a conference group among a plurality of conference participants and the number of conference participants in a very simple manner. In addition, it is possible to realize and provide a conference call system that exhibits various special advantages such as being able to conduct flexible and extremely effective conference calls and being extremely easy to control. Note that the present invention is not limited to the above embodiments. For example, the number of conference participants may be set to 4 people and 8 people, and the number of channels constituting one frame may be determined as appropriate. Further, address conversion may be performed by appropriately determining the conversion conditions according to the settings of the conference group. Furthermore, the number of call conference participants and the conference format may be set as appropriate. In short, the system of the present invention can be implemented with various modifications without departing from the gist thereof, and can be widely applied to various conversion devices.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an outline of a conference device to which the method of the present invention is applied, Fig. 2 is a data format of transmitted and received call signals, Fig. 3 is a diagram showing a conference calculation circuit, and Fig. 4 is an address specification control diagram. 5 is a diagram showing address conversion, FIG. 6 is a timing diagram showing operation, FIG. 7 is a diagram showing processing time divisions, and FIG. 8 is a diagram showing divided areas of buffer memory. , FIG. 9 is a system diagram showing address designation control when buffer memory is spatially divided.
FIG. 0 is a timing diagram showing the operation of the circuit shown in FIG. 1...Receiving highway, 2...Transmitting highway, 3
a, 3b, 3c, 3d... switch, 4, 5... buffer memory, 6... conference calculation circuit, 7... frame counter, 8... highway channel counter, 9
...Oscillator, 11, 12...Address selector, 13
...Conference control memory, 14...Address conversion circuit, 1
6... Addition/subtraction circuit, 17... Accumulator, 31...
Address selector, 22...Buffer memory.

Claims (1)

[Scope of Claims] 1. Call signals input from a plurality of telephones in a time-division manner are stored in a buffer memory, and after the call signals stored in the buffer memory are subjected to conference calculation processing, they are supplied from the buffer memory to the plurality of telephones in a time-division manner. When doing so, the address output of the channel counter that determines the call channel in the above time division is converted into an address, the conference control memory is addressed, and the call stored in the buffer memory is processed at the buffer memory address stored in the conference control memory. The signals are sequentially scanned twice and read out, the first time is to sequentially add each call signal to obtain the total value, and the second time, each call signal is subtracted from the total value, and the buffer memory is read out. A conference calculation method characterized in that conference calculation processing is performed by rewriting each. 2. The conference calculation method according to claim 1, wherein the address conversion is performed by reducing the address output of the channel counter by 1 bit to obtain an address signal that circulates twice in one frame cycle. 3. The conference control memory stores a flag indicating the number of participants in the conference together with the channel address of the call signal, and operates by switching the specified address of the conference control memory in accordance with the flag. The conference calculation method described in Section 1. 4. The buffer memory is composed of elements with sufficiently high operating speeds to serialize the input/output time of speech signals to and from the communication highway and the conference calculation time during one channel, and has an n-bit address line. It is configured by dividing one physical memory area into two, and outputs the output of the highway channel counter or the conference control memory selectively obtained via the selector (n- 1) Bit buffer
Exclusion of the buffer memory switching signal line which is used as a memory address line and divides the buffer memory into the input/output time of the call signal to the call highway and the conference calculation time during one channel, and the output of the frame counter which is inverted for each frame. The present invention is characterized by operating the logical sum output as the remaining 1-bit address line, and at the same time switching the selector using the buffer memory switching signal line to divide one physical memory into two areas and perform conference calculations. A conference calculation method according to claim 1.