JPS5916459B2 - A device that realizes multiple conferences simultaneously in a PCM switching system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to conference calls in time division switching systems, more particularly pulse code modulation PCM systems.

In time division multiplexing, sampled or encoded voice signals generated by a subscriber occupy time slots that are assigned within repeating ordered groups of time slots called "frames."

The connection of two subscribers can be accomplished by a number of techniques, so that the information contained in the repeating time slots of each of the two subscribers is exchanged in both directions.

If three or more subscribers desire simultaneous multiplex interconnection, ie, conferencing, more complex processing of the time slot information is required.

Given a PCM system, an obvious way to implement conferences between subscribers is to
The idea is to algebraically add the words and transmit the sum to one removed participant. If this procedure is performed for each conference participant for each frame, a conference connection is established. If the PCM signal is obtained by non-linear encoding (which is usually the case), then the PCM words are linearized and summed, each sum obtained is converted back to a non-linear code, and then converted into an appropriate code. conference participants. Due to the complexity of the design and the expensive circuitry required, prior art techniques such as PitrOda et al.
US Pat. No. 3,699,264, issued Oct. 17, 972, avoids this technique.

A simple approach is adopted in the PitrOda et al. patent. That is, the participant with the numerically largest binary PCM word is selected as the speaker by the multiple cross-comparison circuit.
Although this simple approach is not very expensive, it is often inappropriate in that it prevents natural multiple interconference schemes.
The present invention provides a circuit for realizing a conference call connection in a PCM switching system, each having an arbitrary number of participants, limited in principle only by the number of channels in one frame. The circuit can be shared by multiple simultaneous conferences.

However, other practical limitations will be discussed later. An object of the present invention is to provide a device for realizing multiple conferences simultaneously.

Another object of the invention is to provide an apparatus for simultaneously realizing multiple conferences in which the two storage means alternately function as input/output memory and arithmetic memory, thereby simplifying the structure. That's true.

According to the invention, the above objects and other objects are achieved between at least three predetermined channels each in an incoming frame of a pulse code modulated audio signal which is arranged in the respective time slots constituting the incoming frame. an apparatus for simultaneously implementing multiple conferences; each accepting and storing the incoming frame; one transmitting its pre-stored contents at the same time as accepting the incoming frame;
two interchangeable storage means RAMI, R adapted to cooperate with arithmetic processing means 15, 16, 17, the other processing the stored information and storing the results of said processing;
AM, the two interchangeable storage means and the processing means are responsive to timing and control means 10 for clocking, initiation and termination of internal operations, and the initiation and termination of the operations are responsive to timing and control means 10 for timing, initiation and termination of internal operations. This is achieved by providing a device characterized in that it consists in interchanging said two interchangeable storage means at the end of each incoming frame. P
Because CM systems often use companding or non-linear encoding, in most systems the processing of stored frames does not consist solely of arithmetic operations.

Rather, the contents of each channel must be decompressed or linearized before processing. After the calculation process is completed,
The final result for each channel is retransformed nonlinearly,
It is then finally stored for transmission. According to the system outlined above, there is typically a delay of two frames.

A first frame delay occurs during incoming frame storage and a second frame delay occurs during processing of stored frames. This processing does not require the time of one entire frame, but the final result is usually stored before being transmitted. As a result, a time delay of two frames occurs. First level PCM, such as the 24-channel T1 system in North America or the 32-channel system in Europe.
For the system, it should be noted that one full frame is generally sufficient to complete the processing of the frame with the current state of the art in readily available processing circuitry. An apparatus according to the invention for simultaneously realizing a plurality of conferences in each of at least three predetermined channels in an incoming frame of a pulse code modulated audio signal arranged in the respective time slots constituting the incoming frame , comprising two interchangeable storage means, and these two
Each of the two storage means is adapted to accept and store the incoming frame, one of the two storage means is adapted to accept the incoming frame and simultaneously transmit its pre-stored contents, and the other is adapted to accept and store the incoming frame, and the other one is adapted to accept and store the incoming frame, and one of the two storage means is adapted to accept the incoming frame and simultaneously transmit its pre-stored contents, while the other stores the stored information. and processing means for processing and storing the results of said processing, said two interchangeable storage means and said processing means said at the end of each of said incoming frames. and timing and control means for the initiation and termination of operations consisting of interchanging storage means.
Next, specific examples of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram of a specific example of the present invention.

The interface and control unit 10, commanded from the central processing unit of the switching system,
Select predetermined time slots from the CM eight ways and assemble them serially into a serial PCM frame. This frame becomes the input to the conference circuit. The selected time slot is the one occupied by the channel associated with the conference. The serial PCM input is subjected to multiple conversion (Multip
lexer) devices 11 and 1V into one of the random access memories PAM1 and PAM. PCM
Memory that accepts input is called input/output memory,
The memory PAMI is shown in FIG.

Input/output memory RAMI accepts serial PCM input while simultaneously outputting its contents to input/output multiplex bit latch 12. Latch 12 provides a serial PCM output via a clock to interface and control unit 10, which is connected to one of the system's PCM highways during a given time slot. The arithmetic memory RAM, which stores one frame of PCM data, is connected via an arithmetic latch 13 to a read only memory (ROM) decompressor (non-linear linear PCM code converter) 14.

The linear output of decompressor 14 is one input to adder 15, the other input of adder 15 being addressable accumulator 1.
This is the output of any one of the independent memory addresses within 6. Accumulator 16 is rewritten with the addition result sent to accumulator 16 via accumulator latch 17. The output of the accumulator latch 17 is also the input of another random access memory RAMl and a multiplex converter 19, which converts the output of the accumulator latch 17 or the compressor (non-linear unilinear PCM code converter) 18. One of the outputs is multiplexed by converters 11 and 11'.
The multiplex converter is connected to one of the memories RAMI and RAM. Compressor 18 receives its inputs from arithmetic latch 13 and additional memory RAMl. 1st
In the figure, all control connections from the interface and control unit 10 have been omitted to avoid cluttering FIG.

The interface and control unit 10 controls the multiplexers 11 and 1V, addresses the memories RAMI, . Its function will become clear during the description of circuit operation. The circuit is also clocked by two clocks. The first clock is the normal bit rate 2.048 MHz clock for the switching system;
The clock is twice that number and is synchronized with it. The second clock allows the basic system time slot to be divided into four sections, thereby . Several consecutive operations can be performed within one time slot. Additionally, there is a frame synchronization clock for the system. The general characteristics of the PCM system of this specific example are as follows.

Number of channels: 32 Number of bits/channel: 8 (MSB is sign human) Line format: Companded PCM, μ
Modulo (μ=255) linear equivalent...14-bit multiple conversion format including sign bit and decimal point bit...
・・・・Isochronism (Interleav)
ed)) Bit speed: 2,048 Mbit/
In FIG. 2, one serial PCM frame has eight bit groups 0-7, each bit group having 32 time slots 0-31.

The bits of each channel are processed in parallel within the conference circuit. Therefore, while receiving isochronous PCM frames in series, the input/output memory stores 8 bits of each channel as 1 for processing.
must be represented in one time slot. This is from the output of the 6-input/output multiplex bit latch 12 to the input of multiplexer 11 and 11', and of this multiplexer 1.
1 and 11' to the input of the input/output memory. The word bits of the channels are available in parallel at the output of the arithmetic memory, and by successively reading out the time slots of the arithmetic memory, all channels can be accessed for one bit group period (
PeriOd). This is shown in FIG. One processing cycle of the conference circuit consists of eight periods 0 to 7.
each channel is used once during its respective period.

In fact, only three periods of one frame are essential to process all channels in the conference circuit. In summary, one processing cycle proceeds as follows. Period 0: No activity Period 1: The 8-bit PCM channel word in each time slot is linearized and added to the accumulator storage location associated with that conference (after each addition, the sum is added to the accumulator location). (re-memorized).

Period 2: The PCM word for each time slot is linearized and subtracted from the accumulator storage location associated with that conference.

The resulting 14 bits are partially stored in operational memory, replacing their original contents, and the remaining 6 bits are stored in additional memory, but the contents of the accumulator remain unchanged.

Period 3: 1 for each channel of calculation memory and additional memory
The 4-linear bits are converted to compressed PCM format in the compressor,
It is stored in the computational memory in place of the contents from the previous stage.

Periods 4-7: Additional memory and accumulators are cleared.

At the end of the frame (bit 31 of period 7), the input/output memory becomes the arithmetic memory. Arithmetic memory becomes input/output memory.

The processing route of the above cycle is shown in the circuit of FIG.

The connection indicated by a thick line starting from the arithmetic memory RAM and ending at the accumulator 16 corresponds to the processing of period 1. Memory RA
The first route, extended by the double-lined connections ending in M and M, corresponds to the processing of period 2. Finally, the connection indicated by the dashed line corresponds to the processing in period 3. The operation of the conference circuit will now be described in more detail with reference to FIGS. 1 and 3. The circuit captures all frames of PCM serial data provided by the interface and control unit 10. Each channel extracted from the system's PCM highway is associated with a conference. The multiplexing format of the current system is isochronous (i.e., the channel bits are plugged in rather than bunched together) so that the 8 bits of the channel are used in parallel for processing. will be re-formed. To illustrate how this is accomplished, reference is made to FIG. 3, which illustrates in functional detail the connection of the multiplexer 11, 1V and the associated latches 12, 13 to the memory RAMI. Input/output memory and arithmetic memory (RAMI and RA in Figure 1, respectively)
M) is. It is configured as 32 words with 8-bit memory. They are addressed by time slot number and are read during the second section of the time slot and written during the third section. This arrangement allows a simple parallel connection of the outputs of the six memories without the need for external multiplexing equipment.Latches 12 and 13 then hold the read data as long as required. As seen in FIG. 3, the data is skewed so that data read from bit position X of time slot Y is written to bit position X+1 of the same time slot. Bit position 0, time slot Y at the input of RAMI is the receiver of serial RCM input data. on the other hand. Bit position 7 of time slot Y at the output of the RAMI serially transmits the PCM data processed earlier (during the previous frame).
By the end of the frame, the data is transferred to the input/output memory (BAMI in Figure 3) so that when the input/output memory becomes the arithmetic memory, all eight bits of a time slot (or channel) appear in parallel at the output of that memory. arranged within. Therefore, by sending pulses to the calculation memory at regular intervals over 32 time slots (= 1 bit group), 6
Each channel sample occurs at the output one time (readout is non-destructive). In FIG. 3, the multiplex converter 11
and 1V are functionally illustrated as one unit.

The dashed line shows an alternative mode of operation, in which the memory RAMI acts as an operational memory and the memory RAM acts as an input/output memory. At the end of each frame of input serial PCM data. That is, time slot 31 of bit group 7
At the end of , the multiplexers 11 and 11' are switched to their alternate positions and interchange the memories RAMI and . Due to the read arrangement of the memories RAMl and readout previously described, such an interchange is not necessary at the output (ie, if the selected memory unit allows it). The data obtained in the previous frame is currently used for processing in the arithmetic memory RAM.

During bit group period 1, the 8-bit channel word from the time slot is stored in arithmetic latch 13 at the end of the first section of the time slot. This data is. R.O.
Addressing M decompressor 14 produces a 14-bit linear word that includes a decimal point bit and a sign bit. Such decompressors are known in the art and require only a single clock operation to produce a linear word. The linear word is added in adder 15 to the contents of the storage location for the associated conference in accumulator 16.
The result of the addition is stored in accumulator latch 17 at the end of the third segment of the time slot. The new sum is then added to accumulator 1
6 is written to the same location. Note that the accumulator is addressed by a 4-bit conference number bus which allows only the appropriate conference memory location to be read/written during every time slot. By the end of period 1 of the bit set, each conference location in accumulator 16 has stored the total sum of linear words for channels participating in that conference (the storage location of the accumulator is , 16 bits to adjust for overflow of 14 bits or more as a result of addition.
(has a storage capacity of 1 word). In period 2 of the next group of bits, the above process is repeated except that instead of addition, the channel word is subtracted from the associated conference total.

Subtraction is accomplished by changing the sign bit of the 8-bit input word to ROM expander 14, which produces as output the two's complement of the linear word (depending on the new address). The change of the sign bit (which is the largest digit) is initiated by a command from the controller 10 which is maintained during period 2 of the bit group. The two's complement of the first word added to the total conference word in accumulator 16 plus one is equal to the total conference word minus the first word. The eight most significant digits of the subtraction result are written to the same time slot location in the arithmetic memory RAM, erasing the contents before that location, while the remaining six bits of the 14-bit word are written to the additional memory RAM.
is written to the corresponding position of l.

At the end of period 2 of the bit group, the memories RAM and l contain the linear conference word. During bit group period 3, in each time slot the 14-bit linear conference word stored in memory RAM and I is compressed by compressor 18 into non-linear form (
In other words, it is converted into a compressed form). This compressor is also known in the art, and the function of compression is accomplished partly or wholly by a table, as in the case of decompressor 14. During period 3 of the bit group, multiplexer 19 connects six multiplexers 11 and 11' to the output of compressor 18. The compressed 8-bit PCM word is then stored in the computational memory RAM by rewriting the previously stored information.
In this way, processing of the PCM word ends at the end of period 3 of the bit group. During the next period the accumulator 6 is cleared. At the end of period 7 of the bit group, ie at the end of the frame, multiplexers 11 and 1V are switched by a command from interface and control unit 10 to exchange memories RAMI and H.

The entire cycle of processing is repeated for each new frame.
As previously mentioned, all time slots not associated with a conference are assigned conference number 0 by the interface and control unit 10. During these channels, this is achieved simply by not addressing the accumulators 16. All four addressed bits are O's. During these same time slots, the output of compressor 18 is pulled O, so the memory RAM does not contain any data in these time slot locations. Of course, data suppression during unused time slots can be performed at any other suitable location within the circuit. In fact, the interface and control circuit 10 itself is connected to the PCM highway only in those time slots participating in the conference. For systems using conferencing circuits, it is necessary to delay the serial PCM output from input/output multiplex bit latch 12 by one or more time slots. This is accomplished by a delay memory that can be integrated into the interface and control unit 10.
We mentioned earlier that the practical limit is to limit the number of conference attendees for a single conference.

These limitations are due to the use of trans-hybrids in the line circuits of conference attendee stations.
id) loss. However, there is no clear limit on the number of conference participants who cannot perform six actions. One way to alleviate some limitations (trans hybrid losses, overload, etc.) is to
The purpose is to cause attenuation when the number of conference attendees exceeds a predetermined number. This can be accomplished by using a ROM expander 14 with a storage capacity of 6+ that is capable of generating 6 unattenuated linear words and 6 attenuated linear words. For 6 to 12 conference participants per conference, 6 dB of attenuation has been found to be adequate.

A 1-bit instruction from the interface and control unit 10 is sent to the ROM expander 14 to determine whether an unattenuated linear word or a 6 dB attenuated linear word is to be retrieved.
is sufficient to command. Both sets of linear words (two corresponding to one 256 possible address) are of course permanently stored in the ROM expander 14. The conferencing circuit is configured in public address mode (Pub-11addressm0d
It may be used in e).

This is accomplished by a 1-bit command from control unit 10 that causes the output of ROM expander 14 to be a logic 1 during the talk period. The lowest carry of adder 15 is also set to logic 1. Thereby, the words of the six speakers do not change within the conference position of accumulator 16. This operation is illustrated in the following example. According to the speaker in accumulator 16, only the speaker's words reach the listener.

[Brief explanation of the drawing]

Figure 1 is. FIG. 2 is a block diagram of a conference telephone circuit according to the present invention. FIG. 2 is a diagram showing the relationship between subperiods of the PCM frame at various points in the circuit of FIG. 1; FIG. 3 is a diagram showing a portion of the circuit of FIG. 1, the function of which is shown in detail. 10...
・Interface and control unit, 11, 11',
19...Multiple converter, 12...Input/output multiple bit latch, 13...Arithmetic latch. 14...read-only memory (ROM) decompressor, 15...adder, 16...accumulator. 17...accumulator latch, 18...compressor.

Claims (1)

[Scope of Claims] 1. A plurality of simultaneous conferences each taking place between at least three predetermined channels in an incoming frame of a pulse code modulated audio signal arranged in the respective time slots constituting the incoming frame. A device that realizes;
operations in which each accepts and stores the incoming frame, one accepts the incoming frame and at the same time transmits its previously stored contents, and the other processes the stored information and stores the results of the processing. It comprises two interchangeable storage means RAM I , RAMII adapted to cooperate with the processing means 15 , 16 , 17 , the two interchangeable storage means and the arithmetic processing means being connected in an internal operation. responsive to timing and control means 10 for the timing, initiation and termination of said operation causing said two interchangeable storage means to interchange substantially at the end of each of said incoming frames; A device characterized in that it includes: 2. Apparatus according to claim 1, characterized in that the timing and control means comprises a changeable memory (16) for associating each number of predetermined channels with a conference. 3. Apparatus according to claim 1, characterized in that said processing means responsive to information are adapted to associate each number of predetermined channels with a conference. 4. The processing means comprises a parallel binary adder 15 for adding two binary linear PCM words, and a plurality of separate parallel binary adders 15 each adapted to accept and store a linear PCM word of a predetermined minimum number of bits. an addressable memory 16 having storage locations adapted to be addressed by the control means to a conference address while processing a channel associated with the conference; A device according to claim 1, characterized in that: