JPS61208363A - Picture magnifying and reducing device - Google Patents

Abstract

PURPOSE:To prevent moire stripe and dot number change by obtaining back picture element number of a picture matrix subject to binary coding of an original picture, forming a density pattern based on the black picture element number, generating a new picture from the density pattern, extracting the generated new picture and applying various picture reconstituting processings. CONSTITUTION:A picture forming circuit 7 receives an output of a picture processing circuit 4 and generates a new picture according to the command from the 1st command circuit 5. The 2nd command circuit 9, according to the command of the 1st command circuit, commands the allocated position on a pattern in response to the number of repetitions of the matrix pattern and interleaving number in response to the magnification to the matrix pattern for one row's or one column's content outputted from the picture generation circuit 77. The picture data subject to reconstitution by a picture reconstitution circuit 8 is stored in a picture memory 10. An operation circuit 3 receives a binary-coded matrix data stored in a binary-coding circuit 1 or a memory 2 and obtains the black number picture elements at each block through operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image enlarging/reducing device capable of enlarging or reducing at least one of an image.

(Prior Art) The SPC method has conventionally been used as an image enlargement/reduction method for enlarging or reducing an image using a pixel density conversion method.

The Fl sum method, 9-division method, projection method, etc. are known.

(Problems to be Solved by the Invention) The problems with these conventional methods include the fact that the lines are blurred or missing, but the problem with Pierre is that the two When enlarging/reducing a medium 11) g1 image with a periodic structure such as a valued image, moiré fringes occur.

The present invention has been made in view of this point, and its purpose is to
An object of the present invention is to provide an image enlargement/reduction method that can easily enlarge/reduce even a binarized image with a periodic structure without causing moiré fringes.

(Means for Solving the Problems) The present invention, which solves the above problems, includes a PI4 arithmetic circuit that calculates the number of black pixels for each block from a binarized image matrix, and a PI4 arithmetic circuit that calculates the number of black pixels for each block from a binarized image matrix. An image processing circuit that performs conversion processing into numerical values, an image creation circuit that creates a new image from the output of the image processing circuit, and a matrix pattern of one row or one column output from the image creation circuit. The present invention is characterized in that it is comprised of an instruction circuit that instructs the allocation positions of these matrix patterns on the screen according to the magnification, and an image reconstruction circuit that reconstructs the image in accordance with instructions from the instruction circuit. It is something.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is 2fi which binarizes the input image signal.
ff conversion circuit 2 is a memory in which an image matrix already converted into 2fti is stored. As the binarization circuit 1, for example, one that performs binarization using a dither matrix is used. 3 is an arithmetic circuit that calculates the number of multi-value pixels (here, black pixels) in the 21a image matrix output from the binarization circuit 1 or the memory 2 for each block;
is an image processing circuit which receives the output of the arithmetic circuit 3 and converts it into another numerical value according to a density conversion instruction from the first instruction circuit 5.

Reference numeral 6 denotes an operation panel for giving instructions to the first instruction circuit 5 regarding magnification 1 gradation pattern, i degree conversion, etc. The operation panel 6 includes, for example, a keyboard and a CRT display section. 7 is an image creation circuit that receives the output of the image processing circuit 4 and creates a new image according to instructions from the first instruction circuit 5; 8 reconstructs the image according to instructions from the second instruction circuit 9; This is an image reconstruction circuit. The second instruction circuit 9 repeats the matrix patterns for one row or one column output from the image creation circuit 7 according to the magnification according to instructions from the first instruction circuit 5. This indicates the allocation position on the screen according to the number of decimations (1).

The image data reconstructed by the image reconstruction circuit 8 is stored in the image memory 10. The operation of the device configured as described above will be explained as follows.

The binarization circuit 1 converts an original image 11A composed of seven trixes for each pixel as shown in FIG.
Binarization processing is performed using a 4×4 dither matrix as shown in FIG. As a result, 2
The shaded areas in FIG. 6 where the valued image matrix B is obtained are black pixels.

Here, the black pixel is the most frequent pixel. The arithmetic circuit 3 is
Upon receiving the binarized image matrix data as shown in FIG. 2(c) stored in the binarization circuit 1 or memory 2, the number of black pixels for each block is calculated. Here, a block refers to an area surrounded by a thick solid line in FIG. 2(c), and in the example shown in the figure, one block is composed of 4×4.

In order to reduce the block structure when enlarging an image, it is preferable that the block be small, and as shown in the figure, the preferable size is about 4×4. FIG. 3(b) is a diagram showing the number of black pixels obtained in this manner.

The image processing circuit 4 receives black pixel count data for each block from the arithmetic circuit 3 as shown in FIG. 3(B) and performs arithmetic processing to convert it into another numerical value. As a method of arithmetic processing, for example, data indicating the number of black pixels for each block shown in FIG. 3(D) is regarded as the average density, and digital arithmetic is performed. At this time, the image processing circuit 4
The following processing is performed according to the density conversion command from.

That is, each value shown in Figure 3 (b) is regarded as the average concentration,
Binarization processing is performed using a 4×4 dide matrix as shown in FIG. 3(a). The average of 14 degrees in the first block B1 is 7
It is. Therefore, a binarization conversion is performed in which only pixels having a value equal to or smaller than 7 in the dither matrix shown in FIG. 3(a) are converted into black pixels, and the result is output. Perform the above operations for all blocks. FIG. 3(c) is a diagram showing the conversion result.

It should be noted that various other methods can be considered for the numerical value conversion process by the image processing circuit 4. For example, a density curve can be specified from the operation panel 6, and new converted values can be obtained, for example, in a ROM table lookup format. However, if you want to obtain an arbitrary curve rather than a fixed curve like this, use a function generator instead of the ROM to create an arbitrary curve shape, and follow this curve to obtain conversion output data for input data. Just do it like this.

The image creation circuit 7 receives the numerically converted data from the image processing circuit 4 obtained in this way and creates a new image according to instructions from the first instruction circuit 5.

For example, a command signal such as a mesh pattern and a mesh angle pattern is received from the first instruction circuit 5, and a pattern corresponding to the command signal is created.

For example, assume that the first instruction circuit 5 gives a command signal for a mesh pattern. The image creation circuit 7 creates a matrix as shown in FIG. 3(c) from the output of the image processing circuit 4 sent for each block. That is, the third
If the values of each block in FIG. 3(b) are converted into ltl according to the dither matrix shown in FIG. 3(a), a matrix as shown in FIG. 3(c) will be obtained.

Specifically, when the output data of the image processing circuit 4 is set as the X address and the Y addresses are sequentially scanned, the address becomes 1.
The configuration is such that a pattern for one column or one row of the matrix is output each time the matrix is incremented.

The image reconstruction circuit 8 reconstructs one screen worth of images from the one column or one row of patterns sent from the image creation circuit 7 according to instructions from the second instruction circuit 9. For example, when obtaining an enlarged image, the same column pattern (or row pattern) is repeated as many times as necessary, and when obtaining a reduced image, some column patterns (or row patterns) are thinned out, and the image is regenerated. Perform configuration. At this time, the repetition start position and end position of the column pattern (or row pattern) on the screen when enlarging the image 9 The assigned position of the column pattern (or row pattern) when reducing the image is reconstructed from the second instruction circuit 9. is applied to circuit 8. 1 reconstructed by the image reconstruction circuit 8
The image pattern for the screen is stored in the image memory 10. The stored enlarged or reduced image is retrieved and subjected to image processing as necessary.

FIG. 4 is an electrical circuit diagram showing a specific configuration of an image processing circuit section consisting of an image processing circuit 49, an image creation circuit 7, an image reconstruction circuit 8, and a second instruction circuit 9. As shown in FIG. Arithmetic circuit 3
The black III prime number counted by (see FIG. 1) is received by the threshold value storage ROM 11 and converted into another numerical value. The conversion characteristics can be selected by the 1III selection signal. Then, the conversion □ operation is performed by the separately inputted clock CLK.

In this way, the converted numerical data is stored in the RAM 12.
is input. The RAM 12 includes an address setting ROM.
The address is given from 13.

The address setting ROM 13 contains a multiplication signal 1 line counter 1.
4 output and column counter 15 output are given, and the address setting ROM 13 receives these signals and sets the RAM.
Give an address corresponding to the input signal to I2. A first clock CLK1 is applied to the row counter 14, a second clock CLK2 is applied to the column counter 15, and the outputs of these counters are used as addresses to set the address RO.
Given to M13.

The address setting ROM 13 receives the magnification signal and determines whether to perform image enlargement processing or image reduction processing.

The address setting ROM 13 stores in advance data corresponding to the image enlargement mode and the image reduction mode, and when it is confirmed which of the modes the address setting ROM 13 is in,
The address setting ROM'+3 is designed to output corresponding numerical data stored therein as an address and provide it to the RAM 12.

On the other hand, the RAM 12 stores an n'xn (n is an integer) pattern determined by the number of black pixels and the threshold pattern, and the output of the threshold storage ROM 11 and the address setting RO
The output of M13 is received as a row/column designation address, and the data stored at the corresponding address is sequentially output. That is, as described above, when enlarging an image, the same data is output multiple times in succession, and when reducing an image, some addresses are skipped or some data is ignored and output. The image data thus output is sequentially stored in the image memory 10 and reconstructed as an enlarged II image or reduced image for one screen.

FIG. 5 is an explanatory diagram of image reconstruction when reducing the original image by 3/4 times. The pattern shown in the figure shows the pattern created by the image creation circuit 7. FIG. 6 is a diagram showing an example of an image reconstructed based on the matrix shown in FIG. 3(C). FIG. 6(A) shows an example of a 5/4 times enlarged image, and FIG. 6(B) shows an example of a 3/4 times reduced image.

(Effects of the Invention) As described above in detail, according to the present invention, the number of black pixels in the binary image matrix of the original image is determined, and a density pattern is created based on this number of black pixels. An enlarged or reduced image can be obtained by creating a new image from this density pattern, extracting the created new image, and performing various reconstruction processes. According to the present invention, since a part of the new image is used, moiré fringes and changes in the number of dots do not occur even in periodic images. Therefore, high quality image processing can be performed.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention, and FIG.
The figure is 2 (Explanatory diagram of In conversion, Figure 3 is an explanatory diagram of numerical conversion,
FIG. 4 is a diagram showing a specific configuration example of the image processing circuit section, and FIG.
The figure is an explanatory diagram of image reconstruction during image reduction, and FIG. 6 is a diagram showing an example of a reconstructed image. 1...Binarization circuit 2...Memory 3...Arithmetic circuit 4...Image processing circuit 5.9...Instruction circuit 6...Operation panel 7...Image creation circuit 8
...Image reconstruction circuit 10...Image memory 11.
...Threshold value storage ROM12...RAM 13...Address setting ROM 14...Row counter 15...Column counter Patent applicant Roku Konishi Photo Industry Co., Ltd. Agent Patent attorney Fuji Ijima One person outside the womb Figure 1 M4 Figure M5 Figure M6 (B) (V4)

Claims (1)

[Claims] An arithmetic circuit that calculates the number of black pixels for each block from a binarized image matrix, an image processing circuit that converts the output of the arithmetic circuit into another numerical value, and a new image from the output of the image processing circuit. an image creation circuit to create; an instruction circuit that instructs the allocation positions of the matrix patterns on the screen according to the magnification with respect to the matrix patterns of one row or one column output from the image creation circuit; An image enlargement/reduction device comprising an image reconstruction circuit that reconstructs an image according to an instruction from the instruction circuit.