JPS61207127A - Tester for protective relay - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a test device for a protective relay device, and more particularly to a test device for a protective relay device that generates a waveform that simulates the amount of electricity in a power system. .

[Conventional technology]

FIG. 4 is a block diagram showing a test device for a protective relay device disclosed in, for example, Japanese Unexamined Patent Publication No. 56-133930.
1 is a data input unit; 12 is a memory that stores continuous data that is output from the data input unit 11 and simulates the voltage or current waveform of the electric power system; 13 controls reading of the memory 12 and stores the read data; 14 is a digital-to-analog (D/A) converter that converts the data output from the data controller 13 into an analog signal; 15 is an amplifier that amplifies the output of the D/A converter 14; 17 18 is a variable frequency oscillator that supplies a variable frequency clock signal for controlling the operations of the data control unit 13 and the LE converter 14; 18 is an amplifier 15;
19 is a relay that is a protective relay device to be tested; 20 is a recording display unit that records and displays the test results of relay 19; 26 is a unit that measures the operating state of amplifier 15; This is the measurement section.

Next, the operation will be explained. The data input unit 11 causes the memory 12 to store data in a format in which the voltage and the like of the power system are sequentially sampled at a constant period.

The data control unit 13 reads and stores the data in the memory 12 using a clock signal from the variable frequency oscillator 17, and also reads the data using a clock signal set at an appropriate speed and supplies it to the D/A converter 14. The amplifier 15 amplifies the analog signal from the sill value converter 14 by the amplification factor given by the signal from the gain adjuster 18, and inputs it to the relay 19 for testing. The operating state of the relay 19 is recorded and displayed on the record display section 20. Further, the operating state of the amplifier 15 is measured by a measuring section 26.

[Problem that the invention seeks to solve]

Conventional test equipment for protective relay devices is configured as described above, so if multiple test inputs are required, only that number needs to be provided. There has been a problem in that it is difficult to set the phase relationship between the voltage and current to a predetermined value.

This invention was made in order to solve the problems of the conventional ones as described above, and it is possible to generate a wide variety of test inputs with high accuracy, and it is possible to repeat such test inputs for a long time. It is an object of the present invention to provide a test device for a protective relay device that can generate data and set the electrical correlation between each test input.

[Means for solving problems]

A test device for a protective relay device according to the present invention stores data representing a plurality of waveforms in a memory, reads out these data from the memory in a time-division multiplexed format, and reads the data in a time-division multiplexed format using a latch timing signal. The output of the data latch register is converted into an analog signal, and an appropriate gain is applied to obtain a test input for the protective relay device.

[For production]

Since the data latch register in this invention is read from the memory and stores the dead time division multiplexed data separately for each waveform, it is possible to convert the outputs of the two data registers into analogs and give appropriate gains. Generate multiple test inputs for testing protective relay devices with controlled frequency, phase, and gain.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the data input section 11 and memory 12 are the same as those in FIG.
It has the configuration as shown in the figure, and the address 23 is stored in the memory 12.
and input data 22 from memory 12.

14a to 14n are D/A converters that input unique waveform data 25a to 25n from the data control unit 13 and convert them into analog signals, and 15a to 15n convert the outputs of the value converters 14a to 14n to appropriate The amplifier 16 that amplifies the signal at an amplification rate is a period control section that outputs to the data control section 13 an address 23 at an appropriate speed and latch timing signals 24a to 24n having timings as shown in FIG.

Next, the operation will be explained. The data input unit 11 causes the memory 12 to store data of a plurality of waveforms simulating the voltage, current, etc. of the power system. This data is read out as data 22 from the memory 12 under the control of the data control section 13, and latched into the data control section 13 under the control of the latch timing signals 24a-24n. The data 22 is a time-division multiplexed signal of multiple waveform data, but since it is discriminated by the latch timing signals 24a to 24n and latched to the data control section 13, it is now divided into individual data 25a to 25n. These signals are respectively input to the D/A converters 14a to 14n. D/A
The converters 14a to 14n convert the data 25a to 25n into analog signals, respectively, and input the analog signals to the amplifiers 15a to 15n. The amplifiers 15m to 15n amplify the stain pressure or current by a preset amplification factor and supply the amplified signal as a test signal to the relay 19 shown in FIG. 4. FIG. 2 shows the details of the data control section 13. In the block diagram of the circuit shown in FIG. 1, a 0 data latch register 21a indicates that the memory 12 is read using the address 23 inputted from the period control unit 16, and the resulting data 22 is supplied to the data latch registers 21a to 21n. ~21
n discriminates the content of the data 22 from the latch timing signals 24a to 24n, and latches and outputs data 25a to 25n each representing a specific waveform.

FIG. 3 is a timing diagram showing the operation of the data control unit 13, and is shown for the case of n-4, that is, the case of n=4. The data 22 is therefore waveforms A and B.

It consists of data obtained by time division multiplexing C and D. The latch timing signals 24a to 24n are generated at the timing when waveforms A, B, C, and D exist, and cause the data 22 to be latched by the data latch registers 21a to 2In, respectively. The latch timing signals 24a to 24n are generated when the contents of the data 22 become stable as shown in the figure.Although the above embodiment describes the case of four types of waveforms, other numbers of waveform types are possible. It's okay.

Furthermore, in the above embodiment, a case was explained in which a data latch register was provided as a latch, but it may also be provided in a memory. It is also possible to use a device that outputs a plurality of waveform signals, both of which produce the same effects as the above embodiments. [Effects of the Invention] As described above, according to the present invention, data of a plurality of waveforms stored in a memory The data is read out by time-division multiplexing, the data is separated into multiple waveform data by the data control unit, and each is independently converted into an analog signal. This has the effect of allowing the protective relay device to be tested with high accuracy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a test device for a protective relay device according to an embodiment of the present invention, FIG. 2 is a block diagram of a data control section, FIG. 3 is a timing diagram of the operation of the data control section, and FIG. 012 is a memory, and 14a-14n are D/
A conversion section, 15 & -15n are amplifiers, 16 is a period control section, and 211 to 21n are data latch registers.

Claims (1)

[Claims] A memory that stores data of a plurality of waveforms, a plurality of data latch registers that sequentially read the data from this memory and store the data at unique timings so as to select one of the waveforms, and the data A plurality of digital/analog converters each converting the data of the latch register into an analog signal, and the above-mentioned digital/analog converter.
A test device for a protective relay device, comprising: a plurality of amplifiers each amplifying the output of an analog conversion section; and a period control section controlling writing and reading of the memory and the data latch register.