SU1453622A1 - Sound amplifying apparatus - Google Patents

Abstract

The invention relates to electromechanical transducers. The aim of the invention is to increase the permissible gain of the sound system without the danger of self-excitation. The device contains a power amplifier 1, the output of which is connected to the loudspeaker 2, which can be installed in the same room with the microphone 4 connected to the preamplifier 5, the output of which is connected to the input of the frequency equalizer 6. The device is additionally equipped with an analog-to-digital converter 7 connected by the input to the output of frequency equalizer 6 or preamplifier 5, memory block 8, connected to the output of analog-digital converter 7, digital-to-analog converter 9, connected between the output of the memory block 8 and the input of the power amplifier 1, the address switch 10, the address output connected to the address bus of the memory block 8, counters 11.12 write addresses and the address of the read address, respectively, connected to the inputs of the switch 10 addresses, block 13 synchronization, generator switch 14, two outputs connected to inputs of synchronization unit 13, two oscillators 15.16 with frequency detuning connected to inputs of generator switch 14, and switching output of address switch 10 is connected to switching input comm tator 14 generators. 7 il. about (L 4ii CD CO O5 N3 N9

Description

Io1 / retention refers to instrumentation, namely devices, to amplify sound.

The aim of the invention is to increase the allowable gain of the device.

Fig, 1 shows a block diagram of the device; Figures 2-6 are diagrams explaining the principle of its operation; Fig, 7 is a block diagram synchronization.

The device (FIG. 1) contains a power amplifier 1, a loudspeaker 2 connected to its output, having the possibility of being installed in one location 3 with a microphone 4 connected to the input of the preamplifier 5 whose output is connected to the input of the frequency equalizer 6. The device contains Also, an analog-to-digital converter (lil) 7 connected to the output of frequency equalizer 6, moreover A1 A1 7 can be connected to the output of the preamplifier 5, Memory block 8 is connected to the output A1 A1 7, digital-to-analog converter (DAC) 9 An input is connected to the output of the memory block 8, and an output is connected to the power amplifier 1. The address switch 10 is an address input connected to the address bus of the memory block 8. The counters 11 and 12 of the write and read address are connected by outputs to the inputs of the switch 10 addresses. The synchronization unit 13, the generator switch 14 are connected to the outputs of the synchronization unit 13 by two outputs. Two oscillators 15 and 16 with frequency mismatch, having a fundamental frequency of at least 100 kHz, are connected to the switch inputs of the 14 generators. The synchronization unit 13 with its outputs is connected to the start inputs of the ADC 7, the writing and reading of the memory block 8, the input / write to the D / A register 9, the counting input of the counters 11, and 12 the write and read addresses, the switching input of the address switch 10,

 The device operates as follows (FIG. 2-6).

In the device for amplifying the sound, the analog signal is sampled by the ADC 7 with the sampling interval specified by the trigger signal of the ADC 7, which is fed to the start signal of the ADC 7 from the synchronization unit 13. The start signal of the A / D converter 7 appears in response to the write request signal received by

.

ts

20

, - | about 25

4.536222

to the input of the synchronization unit 13 through the generator switch 14 from the generator 15, the obtained signal samples are recorded from the output of the A / D converter 7 via the write bus in digital form in the memory unit 8. The recorded samples from the memory block 8 are read into the input register of the digital-to-analog converter 9 at time intervals specified by the DAC gating signal 9 received from the synchronization unit 13. A gating signal, CA 11, 9 appears in response to a read request signal, which is fed to the input of the synchronization unit 13 via the generator switch from the generator 16. Recording is performed sequentially in the memory unit 8 in each cell. The cell number to which the recording is currently being recorded is received via the address bus of the memory block B through the address switch 10 from the write address counter 11. Thus, the recording occurs as in a ring register, the elements of which are memory cells. The reading of the recorded readings occurs from the same ring register at the address indicated by the reading address counter 12 (FIG. 3).

The address switch 10 continuously compares the write addresses coming from the write address counter 11 with the read addresses. Coming from the counter 12 addresses reading. When the difference of addresses is less than a given number, t, e, the address of the record is like

thirty

35

40

it will catch up with the reading address on the ring, since, due to generator detuning, writing is made more often than reading, address switch 10 outputs a switching signal of generators 15 and 16 to switch 1 input of switch 14 of generators.

Upon receipt of the switching signal of generators 15 and 16, the switch 14 of the generators switches the outputs of the generators 15 and 16 to the inputs of the synchronization unit 13 back to the connection that was before the arrival of this switching signal of the generators 15 and 16. Thus, the signal sampling will occur at inverse intervals, t .e, the write is slower than the read, and the write addresses will already lag behind the read addresses.

Dependence of frequency on time, corresponding to phase modulation with

the law of phase change shown in fig. 5 is shown in FIG. 6

Claims (1)

Invention Formula A device for amplifying sound, containing a power amplifier connected in series and a loudspeaker installed in the same room with a microphone connected through a preamplifier to the input of a frequency equalizer, characterized in that, in order to increase the allowable gain factor, serially connected analog-to-digital converter, a memory unit and a digital-analog converter connected by an output to the input of a power amplifier, write and read address counters, an address switch owl, synchronization unit, switch and the first and second signal generators j connected by outputs to the corresponding u U53622 the inputs of the switch connected by the first output to the first input of the synchronization unit and to the input of the read address counter connected by the outputs to one of the inputs of the address switch connected by the switching output to the control input of the switch connected to the input of the write address counter connected to each other outputs with other inputs of the address switch, the start-up input of the analog-digital converter and the second input of the synchronization unit connected by the first output to the input writing the memory block and the second output to the interconnected read input of the memory block, 0 to the write input of the digital-to-analog converter and the switching input of the address switch connected by the outputs to the address bus of the memory block. W  / 37 UilnTi) ., ||, | ,, / 1 || 1 G, M % schG /, w / / 7G  / 37 /, w 7G fl, Sonuch Fig.i T 2G jr 4G Shy T zt 5 0) ST 4T phage. 6T IT ioqo : g yooo E} FIG. 7