JPS61203670A - Production of solid-state image pick-up device - Google Patents
Production of solid-state image pick-up deviceInfo
- Publication number
- JPS61203670A JPS61203670A JP60045131A JP4513185A JPS61203670A JP S61203670 A JPS61203670 A JP S61203670A JP 60045131 A JP60045131 A JP 60045131A JP 4513185 A JP4513185 A JP 4513185A JP S61203670 A JPS61203670 A JP S61203670A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- region
- well region
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 3
- 238000003384 imaging method Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 238000011109 contamination Methods 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 4
- 150000004767 nitrides Chemical class 0.000 abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 16
- 239000013078 crystal Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 239000005416 organic matter Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 241000894006 Bacteria Species 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- -1 oxygen ions Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 150000003017 phosphorus Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は固体撮像装置の製造方法に関し、特に画像欠陥
の減少対策に改善を図ったものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a solid-state imaging device, and particularly aims at improving measures for reducing image defects.
従来、固体撮像装置例えば縦型オーバーフａ−ドレイン
構造を有するインターライン転送方式イメージセンサと
して第２図に示すものが知られている。2. Description of the Related Art Conventionally, a solid-state imaging device, such as an interline transfer type image sensor having a vertical overflow A-drain structure, as shown in FIG. 2 is known.
図中の１は、Ｎ型のシリコン基板である。この基板ｌの
表面には、浅いＰウェル領域２ａと深いＰウェル領域２
ｂが形成されている。一方の浅いＰウェル領域２ａの表
面には、感光画素用の第１ＯＮ ＠３が形成されている
。他方の深いＰウェル領域２ｂの表面には、前記Ｎ 層
３からの信号電荷を読み出すための埋め込みチャネル用
の第２のＮ 層４及びチャ木ルストッパ用（画素分離用
）のＰ 領域５が形成されている。前記基板１上には絶
縁膜６が設けられ、この絶縁膜６の内部には第１１ｆｉ
の転送電極７ａ。1 in the figure is an N-type silicon substrate. The surface of this substrate l has a shallow P well region 2a and a deep P well region 2.
b is formed. A first ON@3 for a photosensitive pixel is formed on the surface of one of the shallow P well regions 2a. On the surface of the other deep P well region 2b, a second N layer 4 for a buried channel for reading signal charges from the N layer 3 and a P region 5 for a channel stopper (for pixel isolation) are formed. has been done. An insulating film 6 is provided on the substrate 1, and an eleventh fi
transfer electrode 7a.
７ｂ及び第２層の転送電極８が設けられている。7b and a second layer transfer electrode 8 are provided.
前記絶縁膜６上には、感光画素用の第１のＮ＋＠３に対
応する部分が開口された例えばＡＩからなるシールド膜
９、及び保護膜ＩＯが設けられている。On the insulating film 6, a shield film 9 made of, for example, AI and having an opening corresponding to the first N+@3 for the photosensitive pixel, and a protective film IO are provided.
ところで、上記構造のイメージセンサを製造する場合、
以下の工程等でシリコン基板１の地肌が露出することが
ある。By the way, when manufacturing an image sensor with the above structure,
The bare surface of the silicon substrate 1 may be exposed in the following steps.
■ Ｐウヱル領域２ａ、２ｂを形成するために打ち込ん
だ不純物を活性化するためのプランピング後の全面剥離
工程。(2) Full-surface peeling process after plumping to activate impurities implanted to form P well regions 2a and 2b.
■ 第１層の転送電極７ａ、７ｂ及び第２層の転送電極
８下の絶縁１ｌＷ６を形成する工程。(2) Step of forming the insulation 11W6 under the first layer transfer electrodes 7a, 7b and the second layer transfer electrode 8.
しかしながら、こうした時にバクテリアに代表されるよ
うな有機物の死骸が基板１表面に付着した場合、大きな
問題が生ずる。即ち、上記有機物中には燐が含まれてい
るため、熱処理工程ではこの燐が拡散源となり、通常の
ウェハプロセス工程を完了した時点では大きさが数μｍ
でかつその表面濃度が約１０ ｃｒｎ と非常に高
濃度になっている場合がある。例えば、第２図に示す如
く有機物の死骸１１が埋め込みチャ木ル用の第２のＮ
＠４に付着１．．た場合、通常のウェハプロセス工程
を完了した時点では、その地点での濃度は他の地点より
濃くなり、その地点での表面電位が深くなる。従って、
転送されてきた電荷は、そこで一部トラップされ電荷の
転送損失をもたらす。However, in such a case, if dead organic matter such as bacteria adheres to the surface of the substrate 1, a big problem will occur. In other words, since the above organic matter contains phosphorus, this phosphorus becomes a diffusion source during the heat treatment process, and when the normal wafer processing process is completed, the size is several μm.
In some cases, the surface concentration is as high as about 10 crn. For example, as shown in FIG. 2, the dead organic matter 11 is buried in the second N
Attached to @4 1. ．． In this case, when the normal wafer processing steps are completed, the concentration at that point is higher than other points, and the surface potential at that point becomes deeper. Therefore,
Some of the transferred charges are trapped there, resulting in a charge transfer loss.
また、例えばＮａ 等の金属不純物が基板１表面に付
着した場合、熱処理工程終了後ではそれらは結晶欠陥に
なる。そして、これらの結晶欠陥には、酸素イオンが供
給されると成長していく傾向があり、通常のウェハプロ
セス工程終了時点には数μｍ〜数十μｍになる場合があ
る。Furthermore, if metal impurities such as Na are attached to the surface of the substrate 1, they will become crystal defects after the heat treatment process is completed. These crystal defects tend to grow when oxygen ions are supplied, and may reach several micrometers to several tens of micrometers at the end of a normal wafer process.
その結果、こうした結晶欠陥１２が感光画素用のＮ 層
３に存在した場合、再生画面上では白点となる。また、
結晶欠陥ｚ２が埋め込みチャ木ル用の第２のＮ １１
１４にあった場合には、再生画面上では白線となり画像
不良を招く。As a result, if such a crystal defect 12 exists in the N layer 3 for the photosensitive pixel, it will appear as a white spot on the reproduced screen. Also,
The second N 11 for the crystal defect z2 is embedded
14, a white line appears on the playback screen, causing image defects.
こうしたことから、基板１の地肌は出来る限り露出しな
いようにし、なおかつ酸素イオンが基板表面に供給され
ないようにすることが望まれている。For these reasons, it is desired to prevent the bare surface of the substrate 1 from being exposed as much as possible and to prevent oxygen ions from being supplied to the surface of the substrate.
本発明は上記事情に鑑みてなされたもので、工程の途中
で半導体基板表面が露出するのを回避し、有機物等によ
る汚染に起因する電荷の転送損失をなくすとともに、基
板への酸素供給に起因する画像不良を回避１．得る固体
撮偉装置の製造方法を提供することを目的とする。The present invention was made in view of the above circumstances, and it avoids exposing the semiconductor substrate surface during the process, eliminates charge transfer loss caused by contamination with organic substances, etc., and eliminates charge transfer loss caused by oxygen supply to the substrate. Avoiding image defects 1. The object of the present invention is to provide a method for manufacturing a solid-state imaging device.
本発明は、熱酸比換と耐酸化性膜からなる２層構造のバ
ッファ絶縁膜を、フィールド酸化膜を形成する際のマス
ク材として用い、かつ更に出力トランジスタ領域のゲー
ト絶縁膜及び電荷の転送路の絶縁膜として用いることに
より、画像不良に関連する基板表面を通常のウェハ工程
で露出しないようにし、もって電荷の転送損失の解消、
画像不良の回避を図ったことを骨子とする。The present invention uses a two-layered buffer insulating film consisting of a thermal acid conversion film and an oxidation-resistant film as a mask material when forming a field oxide film, and further uses a gate insulating film in an output transistor region and a charge transfer film. By using it as an insulating film for the circuit, it prevents the substrate surface related to image defects from being exposed during normal wafer processing, thereby eliminating charge transfer loss.
The main point is to avoid image defects.
以下、本発明をインターライン転送方式イメージセンサ
の製造に適用した場合について第１図（ａ）〜（至）を
参照して説明する。なお、同図（ａｌ〜σ）において、
左側の図はフィールド領域を、中央の図は感光画素領域
を、右側の因は出力トランジスタ領域を夫々示す。Hereinafter, a case in which the present invention is applied to manufacturing an interline transfer type image sensor will be described with reference to FIGS. In addition, in the same figure (al~σ),
The figure on the left shows the field area, the middle figure shows the photosensitive pixel area, and the figure on the right shows the output transistor area.
（１） まず、例えばＮ型のシリコン基板２１上に９
５０℃で熱酸化して厚さ約４００Ｘ程度の酸化膜２２を
形成した後、その上に厚さ約７００λ程度のシリコン窒
化膜２３を堆積し、２層構造のバッファ絶縁膜を形成し
た（第１図（ａ１図示）。(1) First, for example, place 9 on an N-type silicon substrate 21.
After forming an oxide film 22 with a thickness of about 400X by thermal oxidation at 50°C, a silicon nitride film 23 with a thickness of about 700λ was deposited thereon to form a buffer insulating film with a two-layer structure. Figure 1 (a1 diagram).
つづいて、前記基板２１に例えばボロンをイオン注入し
、熱拡散することにより浅いＰウェル領域２４ａ１深い
Ｐウェル領域２４ｂ を所定の位置に形成した（第１
図（ｂ）図示）。次いで、Ｐウェル領域２４ｍ に感
光画素部用の第１のＮ 層２５を、他方のＰウェル領域
２４ｂ Ｋ前記Ｎ＋層２５からの信号電荷を読み出す
ための埋め込みチャネル用の第２ＯＮ＋層２６及び画素
分離用のＰ 領域２７を夫々形成した。更に、感光画素
領域、出力トランジスタ領域を除く前記シリコン窒化Ｉ
Ｊ２３を選択的にエツチングした後、フィールド酸化を
行なってフィールド領域に厚いフィールド酸化膜２８を
形成した（第１図（ｅ）図示）。Next, boron, for example, was ion-implanted into the substrate 21 and thermally diffused to form a shallow P-well region 24a1 and a deep P-well region 24b at predetermined positions (first
Figure (b) shown). Next, a first N layer 25 for a photosensitive pixel portion is placed in the P well region 24m, and a second ON+ layer 26 for a buried channel for reading signal charges from the N+ layer 25 and a pixel isolation layer are placed in the other P well region 24b. A P region 27 was formed for each. Furthermore, the silicon nitride I except for the photosensitive pixel area and the output transistor area
After selectively etching J23, field oxidation was performed to form a thick field oxide film 28 in the field region (as shown in FIG. 1(e)).
（２）次に、感光画素領域の窒化膜２３上に第１層目の
転送電極２９ｍ、２９ｂ を、かつ出力トランジスタ
領域の窒化膜２３上にゲート電極３０を夫々形成した。(2) Next, first layer transfer electrodes 29m and 29b were formed on the nitride film 23 in the photosensitive pixel region, and a gate electrode 30 was formed on the nitride film 23 in the output transistor region.
つづいて、これら電極２９ｍ、２９ｂ、３０の上部を低
温ウェット法で酸化し、酸化膜３１を形成し念。次いで
、第２城目の転送電極３２を形成した後、上記低温ウェ
ット法で再度酸化１７、酸化膜３３を形成した（第１図
（ｄ）図示）。この際、感光画素領域の光入射部３４、
出力トランジスタ領域のソース／ドレイン部３５はほと
んど酸化されないため、シリコン窒化膜２３が露出され
ている。更に、前記転送電極２９８，２９ｂ 及びゲ
ート電極３Ｑをマスクとして上記光入射部３４、ソース
／ドレイン部３５のシリコン窒化膜２３をＣＤＢ（Ｃｈ
ｅｍｉｃａｌＤｒｙ ＢｔｃｈｉｎＩＩ）法で選択的忙
除去した。この際、前記電極２９ａ、２９ｂ、３０上は
酸化膜ｓｌ（又は３２）で覆われているため、これらの
電極はエツチングされない（第１図（ｅ１図示）。なお
、同図（ｅｌで上記シリコン窒化膜２３を選択的に除去
するのは、ソース／ドレイン部３５の後記Ｎ 層をＡ
Ｄ Ｓ （Ａｓ Ｄｏｐｅｄ Ｐｏ１ｙ Ｓｉ）で形成
するのと、工程の最終段階でのシンター効果を充分にも
たせるためである。Next, the upper parts of these electrodes 29m, 29b, and 30 are oxidized by a low-temperature wet method to form an oxide film 31. Next, after forming the second transfer electrode 32, an oxide film 17 and an oxide film 33 were formed again by the above-mentioned low-temperature wet method (as shown in FIG. 1(d)). At this time, the light incident part 34 of the photosensitive pixel area,
Since the source/drain portion 35 in the output transistor region is hardly oxidized, the silicon nitride film 23 is exposed. Furthermore, using the transfer electrodes 298, 29b and the gate electrode 3Q as a mask, the silicon nitride film 23 of the light incident part 34 and the source/drain part 35 is coated with CDB (Ch).
Selective removal was performed using the chemical Dry Btchin II) method. At this time, since the electrodes 29a, 29b, and 30 are covered with the oxide film sl (or 32), these electrodes are not etched (shown in FIG. 1 (el)). The purpose of selectively removing the nitride film 23 is to remove the later-described N layer of the source/drain portion 35 by A.
This is because it is formed from D S (As Doped PolySi) and to provide a sufficient sintering effect at the final stage of the process.
（３）次に、ゲート電極３ｏをマスクとして出力トラン
ジスタ領域のＰウェル領域２４ｂ Ｋｎ型不純物を導
入し、Ｎ 型のソース、ト°レイン領域３６．３７を形
成した。つづいて、 ＣＶＤ法により全面に低温酸化膜
３８を堆積した後、前記ソース、ドレイン領域３６．３
７に対応する低温酸化膜３８を選択的に除去し、コンタ
クトホール３９，３９を形成した（第１図（ｆ１図示）
。次いで、全面に例えばＡＪ蒸着１．た後、パターニン
グし感光画素領域には第１のＮ 層２３に対応する部分
が開口された光シールド膜４０を、かつ出力トランジス
タ領域にはコンタクトホール３９，３９を介してソース
ト９レイン領域３６゜３７に夫々接続する配線４１．４
１を形成した。(3) Next, using the gate electrode 3o as a mask, Kn-type impurities were introduced into the P-well region 24b of the output transistor region to form N-type source and train regions 36 and 37. Subsequently, after depositing a low-temperature oxide film 38 on the entire surface by CVD method, the source and drain regions 36.3 are
The low-temperature oxide film 38 corresponding to No. 7 was selectively removed to form contact holes 39 (FIG. 1 (f1 diagram)).
. Then, for example, AJ vapor deposition 1. After patterning, a light shield film 40 with an opening corresponding to the first N layer 23 is formed in the photosensitive pixel region, and a source 9 rain region 36° is formed in the output transistor region through contact holes 39, 39. Wiring 41.4 connected to 37 respectively
1 was formed.
更に％例えばプラズマシリコン窒化膜（保護膜）４２を
堆積し、所望のイメージセンサを製造した（第１図史）
及び第３図図示）。ここで、第３図は第１図ψ）の平面
図である。第３図において、５ｚ・・・は列状に設けら
れた垂直転送路を、５２・・・はこれら垂直転送路５１
間に設けられた複数の画素５３・・・からなる感光画素
領域を、５４は水平転送路を、５５はフィールド領域を
、５６は出力トランジスタ領域を夫々示す。Furthermore, a plasma silicon nitride film (protective film) 42, for example, was deposited to manufacture the desired image sensor (Fig. 1).
and shown in Figure 3). Here, FIG. 3 is a plan view of FIG. 1 ψ). In FIG. 3, 5z... indicates vertical transfer paths provided in a row, and 52... indicates these vertical transfer paths 51.
54 is a horizontal transfer path, 55 is a field area, and 56 is an output transistor area.
しかして、本発明によれば、画像不良に関連すふ光入射
部３４、ソース／ドレイン部３５等のシリコン基板２１
の表面を、通常のウニへ工程の途中で１回も露出させｋ
いため、例えばウェハ処理工程で使用する処理液や薬品
などの汚染にさらされることはない。従って、バクテリ
ア等の有機物の死骸などに起因して局部的に基板濃度が
高くなってその表面電位が深くなることはなく、電荷の
転送損失を回避できる。According to the present invention, the silicon substrate 21 includes the light incident part 34, the source/drain part 35, etc., which are related to image defects.
The surface of the sea urchin is exposed to normal sea urchins even once during the process.
Therefore, it is not exposed to contamination from processing liquids or chemicals used in the wafer processing process, for example. Therefore, the substrate concentration will not locally increase due to dead organic matter such as bacteria, and the surface potential will not deepen, and charge transfer loss can be avoided.
また、バッファ絶縁膜の一部を構成するシリコン窒化膜
２３により基板表面か常に覆われているため、基板表面
への酸素供給はなされず、結晶欠陥の成長を抑制できる
。虹に、酸化膜２２を低温（９５０℃）で熱酸化するこ
とにより形成するため、結晶欠陥の成長を抑制できる。Further, since the substrate surface is always covered with the silicon nitride film 23 forming a part of the buffer insulating film, oxygen is not supplied to the substrate surface, and the growth of crystal defects can be suppressed. Since the oxide film 22 is formed by thermal oxidation at a low temperature (950° C.), growth of crystal defects can be suppressed.
従って、結晶欠陥に起因する画像不良を回避できる。Therefore, image defects caused by crystal defects can be avoided.
なお、上記実施例では酸化膜２２を９５０℃で熱酸化し
た場合について述べたが、これに限らず、１０００℃以
下なら酸化膜形成に伴う結晶欠陥の成長を抑制できる。Incidentally, in the above embodiment, the case where the oxide film 22 is thermally oxidized at 950° C. is described, but the present invention is not limited to this, and if the temperature is 1000° C. or lower, the growth of crystal defects accompanying the formation of the oxide film can be suppressed.
また、上記実施例では耐酸化性膜としてシリコン窒化膜
を用いたが、これに限定されるものではない。Further, although a silicon nitride film is used as the oxidation-resistant film in the above embodiment, the present invention is not limited to this.
以上詳述した如く本発明によれば、有機物等による汚染
に起因する電荷の転送損失を解消するとともに、基板へ
の酸素供給に起因する画像不良を回避し得る高信頼件の
イメージセンサ等の固体撮像装置を製造する方法を提供
できる。As described in detail above, according to the present invention, it is possible to eliminate charge transfer loss caused by contamination with organic substances, etc., and to avoid image defects caused by oxygen supply to the substrate. A method of manufacturing an imaging device can be provided.
第１図（ａ）〜（２）は本発明の一実施例に係るインタ
ーライン転送方式イメージセンサの製造方法を工程順に
示す断面図、第２図は従来のインターライン転送方式イ
メージセンサの断面図、第３図は第１図η）の平面図で
ある。
２１・・・Ｎ型のシリコン基板、２２，３１．３３・・
・酸化膜、２３・・・シリコン窒化膜、２４ｍ、２４ｂ
・・・Ｐウェル領域、２５．２６・・・Ｎ１−１２７・
・・Ｐ＋領域、２ Ｂ ＝−７イー ７Ｌ／ド酸化膜、
２９ｍ、２９ｂ。
３２・・・転送電極、３０・・・ゲート電極、３４・・
・光入射部、３５・・・ソース／ドレイン部、３６・・
・ｒ型のソース領域、３７・・・Ｎ 型のドレイン領域
、３８・・・低温酸化膜、３９・・・コンタクトホール
、４０・・・光シールド膜、４１・・・配線、４２・・
・保護膜。
第２図
第３凹FIGS. 1(a) to (2) are cross-sectional views showing the manufacturing method of an interline transfer type image sensor according to an embodiment of the present invention in order of steps, and FIG. 2 is a cross-sectional view of a conventional interline transfer type image sensor. , FIG. 3 is a plan view of FIG. 1 η). 21... N-type silicon substrate, 22, 31.33...
・Oxide film, 23...Silicon nitride film, 24m, 24b
...P well region, 25.26...N1-127.
...P+ region, 2 B = -7E 7L/de oxide film,
29m, 29b. 32... Transfer electrode, 30... Gate electrode, 34...
・Light incidence part, 35... Source/drain part, 36...
- R type source region, 37... N type drain region, 38... low temperature oxide film, 39... contact hole, 40... light shield film, 41... wiring, 42...
·Protective film. Figure 2 3rd recess
Claims (3)
おいて、Ｐウェル領域を形成するためのイオン注入時の
バッファ絶縁膜を、熱酸化膜と耐酸化性膜の２層構造と
し、このバッファ絶縁膜をフィールド領域のフィールド
酸化膜を形成する際のマスク材として用いるとともに、
更に出力トランジスタ領域のゲート絶縁膜及び電荷の転
送路の絶縁膜として用いることを特徴とする固体撮像装
置の製造方法。(1) In a method for manufacturing a solid-state imaging device having a P-well structure, the buffer insulating film used during ion implantation to form the P-well region has a two-layer structure of a thermal oxide film and an oxidation-resistant film, and this buffer insulating film is The film is used as a mask material when forming a field oxide film in the field region, and
The method for manufacturing a solid-state imaging device further comprises using the method as a gate insulating film in an output transistor region and an insulating film in a charge transfer path.
されるシリコン酸化膜を用いることを特徴とする特許請
求の範囲第１項記載の固体撮像装置の製造方法。(2) A method for manufacturing a solid-state imaging device according to claim 1, characterized in that a silicon oxide film formed in a low temperature process of 1000° C. or less is used as the thermal oxide film.
特徴とする特許請求の範囲第１項記載の固体撮像装置の
製造方法。(3) A method for manufacturing a solid-state imaging device according to claim 1, characterized in that a silicon nitride film is used as the oxidation-resistant film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60045131A JPS61203670A (en) | 1985-03-07 | 1985-03-07 | Production of solid-state image pick-up device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60045131A JPS61203670A (en) | 1985-03-07 | 1985-03-07 | Production of solid-state image pick-up device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61203670A true JPS61203670A (en) | 1986-09-09 |
Family
ID=12710715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60045131A Pending JPS61203670A (en) | 1985-03-07 | 1985-03-07 | Production of solid-state image pick-up device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61203670A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0492144A2 (en) * | 1990-11-26 | 1992-07-01 | Matsushita Electronics Corporation | Charge-coupled device and solid-state imaging device |
| US5424775A (en) * | 1991-03-06 | 1995-06-13 | Matsushita Electronics Corporation | Solid-state image pickup device and method of manufacturing the same |
| JP2004502297A (en) * | 2000-06-27 | 2004-01-22 | ダルサ、コーポレーション | Method of manufacturing charge-coupled image sensor |
-
1985
- 1985-03-07 JP JP60045131A patent/JPS61203670A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0492144A2 (en) * | 1990-11-26 | 1992-07-01 | Matsushita Electronics Corporation | Charge-coupled device and solid-state imaging device |
| US5241198A (en) * | 1990-11-26 | 1993-08-31 | Matsushita Electronics Corporation | Charge-coupled device and solid-state imaging device |
| US5302545A (en) * | 1990-11-26 | 1994-04-12 | Matsushita Electronics Corporation | Method of making charge-coupled device and solid-state imaging device having an ONO transfer gate insulating film |
| US5424775A (en) * | 1991-03-06 | 1995-06-13 | Matsushita Electronics Corporation | Solid-state image pickup device and method of manufacturing the same |
| JP2004502297A (en) * | 2000-06-27 | 2004-01-22 | ダルサ、コーポレーション | Method of manufacturing charge-coupled image sensor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH05206434A (en) | Solid state image sensor and fabrication thereof | |
| JPH09120965A (en) | Manufacture of semiconductor device | |
| JPH10503328A (en) | Electronic device manufacturing method | |
| JPS61203670A (en) | Production of solid-state image pick-up device | |
| KR100259948B1 (en) | Semiconductor device and manufacturing method thereof | |
| JPS5922342A (en) | Manufacture of semiconductor device | |
| JP2917918B2 (en) | Method for manufacturing semiconductor device | |
| JPS6115595B2 (en) | ||
| JPS62216322A (en) | Manufacture of semiconductor device | |
| JPS5923468B2 (en) | Manufacturing method of semiconductor device | |
| JPH06140410A (en) | Manufacture of semiconductor device | |
| JPH06326183A (en) | Manufacture of semiconductor device | |
| JPH08162523A (en) | Semiconductor device, and its manufacture | |
| JPS6376377A (en) | Manufacture of semiconductor integrated circuit device | |
| JPH0794721A (en) | Semiconductor device and manufacture thereof | |
| JPS6164159A (en) | Manufacture of solid-state image pickup device | |
| JP2890550B2 (en) | Method for manufacturing semiconductor device | |
| JPS59222939A (en) | Semiconductor device | |
| JPH0479336A (en) | Production of semiconductor device | |
| JPH0522397B2 (en) | ||
| JPS60176240A (en) | Manufacture of semiconductor device | |
| KR100872989B1 (en) | Image sensor and method for manufacturing thereof | |
| JP2936826B2 (en) | Solid-state imaging device | |
| JPS60249362A (en) | Manufacture of solid-state image pickup device | |
| JPS62263658A (en) | Semiconductor device and manufacture thereof |