JPS61203648A - Circuit apparatus having solder connector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application This invention relates to electrical connections between a microelectronic chip and its supporting substrate. More specifically, the present invention provides for the operation of microelectronic chips in which denser solder can be used during the cycles in which the chip is heated and cooled without creating unacceptable shear stresses in the connections. A novel solder connection configured to allow use of larger size microelectronic chips having a connection matrix and a method of manufacturing such a solder connection.

B. SUMMARY OF THE DISCLOSURE In accordance with the present invention, a microelectronic chip is electrically connected to a substrate by elongated solder posts created by solder dams on the surface of the chip. Solder dams are provided on at least some of the connection pads on the surface of the chip. Since the bending of the solder connection can be increased by increasing the length of the solder posts, the size of the matrix of such solder posts can be increased considerably.

C1 Prior Art The rapid advances in integrated circuit device fabrication technology over the past twenty years have made it possible to implement very complex circuits on a single silicon chip, including a large number of independent circuit elements.

A typical chip for solder connection is a square with a side of approximately 6.4 mm, so it is a connection point for electrically connecting the chip to external circuitry in order to send and receive data or receive and receive operating power. The solder pads need to be very small. FIG. 2 is an enlarged perspective view illustrating a conventional technique commonly used for mounting the chip 10 on a substrate, and FIG. 3 is a cross-sectional view thereof. Typically, a silicon chip has microelectronic circuitry on only one side. A matrix of downwardly projecting solder balls 12 for connecting microelectronic circuits is connected in a manner already widely known. Such tiny solder balls collapse somewhat upon connection, providing the chip 10 with a connection with controlled collapse, which is commonly referred to in the art as a C-4 connection or C-4. .

The C-4 solder balls are placed in contact with a substrate 14 having a corresponding matrix of solder connection pads 16. Solder connection pads 16 are substantially coplanar with the top surface of the substrate.

Substrate 14 can be a multilayer ceramic structure of the type described in U.S. Pat. No. 4,245,273. Such a substrate includes peripheral connection pads 18, input/output and power pads (not shown) on the underside of the substrate, and horizontally and vertically extending conductive tracks 20.24. Conductive path 20
．． 24 extend through the interior of substrate 14 to interconnect chip 10 and connection pads 16 to various input/outputs and power supplies as desired. An example of such a board is
IBM Technical Disclosure Statement, April 1982
Disclosure Bulletin) Vol.
24. No. 11A, Hubacher's document entitled "SharedECPad Design" (No. 5554).
(pages 5557).

To connect chip 10 to substrate 14, solder balls 12 are placed in contact with connection pads 16, the ambient temperature is raised to the melting temperature of the solder, and the solder is placed in a third
Reflow (reflo%I) to form short connecting posts 26 of the shape shown in the figure.

As a representative example of the prior art, such a connecting column 26 (i
') Length it, 0.025 mm + J mail to o, 050
millimeters, or approximately half the diameter of the solder ball used. The term "solder" as used herein is 20
It has a melting temperature of 0℃ to 320℃, and the main component is lead (40℃).
% to 95%) and tin (5% to 60%).

D1 PROBLEM TO BE SOLVED BY THE INVENTION C-4 Solder connections have been widely used to connect silicon devices to substrates in the manner shown in FIGS. 2 and 3; The scope has been limited to smaller size chips that require only a limited number of connections to the substrate. Thermal expansion of the substrate 14 and the chip 10
This limitation is due to the shear strain created in the C4 bond due to the difference in thermal expansion of the C4 bond. The difference between chip expansion and substrate expansion that occurs between room and operating temperatures must be accommodated by the deformation of the solder posts 26. The allowable deformation knots are governed by the given fatigue cycle life of the joint. The maximum shear displacement δ of the joint is given by the following equation:

In the above equation, L is the outermost dimension of the C-4 connector matrix, α and C5 are the coefficients of thermal expansion of the silicon device and substrate, and ΔT is the temperature rise from room temperature to operating temperature. It has been previously recognized that as the height h of the solder post 26 increases, the shear strain γ decreases according to the following equation.

δ Here, δ is the amount of shear displacement of the solder column in question.゛C-
The performance of the 4-connector is determined by reference to the maximum shear strain experienced by the outermost C-4 connector when operating with a given combination of chip and substrate. Therefore, for a given maximum allowable shear strain, increasing the height h of the C-4 connections will correspondingly increase the overall size of the matrix of C-4 connections and
The allowable size of the device itself is concomitantly increased. Larger size chips perform more functions on the chip and increase the degree of integration, thereby achieving increased operating speed and manufacturing efficiency.

Known techniques attempting to increase the length of connections between a chip and its substrate are disclosed in U.S. Pat.
It is disclosed in No. 04. However, simply increasing the height of the C-4 connector creates additional problems, making it difficult to use larger chips. For example, the connector deforms during temperature cycling, so The possibility of electrical shorts occurring between densely packed C-4 connections increases. It is therefore necessary to avoid the tendency of the C-4 connections to spread out and touch each other when very little space is required between the connections.

The main purpose of the present invention is to provide an extended solder post connection which increases the size of electronic circuit devices and prevents electrical shorts between the connections due to distortion during operation or solder paste flow during the manufacturing process. An object of the present invention is to provide an electronic circuit device having a physical structure.

Another object of the present invention is that each connection point dams flowing solder when the chip is attached to a board, either when the solder is first reflowed or when the solder is reflowed to replace the chip. An object of the present invention is to provide a new connector structure including means for the purpose of the present invention and a method for forming the same.

Another object of the present invention is to provide a connector and method for manufacturing the same that can be used with known techniques for manufacturing substrates for holding and electrically connecting microscopic quantum chips.

Means for Solving the E0 Problem The present invention improves the height of C-4 connections without increasing the spacing between the connections and without increasing the tendency of longer connections to create electrical shorts. Provide technology to increase

According to one embodiment of the method of the invention, by providing at least some of the connections with dam means surrounding the connections,
On an electronic circuit device having a matrix of electrical connections,
A solder connection is formed.

Said dam means receives molten solder therein during attachment of the electronic circuit device to a substrate having a matrix of electrical connections corresponding to said electrical connections, or upon removal of the electronic circuit device from the substrate. Therefore, an open space is defined in the center. Molten solder is then introduced into the open space of the dam means of the electronic circuit device and cooled to form an elongated solder column within the dam means with exposed contact surfaces. To join the substrate and the electronic circuit device, the electronic circuit device is placed on the substrate such that the solder posts on the electronic circuit device are in contact with the corresponding connections on the substrate, and the assembly thus formed The body is heated to melt the solder and the solder posts melt and electrically connect the electronic circuit device to the board.

In accordance with the method of the invention, a layer of electrically insulating material is provided on the surface of the electronic circuit device, surrounding the connection points of the electronic circuit device, and passing through said layer so as to define said central open space. By providing a plurality of openings, a dam means for damming the molten solder is formed. The expansion coefficients of the insulator material and solder are chosen such that the apertures forming the dam means at least partially separate from the solder pillars when the solder cools, so that the solder does not disturb the solder during thermal expansion or contraction. Provide a gap in which the pillar can move.

F. EXAMPLES Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The same reference numerals represent the same elements in each of the drawings.

FIG. 1 shows an embodiment of the invention. First, eight layers 28 of photosensitive polymer or photosensitive dielectric epoxy are formed on the bottom surface of the electronic circuit chip 10, and the thickness of the eight layers 28 is approximately 0.050.
A zero order via hole 3o having a thickness of millimeter to 0.200 millimeter is drilled through layer 28 using photolithographic techniques. Solder is deposited within the via hole 30 to provide a solder ball or solder column having a longer axial dimension than known in the prior art. When a chip formed in this manner is bonded to substrate 14 as shown in FIG. 1, longer connections 26 are obtained, allowing for more densely packed C-4 connections. You can use larger chips than you have. In addition, one layer 28 connects the chip 10 to the substrate 14.
It serves as a means to at least partially dam the flow of solder during bonding and flow, thereby reducing the possibility of solder spreading causing short circuits.

4 and 5 show an example of an arrangement in which an electrically insulating and easily deformable ring 32 is provided around each connection pad 16 of the substrate 14. FIG. υ puffer 32 can be formed from layers of a suitable material, such as photosensitive polyimide, using common photolithographic techniques. ring 32
After forming the ring, the central open space of the ring can be filled with solder by solder dipping or wave soldering techniques well known to those skilled in the art. The ring thus functions as a solder dam as described above.

As the chip 10 shown in FIG.
is elastically deformed. In the case of a polyimide ring with a height h□ of approximately 0°064 mm, an inner diameter r1 of approximately 0.057 mm, and an outer diameter r2 of 0.079 mm,
Connection body 26 between ring 32 and the bottom surface of chip 1o
The shear strain in the unretained portion of is reduced to about 25%. In this state, the radial thickness is approximately 0°0
The 20 mm ring 32 deforms the lower portion of the connector 26 slightly as shown in FIG. The thicker the ring, the smaller the change in shear strain applied. This modification of the C-4 connector increases the chip size by approximately 25% without violating the maximum shear strength limit.

The improvement in shear strain is demonstrated in the simple analysis below. The balance of shear forces on the top surface of each ring 32 requires:

In the above formula, τ. is the shear stress of the unretained portion of the C-4 solder pillar, which is assumed to be a constant value. r□ is C
-4 is the radius of the solder pillar, assumed to be a cylinder. τ is the shear stress in the solder within the ring 32, and is assumed to be a constant value. τ is the shear stress in the ring 32 and is assumed to be a constant value. r2 is the outer diameter of the ring 32.

Since a polymer such as polyimide can be treated as a perfectly elastic body, δ1 τ = μ ·−(2) p ph,. In the above equation, μ is the shear modulus of the polymer, δ1 is the displacement of the top of ring 32, and hl is the height of ring 32.

The strain in this part within the connecting body 26 is about 1%, and the solder material can be considered to be a work-hardening plastically deformable material, so τ=A+Bγn(3) In the above, A, B, and n is a constant and γ
is the shear strain. ” 5 / 95 S n /
Mechanical properties of Pb solder and solder containing impurities'' (
5/ 95 S n P b 5older an
dSolder Containing Impuri
Rathore, Yih and Edenfeld
IBM technical report by
Report) Based on the information disclosed in TR221009 (1970), the approximate values of A, B and n are:
A is 98 kg/cx for approximately 1% strain
, B is 280 kg/mouth", and rl is approximately 0.5.

Combining equations (1), (2) and (3) leads to:

h,=h δ=δ□+δ. Then, it becomes.

rl is 0.057 mm, hi is both 0.064 mm, μ is 18. I X 1Q
for various r
δ for the value of 2. The values of and δ1 are shown below.

r2(no) δ, (mm) δ, (III,
l) δ. /δ0.079 48.3 X 10
-' 13.7 X 10-' 0.780.09
5 53.1 x 10-' 9.14 x 10
-' 0.860.122 56.6 x 10-
5 5.33 x 10-' 0.91 Note that for an array of connection pads with center-to-center spacing of 0.228 mm, values of r2 greater than 0.114 mm have no meaning. It takes. However,
This example can be used to represent the stiffness of a solid polymer layer with cylindrical apertures spaced 0.degree. 114 millimeters apart. .

δ. The value of /δ is the shear strain in the unretained portion of the connection 26 that is not retained by the ring 32 as compared to the standard type connection 26 that is not retained by the ring shown in FIG. gives an indication of the decrease in For the thinnest polymer ring with a wall thickness of 0.020 millimeters, shear strain is reduced by about 22%. If the chip thickness were increased to accommodate the standard maximum allowable shear strain, the new chip size would be approximately 25% larger than the original size.

Figures 6 to 15 are further away from the solder column at operating temperature, thus providing the lower part of the solder column with greater freedom of movement and reducing shear strain more effectively with the solder dam. An example of the formed configuration is shown. A layer 34 of electrical insulator having a coefficient of expansion greater than that of the substrate 14 is provided on the top surface of the substrate 14.

For example, a polyimide plastic layer having a thickness in the range 0.905 mm to 0.125 mm can be provided. Such a polyimide plastic layer has an expansion coefficient α of 25 x 10'-'/K''.
92% alumina CA on the substrate 14.
Q203) When ceramic is used, the expansion coefficient α5 of the substrate 14 is 6.5×10−′/°. If an array of vertical cylindrical via holes 36 as shown in FIGS. 6 and 7 is provided in the layer 34 described above, each via hole 3
The top of 6 will expand against the bottom of the via hole when the substrate 14 and adhesive layer 34 are brought back from soldering temperature to room temperature (see FIG. 8). This is caused by bi-axial tensile stresses in the upper layer, assuming good adhesion between layer 34 and substrate 14.

When a substrate with such layer 34 is bonded to chip 10 in the manner shown in FIG. do. Additionally, the solder shrinks more than the substrate, creating larger voids. The coefficient of thermal expansion of lead solder containing 5% tin is approximately 25 x 10-'/'. Thus, both the polyimide polymer wall 38 and the solder move away from each other.

The structure shown in FIGS. 6-9 is formed by depositing a layer of electrically insulating material with a large coefficient of expansion on the top surface of substrate 14. Apertures having the desired C-4 connection dimensions are provided in this layer.

Apertures are formed through the layers leading to the underlying solder pads 16 and conductive tracks 20 that electrically connect the C-4 connections. These apertures therefore function as solder dams in the manner already described. These openings are then filled with molten solder by vapor soldering, dip soldering, wave soldering, or other known soldering techniques. Next, normal C-4
The silicon device provided with solder balls is placed on the substrate, and after the solder is reflowed and cooled to room temperature, the structure shown in FIG. 9 is obtained.

Upon cooling from reflow temperature to room temperature, the silicon of chip 10 shrinks less than the ceramic material of substrate 14, so that solder connections 26 are severely distorted, as shown in FIGS. 10-15. When the chip is brought up to its operating temperature, the severely distorted solder connections, ie the solder connections at the periphery of the chip, are removed from the inner wall 38 of the via hole 36, where the connectors are opposite at room temperature. Deformed in the direction of separation. The distance that point p of the C-4 solder post at the level of the top surface of layer 34 moves before the C-4 solder post hits the inner wall on the opposite side of via hole 36 is 2Δ', or approximately 2 of Δ'. It's double. In this case, Δ′ is via hole 3
The solder pillar 26 in the center of the chip is estimated by considering the elasticity of the upper part of C-4 and the shrinkability of the C-4 solder pillar.

Since the polyimide material of layer 34 is rigid against the plastically deforming solder material, it is necessary to avoid deforming the C-4 pillars into contact with the inner wall 38 of the via hole 36.

When the C-4 solder post comes into contact with the inner wall of the via hole, any further displacement of the chip 10 with respect to the substrate 14 will be 34° per layer, i.e., the portion of the C-4 post above the solder dam. The radius is 0, which must be covered by deformation.
For a polyimide layer 34 having an array of via holes 36 with 0.057 mm diameter via holes having a center-to-center spacing of 0.229 mm, and a 5% tin lead solder with a solidification temperature of 300 degrees C. It is estimated that an increase in chip size on the order of 140% can be achieved without exceeding the maximum shear strain that can be applied and without all C-4 pillars touching the inner wall 38 of its via hole 36. It is being

The isolation of the C-4 pillar provided by the solder dam and which C
It is also possible according to the invention to reduce the size and spacing of the C-4 connections in view of the effective shear strain that can be achieved without -4 pillars impinging on the solder dam. The smaller and more closely arranged apertures in layer 34
It is easy to form inside. The solder balls of the chip 1o are made smaller as the distance between the C-4 connectors becomes closer. For typical chips currently in use, a polymer dam with a diameter of 0.051 mm is
．． Allows for a C-4 column radius of 0.025 mm, allowing for a center spacing of 0.100 mm for a ho of approximately 0.025 mm. This reduces the size and spacing of the C-4 connections by approximately 60%.

At the operating temperature T0 of the chip, the gap Δ between the inner wall 38 of the via hole 36 and the C-4 column in the strain-free type connection shown in FIG. 9 can be estimated by the following equation.

Δ=Ca,-(!,)(T8-To) r,+(α,-
a,, )('r s-'ro) r□(s) In the above formula, α is the expansion coefficient of the polymer, and α is the coefficient of expansion of the substrate 14.
is the coefficient of expansion of the material, α5 is the coefficient of expansion of the solder, T is the solder reflow temperature, and r is the radius of the bottom of the via hole 36 as seen in FIG. This relationship assumes that thermal strains are completely relaxed at the top surface of layer 34 (which is generally the case for structures where the thickness h8 of layer 34 is approximately equal to r□).

α and α are 25
sS is 297°C, To is 85°C, and r is 0.
057 millimeters, Δ is 46×10 −s millimeters.

The difference in coefficient of expansion between the chip 10 and the substrate 14 causes a strain on the C-4 pillar at the periphery of the chip, causing the 12th
As shown, the C-4 post may be pressed against one side of the via hole 36. At room temperature TR, the distance such a C-4 pillar must travel to reach the other side of via hole 36 is defined by the following equation:

Chip operating temperature T. , the distance that the C-4 column must travel is 2Δ as shown in FIG. Therefore, at To, the displacement δ resulting from the chip-to-substrate expansion mismatch should not be so large that the C-4 pillar contacts the inner wall 38 of the via hole 36. This relationship is expressed by the following equation.

In the above formula.

Therefore, the maximum outer dimension of the matrix of the C-4 column, the value of L, should be 2Δ=γmh, (11) This can be maximized by setting the value of h to 0.
．． Make it 086 mm ah.

For this value of , the value of L would be 9.14 millimeters, which represents an increase of approximately 140% compared to the maximum chip size currently allowed.

Figures 16 to 22 show C-
This shows an example of a configuration in which a unique structure holding four pillars is formed on a multilayer ceramic substrate. As shown in FIG. 16, a multilayer ceramic substrate includes a plurality of layers 14a-14a that are assembled and sintered to provide a unitary substrate. Conventional techniques for manufacturing ceramic substrates are disclosed. In the configuration shown in FIGS. 16-22, the final layer 40 of unsintered fresh ceramic is
A plurality of via holes 36 aligned with pads 16 and conductive paths 20, such as conductive paths 22 and connection pads 1.
Via hole 36 is pre-punched (see FIG. 17) to provide another via hole 42 aligned in line with 8.
A mask 44 is provided having an aperture 46 matching the .

Mask 44 has no openings at positions corresponding to via holes 42; via holes 36 are filled with a combustible material, such as terephthalic acid paste (see FIG. 18). Next, another mask 50 is provided having an aperture 52 that matches the via hole 42 . The mask 50 has no openings at the positions corresponding to the via holes 36, and the via holes 42 are made of molybdenum.
Filled with a conductive material such as paste. Also, in order to provide a connection path to pad 18, conductive path 2
2 is provided on the surface of layer 40 (FIG. 16).

Next, layer 40 is laminated onto the previously assembled multilayer substrates 14a-14e and sintered to form the structure shown in FIG. At this time, the combustible material 48 is burned away leaving a via hole 36 which is a space for receiving molten solder. To coat the exposed surface of the molybdenum conductive track 20, nickel or gold is plated on the bottom of the via hole 36, and then a solder ball is set into the via hole 36 and as shown in FIG. It is then reflowed to fill the pipe hole 36. As another method,
The via holes 36 can also be filled with solder and reflowed by immersion in a solder bath using ultrasound, by solder lamination, or by solder evaporation. Temporary protective coatings can also be applied to other sides of the board to avoid solder contamination. Finally, the standard C-
A chip 10 with 4 solder balls attached to its underside is placed in contact with the substrate 14, with the solder balls attached to the via holes 3
Contact with the solder in 6. The solder is thus reflowed and the extended C-4 as shown in FIG.
A pillar is made.

Via holes 36 are formed in the upper layer 40 using an embossing technique that creates a recess having a depth of 0.025 mm to 0.125 mm by pressing the upper end surface of the conductive path 20 downward with a suitable die. It is also within the scope of the present invention to do so. In some applications, the center of the connector matrix, where the shear strain is much lower than the periphery, may use regular connectors, and only the periphery of the connector matrix may use C-4 pillars with solder dams.

The reliable C-4 design currently in use uses a C-4 ball of approximately 0.127 millimeters.
A 7×17 matrix can be used with a center spacing of 0.254 mm. Using the structure shown in Figure 16, a matrix of 0.127 mm deep depressions would support a matrix of 42x42 C-4 columns at currently allowed fatigue strain levels. It can be used.

If a normal 0.127mm solder ball is bonded to a 0.127mm thick solder post in the via hole 36 as shown in Figure 10, the temperature will be approximately 297°C and the temperature will be approximately 85°C. Due to the difference in volumetric shrinkage and thermal shrinkage of the solder between the operating temperature and the
This results in a shrinkage difference ΔL/L of 56. For a via hole with a diameter of 0.127 millimeters, this shrinkage rate is approximately 99° lXl between the via hole and the C-4 column at operating temperature.
This creates an air gap Δ (FIG. 15) of 0-5 mm. As shown in FIG. 12, the outer C-4 pillar is distorted to an extreme position at room temperature, effectively touching the inner wall opposite the via hole.

Equations (8), (9), and (10) are used in FIG. )
The following conditions must be met.

In such case, if γm is equal to 0.0094 and α
b is equal to 6, 5 x 10-'/ and α
is equal to 2,5 x 10''/', then C-4
The maximum lateral displacement of the column, δ, is 177.8XIO-5 mm. If the maximum number of solder pillars on one side of the solder pillar matrix is n, and the spacing between the centers of solder pillars is a, then the value of L in equation (10) is equal to (n-1)a, so one The maximum number of solder pillars on a side can be approximately 42 in the present invention, compared to 17 in the prior art. The outermost C-4 pillar does not deform until it contacts the inner wall opposite its via hole.

FIG. 22 shows another configuration example, in which the substrate 1
4 is provided with a recess for a solder post of the type shown in FIGS. 16 to 21, while the chip 10 is also provided with a recess for a solder post of the type shown in FIG. It is provided. Chip 10 or chip 10 and substrate 1
It is within the scope of the present invention to provide such recesses or solder dams at all or only selected connection points of both connection points in FIG.

G0 Invention As described in detail, the present invention provides a novel method for manufacturing a C-4 solder connection to provide a solder connection that is superior to conventional C-4 connections. According to
Avoiding the problem of short circuits between connectors, larger size and higher density electronic chips can be used, resulting in increased integration, faster computer operation, and improved manufacturing efficiency. It can be improved.

[Brief explanation of drawings]

FIG. 1 is a partial cross-sectional view of an embodiment of the present invention, FIG. 2 is a perspective view showing a conventional chip and substrate before bonding, FIG. 3 is a partial cross-sectional view showing a conventional connection structure, and FIG. Figure 5 is a partial cross-sectional view of a structure in which ring-shaped dam means are provided on the top surface of the substrate; Figure 5 is a partial cross-sectional view showing the structure of Figure 4 deformed due to differences in thermal expansion; Figure 6; 7 is a partial cross-sectional view of a structure in which the dam means is provided by a layer of electrically insulating material on the top surface of the substrate; FIGS. 7 and 8 are cross-sectional views of a portion of the structure shown in FIG. FIG. 9 is a partial cross-sectional view of the structure of FIG. 6 during operation. Figures 10 to 15 illustrating how the inner wall of the dam means separates from the solder connection with respect to deformation of the connector due to different thermal expansions;
16 is a partial cross-sectional view of the structure of FIG. 6, illustrating the different strains of the connector at the periphery of the chip and at the center of the chip at reflow temperature, room temperature and operating temperature; FIG. Figures 17-21 are partial cross-sectional views at room temperature showing other structures in which dam means are formed in a multilayer ceramic substrate by providing a final ceramic layer with suitable apertures for receiving solder; The figure is the first
Figure 22 is a diagram illustrating a modification of the structure shown in Figure 16 in which dam means are provided both on the substrate and on the chip; It is. 10... Chip, 12... Solder ball, 14
... Board, 16.18... Connection pad, 2o,
24... Conductive path, 26... Connection body, 32...
・Ring, 3o, 36.42... Via hole. Applicant International Business Machines Corporation Agent Patent attorney Hitoshi Yamamoto (1 other person) Figure 1 Conventional technique Figure 2 Figure 3 Figure 7 Figure 8 Reflow: l change time Refushi-X
+L supply Fig. 10 Fig. 11 Fig. 12 Fig. 13 When working at home to make heated coal @ When the production temperature is good Fig. 14
Figure 15 Figure 16 Figure 18 Figure 19

Claims (1)

[Claims] (1) In an electronic circuit device having a matrix of electrical connections to be connected to a substrate, solder dam means made of electrically insulating material surrounding at least some of the electrical connections and defining a central open space; An electronic circuit device having a solder connection body, comprising: a solder post attached to the central open space and protruding from the dam means.