JPS61202400A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To attain the simultaneous writing of the same data to plural memories and therefore to reduce greatly the function test time, by driving plural memory cell selecting circuits at a time in a test mode of the memory cell function. CONSTITUTION:In a normal mode the actuation of this memory is exactly equal to that of a conventional circuit which contains no address control circuit 27. While the address signals supplied to the memory cell selecting circuits 19-22 are all set at low levels by the circuit 27 in a test mode, i.e., when the TM signal is set at a high level. Thus the circuits 19-22 deliver simultaneously signals C1-C4 of high levels to turn on the related sets of transistors TR. That is, the TR3-10 are all turned on when the TM signal is kept at a high level. Then the output signals of a data input buffer 2 are written to all memory cells 15-18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that can simultaneously write the same data to a plurality of memory cells during a functional test of the memory cells. It is something.

[Prior Art] FIG. 4 is a schematic block diagram mainly showing the electrical configuration of an input (write) circuit of a conventional semiconductor memory device.

First, the configuration of the semiconductor memory device shown in FIG. 4 will be explained. In FIG. 4, input data W is applied to a data input buffer 2 via a data write terminal 1. In FIG.

In response, the data manual buffer 2 inputs the input data W
and a signal W which is an inversion of W. The signal W output from the data input pants 72 is further connected to the transistor 3
, 5° is given to one conduction terminal of each of 7 and 9,
The signal W output from the data human buffer 2 is roughly as follows.
Applied to one conduction terminal of each of transistors 4.6.8 and 10. The output from the other conductive terminal of each of transistors 3 and 4 is amplified through a first amplifier 11 and then coupled to a one-pit memory cell 15.

Similarly, the output from the other conduction terminal of each of transistors 5 and 6 is amplified via pre-I amplifier 12 and then coupled to a 1-pit memory cell 16, and the output from the other conduction terminal of each of transistors 7 and 8 is The output from the conduction terminal is amplified via preamplifier 13 and then coupled to one pit memory cell 17, and the output from the other conduction terminal of each of transistors 9 and 10 is coupled to preamplifier 14. After being amplified through the signal, it is coupled to one pit of memory cell 18. The on/off of transistors 3 and 4 is controlled by the output signal @C1 of one memory cell selection circuit, and the on/off of transistors 5 and 6 is controlled by the memory cell selection circuit 20.
The on/off of transistors 7 and 8 is controlled by the output signal C of the memory cell selection circuit 21, and the transistors 98'3 and 10 are controlled by the output signal C2 of the memory cell selection circuit 21.
ON/OFF is determined by the output signal C4 of the memory cell selection circuit 22.
controlled by The address signal A is applied to the terminal 23, the address signal A is applied to the terminal 24, the address signal @A is applied to the terminal 25, and the address signal @A is applied to the terminal 26. These address signals cause the memory cell to be One of the selection circuits 19 to 22 is selected and driven.

Each of these memory cell selection circuits 19 to 22 is
It is assumed that the configuration is such that it is selected and driven only when two normally input address signals are both at low level. For example, in the circuit shown in FIG. 4, when address signals A and Ac are both at low level, memory cell selection circuit 19 is selected and its output signal C7 becomes high level. On the other hand, address signals A and Ac are input to the memory cell selection circuit 20, but in the above case, since Ac is at a low level, Ac is at a high level, so this memory cell selection circuit 20 selects Not done.

In general, memory cell selection circuits 2113 and 22 are also not selected in the above case.

Next, the operation of the conventional semiconductor memory device shown in FIG. 4 will be explained. When writing data, data write terminal 1
Input data W is given to . The data manual buffer 2 then outputs a complementary signal set (W, W). In this state, the signal (W).

In order for W) to reach and be written into each memory cell, transistors 3 to 10 must be on. In a conventional semiconductor memory device, 1 specified by address signals Am, Am, Ac, and Ac
One set of transistors (for example, transistors 3 and 4) is turned on by one memory cell selection circuit (for example, memory cell selection circuit 19), and data is written to only one pit of memory cell (for example, memory cell 15). It will be done. Next, by changing the address signal, other memory cell selection circuits are sequentially designated, and data is sequentially written into each memory cell one pit at a time.

Incidentally, in conventional semiconductor memory devices, memory cells are generally tested for function in a wafer state before the semiconductor memory device is assembled into a package.

This functional test is executed by exchanging signals between the memory test bag M (not shown) and the semiconductor storage device. For example, a memory tester first assigns a certain logical value (
For example, write "0"). Next, it is determined whether the memory cell is functioning normally by reading out the memory cell one pit at a time and checking whether it matches a logic value written in advance. In a conventional semiconductor memory device, writing of data to each memory cell for the above-mentioned functional test was performed via the conventional data input circuit shown in FIG.

[Problems to be Solved by the Invention] As mentioned above, in the conventional semiconductor memory device, test data had to be written into a plurality of memory cells one pit at a time during a functional test of the memory cells. As the capacity of semiconductor memory am has increased, there has been a problem in that the functional test time per semiconductor memory device has become extremely long.

Therefore, the main object of the present invention is to solve the above-mentioned problems, and to be able to simultaneously write the same data to multiple memory cells by simultaneously driving multiple memory cell selection circuits during a memory cell function test. , 1ull semiconductor memory that can significantly shorten functional test time
It is to provide.

[Means for Solving the Problems] In the semiconductor memory device according to the present invention, during normal operation, a memory cell designation signal that designates a memory cell in which data is to be written is supplied as is to the memory cell selection means. As a result, data is written only to the designated memory cell, while in the test mode, all the memory cell selection means are driven simultaneously regardless of the memory cell designation signal.

[Function] In addition to the normal writing means that selects one memory cell from a plurality of memory cells one by one and writes data, a function is provided to simultaneously drive all memory cell selection circuits. Since it is a multiple-bit memory cell, multiple bits of memory cells can be filled with the same data at the same time.

[Actual Example] FIG. 1 is a schematic block diagram showing the electrical configuration of a semiconductor memory device according to an embodiment of the present invention.

jIl! The structure of the embodiment shown in FIG. 1 is the same as the structure of the conventional semiconductor memory device shown in FIG. 4 except for the following points. That is, address signal input terminals 23 to 26
An address control circuit 27 is provided between the memory selection circuits 119 to 22, and a test mode switching signal (hereinafter, a test mode switching signal (hereinafter referred to as a signal supplied from the TM double signal input terminal 28 to the TM double signal address control circuit 27) is provided between the memory selection circuits 119 to 22. That's true.

Next, an outline of the operation of the embodiment shown in FIG. 1 will be explained. The TM double signal is a signal that rises to a high level in the test mode, and falls to a low level in cases other than the test mode (hereinafter referred to as normal mode).

First, in the normal mode, the circuit shown in FIG. 1 operates exactly the same as the conventional circuit shown in FIG. 4, which does not include the address control circuit 27. That is, when the TM double signal is at low level, the address signals Aa, A++, A
c, one memory cell selection circuit selected by A- operates to control its associated transistor set to the ON state, and inputs data to one of the memory cells specified by the above address signal in the conventional procedure. Write data.

On the other hand, in the test mode, that is, when the TM double signal rises to high level, all the address signals input to the memory cell selection circuits 19 to 22 are set to low level by the address control circuit 27. 22 simultaneously outputs a high level signal C~C6 which drives the associated set of transistors on. That is, when the TM double signal is at a high level, transistors 3 to 1o are all turned on, and the output signal (W) of the data input buffer 72 is turned on.

W) will be written to all memory cells 15-18.

Next, FIG. 2 is a circuit diagram showing details of the address control circuit 27 shown in FIG. 1.

First, the configuration of the address control circuit 27 shown in FIG. 2 will be explained. The address control circuit 27 receives the address signal from the address signal input terminals 23 to 26 shown in FIG. have.

Roughly speaking, the address signal input terminal 23 is a transistor 29.
The gate of this transistor 29 is connected to the internal node N, which is the connection point between the high pull-up resistor 38 and the drain of the transistor 37, and the source of the transistor 29 is connected to the address signal output terminal 2.
3- is connected. In addition, address signal input terminal 2
4 is connected to the drain of the transistor 30, the gate of the transistor 30 is connected to the internal node N, and the source of the transistor 30 is connected to the address signal output terminal 24-. Further, the address signal input terminal 25 is connected to the drain of the transistor 31, the gate of the transistor 31 is connected to the internal node N, and the source of the transistor 31 is connected to the address signal output terminal 25'. Further, the address signal input terminal 26 is connected to the transistor 32.
The gate of the transistor 32 is connected to the internal node N, and the source of the transistor 32 is connected to the address signal output terminal 26'.

Roughly speaking, the address signal output terminal 23' is also connected to the drain of the transistor 33.
The gate of the transistor 33 is connected to the TM signal input terminal 28, and the source of the transistor 33 is grounded. Further, the address signal output terminal 24- is also connected to the drain of the transistor 34, the gate of the transistor 34 is connected to the TM signal input terminal 28, and the source of the transistor 34 is grounded. Further, the address signal output terminal 25' is also connected to the drain of the transistor 35, the gate of the transistor 35 is connected to the TM signal input terminal 28, and the source of the transistor 35 is grounded. Also,
The address signal output terminal 26' is also connected to the drain of the transistor 36, the gate of the transistor 36 is connected to the TM signal input terminal 28, and the source of the transistor 36 is grounded. The drain of transistor 37 is connected to internal node N, its gate is connected to TM signal input terminal 28, and its source is grounded. One end of the high resistance 38 is connected to the power supply Vcc, and the other end is connected to the internal node N.

Next, the operation of the address control circuit 27 shown in FIG. 2 will be explained. First, in the normal mode, that is, when the TM double signal is at low level, transistor 11 and transistor 33
37 are in the off state.

Therefore, the internal node N is at a high level through the high resistance 38, and therefore the transistors 29 to 3
2 is turned on, the address signal output terminal 23'
Address signals from the corresponding input terminals 23 to 26 are output as they are to the corresponding input terminals 23 to 26'. That is, in the normal mode, the address control circuit 27 does not affect the normal data write operation at all.

Next, in the test mode, that is, when the TM double signal is at the level, the transistors 33 and 37 are in an on state. By appropriately selecting the on-resistance of the transistor 37 and the resistance value of the high resistance 38, the internal node N can be brought to a low level.

In this case, since the transistors 29 to 32 are turned off, the address signals of the input terminals 23 to 26 are not outputted from the output terminals 23' to 26'. On the other hand, since the transistor 33 6% L/36 is in the on state, the address signal output terminals 23' to 26' are
All of these transistors 33 to 36 are grounded and clamped to a low level. That is, in the test mode, only low level signals are applied to all of the memory cell selection circuits 19 to 22, and all of these memory cell selection circuits are selected and driven.

In the above embodiment, the memory cell selection circuit is selected only when the memory cell selection circuits 19 to 22 are of the NOR type, that is, when all the address signals input to each memory cell selection circuit are at low level. Although an example of the address control circuit 27 suitable for the case where the memory cell selection circuits 19 to 22 are configured as
An address suitable for the R type case, that is, when the memory cell selection circuit is configured to be selected when at least one of the address signals input to each memory cell selection circuit is at a high level. An example of the control circuit 27 is shown in FIG. The address control circuit 27 shown in FIG. 3 is similar to the address control circuit shown in FIG. 2 in that each conduction path of the transistors 33 to 36 is connected between the voltage source Vcc and each address signal line. It is different from 27. That is, by only slightly changing the connections of the address control circuit shown in FIG. 2, an address control circuit suitable for an OR type memory cell selection circuit can be obtained.

In addition, in the above-mentioned embodiment, 4
Although the semiconductor memory device in which data is written into pit memory cells has been described, the number of bits may be any number of bits, and the semiconductor memory device may be of any type.

In general, it is clear that the test time can be further shortened if a multi-bit parallel reading means is also provided.

[Effects of the Invention] As described above, according to the present invention, by providing an address control circuit with a simple circuit configuration, the same data can be written to multiple bits of memory cells at the same time. High-capacity semiconductor memory device that can shorten cell write time! Also, the time required for functional testing can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing the electrical configuration of an embodiment of the present invention. FIG. 2 is a circuit diagram of an address control circuit constituting an embodiment of the present invention. FIG. 3 is a circuit diagram of an address lIIIJ1m circuit constituting another embodiment of the invention. FIG. 4 is a schematic block diagram showing the electrical configuration of a conventional semiconductor memory device. In the figure, 1 is a data write terminal, 2 is a data manual buffer, 11.12.13.14 is a preamplifier, and 15.
16, 17, and 18 are memory cells. 19.20.21.22 is a memory cell selection circuit; 23.
24, 25, and 26 are address signal input terminals, 27 is an address control circuit, and 28 is a test mode switching signal input terminal. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3

Claims (2)

[Claims] (1) A data write terminal, an n (n is an integer of 2 or more) bit memory cell connected in parallel to the data write terminal, and a memory cell provided for each memory cell to which data should be written. n memory cell selection means for selecting a memory cell; memory cell designation signal generation means for generating a memory cell designation signal for designating a memory cell in which the data is to be written and applying it to the memory cell selection means; and address control means for controlling the memory cell designation signal so that all of the n memory cell selection means are simultaneously driven in a test mode. (2) In response to an external test mode switching signal, the address control means prevents the memory cell designation signal from being applied to the memory cell selection means during the test mode, and the n memory cell selection means A driving signal for simultaneously driving all of the n memory cell selection means is applied to the n memory cell selection means, and the switching means is switched to apply the memory cell designation signal to the memory cell selection means when not in a test mode. range 1
The semiconductor storage device described in .