JPS61201115U - - Google Patents

Info

Publication number
JPS61201115U
JPS61201115U JP8370985U JP8370985U JPS61201115U JP S61201115 U JPS61201115 U JP S61201115U JP 8370985 U JP8370985 U JP 8370985U JP 8370985 U JP8370985 U JP 8370985U JP S61201115 U JPS61201115 U JP S61201115U
Authority
JP
Japan
Prior art keywords
power supply
supply circuit
stabilized power
generates
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8370985U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8370985U priority Critical patent/JPS61201115U/ja
Publication of JPS61201115U publication Critical patent/JPS61201115U/ja
Pending legal-status Critical Current

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  • Control Of Voltage And Current In General (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示すブロツク図、
第2図は第1図における誤差増幅器の一例の回路
図、第3図は誤差増幅器のゲインを手動で調整す
る場合の回路図、第4図は負荷変動に応じて誤差
増幅器のゲインを自動的に調整する場合の回路図
、第5図は第4図の回路動作を説明するための波
形図、第6図は入力電圧に応じて誤差増幅器のゲ
インを自動的に調整する場合の回路図、第7図は
従来例を示すブロツク図である。 主要部分の符号の説明、1……制御回路、3…
…誤差検出回路、4……誤差増幅器、6……ゲイ
ンコントロール端子。
FIG. 1 is a block diagram showing an embodiment of the present invention.
Figure 2 is a circuit diagram of an example of the error amplifier in Figure 1, Figure 3 is a circuit diagram for manually adjusting the error amplifier gain, and Figure 4 is a circuit diagram for automatically adjusting the error amplifier gain according to load fluctuations. 5 is a waveform diagram for explaining the circuit operation of FIG. 4, and FIG. 6 is a circuit diagram when the gain of the error amplifier is automatically adjusted according to the input voltage. FIG. 7 is a block diagram showing a conventional example. Explanation of symbols of main parts, 1... Control circuit, 3...
...Error detection circuit, 4...Error amplifier, 6...Gain control terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 制御電圧に応じて一定の出力電圧を発生する制
御回路と、前記出力電圧の基準電圧に対する変動
誤差分に応じて前記制御電圧を発生する誤差増幅
器とを含む安定化電源回路であつて、前記誤差増
幅器はそのゲインが可変に構成されたことを特徴
とする安定化電源回路。
A stabilized power supply circuit including a control circuit that generates a constant output voltage according to a control voltage, and an error amplifier that generates the control voltage according to a fluctuation error of the output voltage with respect to a reference voltage, the stabilized power supply circuit comprising: The amplifier is a stabilized power supply circuit characterized by a variable gain configuration.
JP8370985U 1985-06-01 1985-06-01 Pending JPS61201115U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8370985U JPS61201115U (en) 1985-06-01 1985-06-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8370985U JPS61201115U (en) 1985-06-01 1985-06-01

Publications (1)

Publication Number Publication Date
JPS61201115U true JPS61201115U (en) 1986-12-17

Family

ID=30632582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8370985U Pending JPS61201115U (en) 1985-06-01 1985-06-01

Country Status (1)

Country Link
JP (1) JPS61201115U (en)

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