JPS61200740A - Automatic synthesis system for protocol - Google Patents

Abstract

PURPOSE:To give a specification without contradiction of logic to an incomplete protocol by dividing a state transition at every process and synthesizing the existing state transition to a state transition generated additionally at every process when the state transition of the opposite process is deficient. CONSTITUTION:An incomplete protocol specification is stored in a memory 1, an initial setting block 2 accesses the memory 1 to obtain an incomplete state transition diagram. A D conversion block 3 accesses the memory 1 to divide the state transition diagram of the process 1 into a part transmitting/ receiving a signal with a process 2 and a part transmitting/receiving a signal with a process 3, and the divided parts are stored in the memory 4. A T conversion block 5 accesses a memory 4 to produce the state transition deficient in the opposite process at every channel and it is stored in a memory 6. A C conversion block 7 accesses the memory 6 to synthesize the state transition diagram produced at every channel and the complete state transition diagram of each process is obtained and stored in a memory 8.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention inputs a protocol specification including functionally insufficient parts, automatically generates additional missing parts, and outputs a complete protocol specification. Concerning automatic synthesis of protocols.

(Prior Art) As information communication systems have become more sophisticated and diversified in recent years, the protocols used to implement these systems have become larger and more complex. For this reason, it has become increasingly important to accurately and efficiently design such large-scale protocols without logical contradictions, that is, specification errors.

Protocol verification and protocol synthesis are methods for designing protocols that operate correctly. Protocol verification detects logical contradictions, or specification errors, inherent in a designed protocol, and uses the verification results to modify the protocol. However, it only points out logical contradictions and does not provide guidelines on how to correct them, so it is insufficient for designing a correct protocol. On the other hand, protocol synthesis inputs a protocol specification that is not functionally complete but has no specification errors.
It automatically generates and supplements the missing parts and outputs a protocol specification with no logical contradictions as a whole, making it an efficient means for designing a correct protocol.

Conventionally, a method for synthesizing protocol specifications consisting of two processes has been proposed. In this conventional technology, a state transition diagram of one process is provided as a protocol without specification errors, although it is not functionally complete, a state transition diagram of the other process is automatically generated, and the entire protocol is synthesized (C, V
, Ramamoorthy and S., T., Dong.
Communication protocol synthesis:
nProtocol 5 synthesis”),
COMPSAC' 82. pp, 217-225.1
982'). This conventional technique will be explained using FIG. 19 and FIG. 2. Note that the dotted lines in FIG. 2 represent the same transition state series. FIG. 1 is an example of a protocol to be synthesized, and is a diagram illustrating the protocol specifications of a communication system consisting of process 1 and process 2. Here, the communication system may be, for example, a system in which processes 1 and 2 are a terminal device and a switch, or both may be a system in which processes 1 and 2 are connected to one C
It may be within the PU. That is, a processing unit that performs signal transmission and reception (may be only transmission/testing or reception) with other functions is called a process. FIG. 1 is an example of a protocol with two processes.

In FIG. 1, circles represent process states, arrows represent state transitions, and labels -X and +X on the arrows represent transmission and reception of signal X, respectively. The initial state of each process is assumed to be R.

Process 1 has R as its initial state, and when it transmits signal S to process 2, it transits to state W. When it receives signal r from process 2, it transits to state P, and so on. In this way, the operation of each process can be designed relatively easily.

However, it is not easy to design a protocol so that there is no logical contradiction between processes 1.2.

In the conventional technique of protocol synthesis, when a state transition diagram of process 1 is given, a state transition diagram of process 2 is automatically generated based on a conversion pattern described later, and the protocols of the two processes are synthesized. The synthesized protocol is guaranteed to be free from logical contradictions such as deadlocks. FIG. 2 shows various conversion patterns. If process 1 has the partial state transition diagram shown on the left in FIG. 2, the partial state transition diagram shown on the right in FIG. 2 is automatically generated in process 2. FIG. 3 shows an example in which a conversion pattern is applied to the protocol example in FIG. 1. According to the application example of FIG. 3, a state transition diagram of process 1 of the protocol example of FIG. 1 is given, and the above-mentioned prior art can only synthesize protocols of two processes. With the technology proposed by the present invention, it is possible to synthesize a protocol consisting of an arbitrary number of processes of two or more.

(Means for Solving the Problems) The present invention was made in view of the above-mentioned drawbacks of the prior art, and aims to provide a method for synthesizing a protocol consisting of an arbitrary number of processes of two or more. The feature is that, like the prior art, it guarantees the synthesis of protocols without logical contradictions such as deadlocks.

(Operation) According to the present invention, an incomplete protocol specification including a functionally insufficient part is input, the state transition diagram of each process is divided with respect to channels, the corresponding missing part of the other process is generated, and the existing protocol Synthesize the specification part and the newly generated protocol specification part for each process,
The protocol specifications should be functionally complete without any logical contradictions such as deadlocks.

(Example) The protocol targeted for automatic synthesis in this example is the protocol example shown in FIG.

Here, we will summarize the protocol specifications, assumptions, and terms for explanation.

The protocol generally consists of the following four-term set P = (Q, 0゜M,
5uCC). However, Q=
(Ql,...,QN), 0=(01,...,ON)
,M:(M,,.

---, MNN), 5ucc is QiX (Mi3
is a partial function of UMji)-Q; 1<:ikuN,
1kujkuN.

Here, N is the number of processes forming P, Q is the state set of process i, and O11! −Ql is the initial state of process i, Mij is the set of signals sent from process i to J through channel (i, j), 5ucc (Sitx) = J
(s;gQ7.tHG:Q;) indicates that if XεMij, the state becomes state ti when the signal . That is, 5ucc represents a state transition.

The protocol is described by a finite state machine, and for convenience of description, 5
Directed f rough Hi = (Vi # E i
+ ” i ) (1 x N) N-term set P = (H,,
..., HN). However, Vi is a set of nodes and is equal to Qi. Also, Ei(c VixVl
) is a set of directed edges and is defined as follows. S1εQi
, ti6Qi, xεMIJ U M jt , 5uc
If and only if C(5t, X)=tr, then (Si, t4)gEi. Furthermore, Li is a set of labels, and for each (si, ti)g-Ei, if Xe M7j, then label +x6Li is added if #-x&LH, xgMj; ◇ Here, Vi is the state of process i, Ei represents the state transition of process i. -X and +X represent transmission and reception of signal X, respectively.

In describing the protocol, we make the following assumptions.

■ The time required for signal transmission between processes is a finite non-negative value.

■ The time required for state transition within a process is assumed to be zero.

■ The reception order of signals sent and received between processes is the same as the transmission order.

The global state of protocol P is the following binary set G=(
s, c). However, 8=(s,...,SN).

Si 6 Qi p C= (C+1.”'+ CNI
0cijεMτ, which is Vri+Cr31E−MrJ, represents the entire sequence, one signal, or two or more signal sequences.

Here, S represents the state of each process, and C represents the signal sequence remaining in each channel between processes.

Define a binary relation T on the set of G. Now, G = (S, C
), 8=(s,...,SN), C=(C1□,・
...v CNN )eG'=(S', C'), S'=(
S'1. ..., hat), C'=(C'n, ...a
C'NN). The necessary and sufficient condition for G)-G/ is a process i that satisfies the following condition (1) or (2).
, j and the signal X exist.

+11 s'i = 5ucc for only one i, j
(si, x), x and Mij.

C'1j=Cij・X, other elements are the same for G and G'.

(2) For the only 'tJ? -5ucc(sj,
x), xεM′”C゛°=X−c′ij, other elements are the same as G, G/Tomosp.

and the state of channel (i, j) changes from C13 to dij
This indicates that the change has occurred.

There is a necessary and sufficient condition for Gl-G' to be n(n〉0
) for K G=GO1-Gl l-...+ )-G
n=G'theal.

Let 1- be a reflexive and transitive closure of H. In other words, for every G, Gl-G, different G, G/.

For q, if Gl-G/and G/l-G#, then Gl-G
'is. If Gol-G, then G is said to be reachable.

However, Go = ("o+ co), 5o = (O1+
+++, oH), co=(ε,...,ε). ε represents the entire series.

In protocol P, the ordered pair (S+X)+SεQi.

XεMij is called a transmission pair, and the ordered pair (S, x), SεQ
i.

X6M,j is called a receiving pair. 5ucc (s, x)
(s, x) is said to be specified if is defined in protocol P. G = (S, C), 5 = (s, .
..., Sl.

...+SN)+"" (C11+...IcN
N) is reachable, then send pair (S J e x )
t x G-Mr) is said to be feasible. G=(
8,C), S=(s, ,...+ Sie...#
SN)+C"(CIt#...+CJ1+・
.IcNN) is reachable, and c-=x-Y,
If xGM=,YεMji, the reception pair JI
Jl(s;, x) is said to be executable.

The protocol specifications synthesized according to the present invention are guaranteed to be free from logical contradictions in the following three items, that is, specification errors.

+11 Undefined Executable Transitions Receive transitions that are not specified in the protocol specification but are executable. However, in the state of the transition light of this reception transition, it is assumed that there is no executable transmission transition or reception transition specified by the protocol specifications.

(2) Defined Infeasible Transitions Transmit or receive transitions that are specified in the protocol specification but are not executable.

(3) Deadronok: A system state in which state transitions of all processes are not executable, and the signals remaining in the channels between processes are completely exhausted.

A set Ei of state transitions and a set Li of labels of process i
The division of is defined as follows.

Ei = Ei' UE ” U...UEゝEJ=
ETjUE″:j (1kujkuN)II
I L=LSULNJ...UL.

Lj, =L-, ``UL↑J (1 ku'' N) and L+j represent the sets of -X1 and +xj, respectively.

! However, -xj is a signal x sent to process j in process 1; +X is a label representing Mij;
(is the signal X that process i receives from process j
The state transition e±JεE±j marked by X1 does not exist, or 1
1K
P is said to be complete if there are no logical contradictions in the three items mentioned earlier. If this is not the case, P is said to be incomplete,
-Xi and +x (for process i, +x and -Xi for process j).

It is said that there is. If +X and -x1 of process J are insufficient for arbitrary -Xi and +x1 of process i, then process j is said to be insufficient for process i.

Based on the above preparations, the protocol synthesis problem is defined as follows.

Input: incomplete Pr = ('l”..., H blue), river"
("r tEj, Lj) (1kuikuN) Complete Po = (HO,...) that satisfies the following condition 1
.

H3) tH'i' = (V'i'l?, L'i') (1 x N) Condition 1: Vj (V'i', Ei c,
E'i', L', ex Li (1 x N) A synthesis problem defined by adding the following condition 2 to this condition 1 is called a new protocol synthesis problem.

Condition 2: Any two processes i and j (1
Either process for <i<N, 1<l:j<N, i〆i)! is insufficient for the other process j.

The protocol synthesis method proposed by the present invention to solve the above-mentioned problem of synthesis of both protocols consists of the following three transformations.

D conversion: Floss j Kotoni H1 = (vi, Ei, Li)
Divide and obtain Ej and Lj. 1 <i <N, 1
<II jkuN, j〆10 +X: and -x i of the missing process j, respectively
G L i and the state J to which it is attached, J transition e to E! generate. 1<;:i<;:N,
1<j〆N, j〆10 C conversion: IBk, Ik divided by process
Synthesize Hj=(Vj, Ej, Lj) from

1×j×N, 1×k×N, nimej0 The protocol synthesis method is performed as follows using the above three transformations. For all two processes i and J (1 x N,
The following processing is performed for 1 x N). Process 1
-xJ or +x: 6, corresponds to Li. ■ A process lacking +Xi or -xje-Lj. If there are multiple processes j (1), D conversion is performed and process i is divided. 6L' is generated for the divided Ej and Lj. As a result, BB LH is obtained for any process (ij), so the protocol specification is completed by performing C conversion J' J and composing them to obtain Ej and Lj.

FIG. 5 is a block diagram showing one embodiment of the present invention. Figure 5
We will explain the blocks and memory in this section. 1 is a memory that stores incomplete protocol specifications including functionally insufficient parts given from the outside, 2 is an initialization block that sets initial values of various variables used in synthesis processing, and 3 is each block in the incomplete protocol. A block that executes D conversion that divides the state transition diagram of a process into each channel for transmitting and receiving signals, 4 is a memory that stores the state transition diagram divided for each channel, and 5 is a block that executes D conversion to divide the state transition diagram of the process into channels for transmitting and receiving signals. A block that executes T-transformation that generates missing state transitions of the partner process to which it sends and receives continuous signals, 6 a memory that stores state transition diagrams generated for each channel, and 7 a state transition generated for each channel. A block that executes C transformation to synthesize diagrams and obtain state transition diagrams for each process, 8
is a memory that stores a complete protocol specification with no functional gaps, which is the result of protocol synthesis.

FIG. 6-(a) shows a storage format when incomplete protocol specifications are stored in the memory 1. In Figure 6-(b), Figure 4
1 shows a storage format when a complete protocol specification represented by a state transition diagram is stored in the memory 1.

For example, in FIG. 6-(a), for 1 which represents sending a signal V to process 3 in state V of process l,
Since process 3 lacks +V, which represents receiving the signal V from process 1, it can be seen that the protocol specification of FIG. 6-(al) is incomplete.
b) State RJ of process 3 from the complete protocol specification of
It can be seen that when process l receives signal V, it enters state CJ. The incomplete protocol specification of FIG. 6-(a) is represented in a state transition diagram as shown in FIG. 7. 8, 9, and 10 are examples in which the D transformation, T transformation, and C transformation in the embodiment of FIG. 5 are applied to the state transition diagram of FIG. 7, respectively. Synthesis of the protocol of the present invention yields the complete protocol of FIG. 4 from the incomplete protocol of FIG. 7, including the functionally missing portions.

The operation of the embodiment of FIG. 5 will be described below using examples of FIGS. 7 to 100, assuming that the incomplete protocol specification has already been stored in the memory 1 in the format shown in FIG. 6-(a). Figure 5
In the block diagram, initialization block 2 operates first. Initialization block 2 accesses memory 1 and obtains information corresponding to the incomplete state transition diagram of FIG. In FIG. 7, the state transition diagram of process 1 includes state transitions for transmitting and receiving signals to and from processes 2 and 3. Therefore, D conversion block 3 accesses memory 1 and divides the state transition diagram of process 1 into a part that sends and receives signals to process 2 and a part that sends and receives signals to process 3, as shown in FIG. stored in memory 4. For example, the portion that sends and receives signals to and from process 2 is determined by removing short circuits from the state transitions that send and receive signals to and from process 3. However, Figure 11
As shown on the left side of , if there is a possibility that an infeasible state transition sequence (labeled 11!3.l) becomes executable after short-circuiting the state transition with label ld (
If al and the transmission transition or reception transition are continuous and form a closed state transition sequence (b), (C1 is transformed as shown on the right side of FIG. 11. The T transformation block 5 accesses the memory 4. , according to the conversion pattern of FIG. 2, the missing state transitions of the partner process are generated for each channel as shown in FIG.

The generated state transitions are stored in the memory 6.

The C conversion block accesses the memory 6 and synthesizes state transition diagrams generated for each channel as shown in FIG. Then, a complete state transition diagram for each process as shown in FIG. 4 is obtained and stored in the memory 8 in the format of FIG. 6-(bl).

Synthesis of a state transition diagram for each channel is generally a synthesis of two or more state transition diagrams, but it is possible to combine two state transition diagrams H+ = (V+ -E+, L+) and H2= without losing membrane properties.
(v2. E2. L!) Kara H=(V, E,
L) ヲIt is executed by obtaining as shown below.

■=v.

×■21 eI ”(vl l vi') e El
If there is an e that satisfies all v2 t v2'6 v
If we create e = (vl V21 v+'V2') 6E for 2, and there is a C2 that satisfies C2 = (v2 e V2')e ``'2, then e = (v , v2. v, '■2') Create εE.

If d+eL+ is attached to eI = (vl + vt') EE+, 11εL is for all v, , v2' = "" for V2 (vl v? v, 'v2') t
E: Attached to E. +1!2(L2 is C2= (v2
1 V2')e If attached to E2, 126 '' is e=(v, v
2゜v,'vl) (attached to F-E. For example, in Fig. 10, if -r↓ is attached to (R, P), then
rl is (RJ.

PJ) and (RK, PK).

The fact that the protocol synthesized according to the present invention does not have the three logical contradictions mentioned above, that is, there are no specification errors, is explained as follows. In D conversion, the state transition diagram of each process is simply divided into channels for transmitting and receiving signals. The divided state transition diagram maintains the order of transmission and reception transitions related to the channels for transmitting and receiving signals in the original state transition diagram. Therefore, state transition sequences divided for each channel that correspond to executable state transition sequences in the original state transition diagram are also executable. Furthermore, since signal transmission and reception are executed independently for each channel, if any state transition sequence in the state transition diagram divided for each channel is executable, the corresponding state transition sequence in the original state transition diagram can also be executed. It is doable. Since the T conversion is the conversion pattern used in the conventional technology,
Similarly, it can be proven that there is no logical contradiction. In C conversion, the state transition diagram of the process is obtained by combining the state transition diagrams generated for each channel, so that the possibility of executing signal transmission and reception independently for each channel is maintained as a whole.

Therefore, it is guaranteed that the protocol synthesized according to the present invention is free from three logical contradictions, that is, specification errors.

(Effects of the Invention) As described above in detail, the method according to the present invention, compared to the conventional method, enables the synthesis of protocols composed of an arbitrary number of processes of two or more. As such, it can provide protocol designers with sufficient guidance for designing a wide range of practical protocol specifications. Therefore, it is effective for maintaining protocol specifications, such as adding or changing new functions to existing protocols, for example.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a protocol, FIG. 2 is a diagram showing an example of various conversion patterns, FIG. 3 is a diagram showing an application example of the conversion pattern, FIG. 4 is a diagram showing an example of a protocol synthesized by the present invention, and FIG. A block diagram of an embodiment of the present invention, FIG. 6 is a diagram showing the storage format of memories 1 and 8 in FIG. 5, FIG. 7 is an incomplete state transition diagram, FIG. 8 is a diagram showing D conversion, and FIG. 9 is a diagram showing T Diagram showing the transformation,
FIG. 10 is a diagram showing C conversion, and FIG. 11 is a diagram showing state transition short-circuit removal in D conversion. (Symbols; Figure 5) 1.8: Memory, 2: Initial settings, 3: D conversion, 4: Memory, 5: T conversion, 6: Memory, 7: C conversion. Solution, Figure 1 Derose λ1 22< in Zoro
o) <b> Arithmetic, 2
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Claims (1)

[Claims] In a protocol synthesis method in which an incomplete protocol specification expressed by an electrical signal is input, missing functions are automatically added and a complete protocol is output. Divide state transitions with respect to the partner process that sends and receives signals, and if there is a lack of state transitions in the partner process that correspond to the state transitions, automatically generate additional state transitions and combine the generated state transitions and existing state transitions. An automatic protocol synthesis method characterized by synthesizing each process for each process and outputting an electrical signal representing a complete protocol specification.