JPS61198866A - Picture image communication equipment - Google Patents

Abstract

PURPOSE:To attain transmission of missing signal even when training reception is successful but a demodulation data is not correctly demodulated by providing a means discriminating that a communication opposite party does not detect a line end code within a prescribed period and a means controlling retransmission of data in response to the result of discrimination. CONSTITUTION:In a hybrid circuit 68 separating a signal of a transmission system and a signal of a reception system, a transmission signal on a signal line 71a is sent to a telephone line 67a via a signal line 67a and a network control section 67. Further, a signal sent from the opposite facsimile equipment is sent to a signal line 68a via the network control section 67. A binary signal detecting circuit 73 generates a pulse to a signal line 73a when a binary signal is detected and outputs the demodulated binary data to a signal line 73b. A retransmission mode selection switch 75 outputs a signal of logical 1 to a signal line 75a when the transmission of the said retransmission mode is selected. An mode change notice tone generating circuit 77 generates a peap tone when a pulse is generated on a signal line 76e.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image communication device that divides image information into a plurality of line information and transmits the divided information.

More specifically, one aspect of the present invention is an image communication apparatus configured to efficiently stop retransmission of image information.

(The following is a blank space) [Prior art] We will take up a facsimile machine as this type of image communication device, and will specifically explain the prior art according to the items shown below. i) I Description of HDLC frame structure (Part 1) 92 Specific example of error retransmission using HDLC frame structure (see Figure 2) 93 Problems caused by error retransmission using HILC frame structure 93.1 Impact on line errors 93.2 Errors occur Effect of bit position (3rd bit position)
(Use figure) 133.3 Effects based on propagation delay characteristics of the A signal line (Use figure 4) 93.4 Difficulty in encoding 54 Disadvantages of conventionally known error retransmission methods 94.1 Regarding fall pack! 54.2 Processing when training signal reception fails (see Figures 5 to 7) fi 4.3 Processing when EOL cannot be detected 94° 4 Processing when image signal transmission is completed @465 Regarding processing after sending instruction signals such as retransmission start line 94.6 Regarding selection of error retransmission mode 61 HD
Description of LIC Frame Structure When data is transmitted via a communication line such as a telephone line, there is a certain probability that errors will occur in the data due to the influence of momentary interruptions, noise, distortion, etc. of the communication line. In order to detect errors in this data, predetermined calculations and the like are performed on the received data to determine whether certain rules are maintained. If an error is detected, a method is adopted in which the information data group containing the error data is sent out again according to a predetermined transmission control procedure.

This automatic retransmission request method (ARQ)
repeat request + t) is a method used when performing half-duplex transmission using a telephone line, etc., and is a high-level data link control procedure (HDLC: high
1 level data 1 ink control p
rocedure). This HDLC is a data terminal equipment @ ([1
TE) It is a bit-transparent synchronous transmission control procedure that enables highly efficient data transmission between each other and can transmit any bit string without depending on any coding system.

In the HDLC procedure, arbitrary bit string information and link control information are transmitted using a frame, which is a transfer unit. The start and end of a frame are flag sequences (01
111110).

FIG. 1 shows a frame format in HDLCf order. The illustrated flag sequence is a signal for frame synchronization, and frame synchronization is achieved by transmitting and receiving one or more flag sequences. Also, if the same bit string as the flag sequence appears in the information transferred in a frame,
The receiving side considers this to be the end of the frame, and to prevent this, five consecutive bits “1”’ are inserted in the frame information.
If a pattern of 5 consecutive bits ``1'' appears, the transmitting side forcibly inserts one bit "0" immediately after it and transmits it, and the receiving side inserts one bit ``1'' that is received following the pattern of 5 consecutive bits Transparency of transferred data is guaranteed by using a method of removing bit "O" (zero bit insertion method).

The address field contains the address assigned to the station transmitting and receiving the frame in binary code (for example, 111111
The frame indicated by 11) having the address of the station on the receiving side is a command frame, and the frame having the address of the station on the transmitting side is a response frame.

If the frame is a command, the control field indicates an instruction to the other station, and if the frame is a response, it indicates a response to the command frame.

The frame check sequence (FGS) is 71/-
Frame (7) is a 16-bit sequence for detecting transmission errors, and indicates the result of calculation by the generator polynomial X' +X + X5+1.The calculation target is from the beginning of the address field to the end of the information field of the frame.

The length of the information field is arbitrary (eg, 512 bytes or 512 x 8 bits).

62 Specific Example of Error Retransmission Using HnLC Frame Structure FIG. 2 shows a specific example of error retransmission using the HDLC frame data shown in FIG.

That is, when the receiving side receives a certain frame, if no error has occurred, it sends out an ACK signal, and if an error has occurred, it sends out a NACK signal.

On the other hand, on the transmitting side, in response to the ACK signal detected during frame N transmission, frame N+1 is transmitted after frame N is transmitted.

On the other hand, if a NACK signal is detected while transmitting a certain frame N, or if an ACK signal cannot be detected, frame N-1 is retransmitted after transmitting frame N, and for the same frame, When a NACK signal is detected a predetermined number of times or more, or when no ACK signal is detected at all.

Control is performed to perform fallback.

In this way, when framed data is sent from the transmitting side and received by the receiving side, no error occurs on the receiving side regarding frame N, but an error occurs when receiving frame N+1, as shown in Figure 2. If this occurs, the following control is performed. That is, the receiving side sends an ACK signal after receiving frame N, and
After receiving +1, it sends a signal to HA(:.

On the other hand, on the transmitting side, A
Since the CK signal will be received, frame N+2 will be sent after frame N+1 is sent.Furthermore, the sending side will receive the NACK signal while frame N+2 is being sent, so it will be sent again after frame N+2 is sent. Frame N+1 is sent.

On the receiving side, after transmitting the HACK signal for frame N+1, the A and GK times signals are transmitted after receiving frame N+2, regardless of whether an error occurs in frame N+2. Thus, the receiving side enters a state of waiting for reception of frame N+1. Then, if no error has occurred in retransmitted frame N+1 that is sent following frame N+2, the receiving side, after receiving retransmitted frame N+1,
Sends a CK signal.

On the other hand, the transmitting side receives ACK while sending retransmission frame N+1.
Since the signal will be received, frame N+2 is transmitted again after retransmitting frame N+1, and frame N+3 is transmitted after frame N+2 is transmitted in response to the ACK signal received while frame N+2 is being transmitted. I do.

j)a Problems caused by performing error retransmission using HDLC frames Image communication devices using the conventionally known retransmission correction method ARQ adopt the HDLC frame structure as described above, so they mainly suffer from the following problems. There were problems described in .

! G3.1 Effect on @ line error HDL
Since the signal to be transmitted is divided into blocks using IC frames, the receiving side has no way of knowing whether a) no errors have occurred in that block, or b) whether one or more bits of errors have occurred. can be judged. Therefore, on the receiving side, it is possible to reproduce a good image without even a single bit error.

However, when a reception error occurs for a certain blow 2, it is impossible to determine the extent of the error.In other words, on the receiving side, it is possible to determine whether there was no error at all in that block, or whether there was no error at all. An alternative judgment as to whether there was an error in the block (i.e., it is not possible to specify from the 1st bit to the That's all I could do.

Therefore, in situations where the line conditions are good, such as in Japan, HDL
C: Although it is effective to block signals using frames (that is, when the line condition is good, the receiver side can reproduce an image without even a single bit error), but one line condition is bad. In this case, there is a high probability that several bits included in the HDLC frame will result in a reception error. For this reason, there was a drawback that the number of retransmissions increased.

53.2 Regarding the influence of the bit position where an error occurs Since the signal to be transmitted is divided into blocks using HDLC frames, if an error occurs at any bit position of the block, retransmission is performed from the beginning of the second blow. For example, as shown in Figure 3, even if an error occurs in the data in the part shown in (a), it is necessary to retransmit it from the beginning of the block, that is, the data in part (b). . For this reason, there is a drawback that transmission efficiency cannot be improved.

93.3 Effects Based on Propagation Delay Characteristics of Communication Lines On the transmitting side, during the transmission period of a certain frame N, it is determined whether or not the previously transmitted frame N-1 was correctly received by the receiving side. However, even in this case, a situation may occur in which the ACK signal cannot be received due to the inherent delay time of one line. A specific example will be explained with reference to FIG. Now, assuming that the time required to transmit the data of block (1) is Tf, and the delay time caused when transmitting a signal from the transmitting side to the receiving side is d, then Tf>27d must be satisfied. In this way, there is a drawback that the permissible delay time on the line is defined depending on the block size. Therefore, in order to allow a longer delay time on the line, a method of increasing the block size can be considered. However, when the block size is increased, the drawbacks mentioned in the above-mentioned section ``reI3.2 Regarding the influence of the bit position where an error occurs'' become more noticeable.

53.4 Difficulty in encoding A drawback was that the new design required additional time to create the encoding.

94 Disadvantages of conventionally known error retransmission methods 94.1
Regarding fall packs, conventional error retransmission systems are configured to issue a retransmission request when a reception error occurs in a receiving device. Furthermore, when a certain document is being transmitted and an erroneous retransmission is performed a certain number of times (for example, three times) or more, a fall pack (reducing the transmission speed) is performed.

Therefore, even if there is no change in the state (characteristics) of the line and reception is possible at a predetermined transmission speed (for example, 4800 bits/5ec), if impulse noise is superimposed on the line (for example, one If impulse noise occurs three times while transmitting the original document, the system will fall back.

Similarly, even if the line is in a steady state, reception at the specified transmission speed is not possible.

Fallback occurs when three consecutive erroneous retransmissions occur.

In the latter case described above, fall packing is meaningful because there is a possibility of eliminating reception errors. However, in the former case, even if fall pack is performed, an error will occur again on the receiving side due to impulsive noise. Therefore, it is wasteful to perform a fall pack in the former case.

As described above, the conventional error retransmission system has the disadvantage that wasteful fall packs are performed, which unnecessarily lengthens the transmission time.

64.2 Processing when training signal reception fails In conventionally known image communication systems, when training signal reception fails, an error immediately occurs on the receiving side, while on the transmitting side, one It was configured so that an error would occur after the manuscript transmission was completed. In this way, even though image transmission is not being performed, the line remains occupied until the transmission of one original document is completed, resulting in a major drawback in that charges are wasted.

FIG. 5 shows an example of the operation when the receiving device fails to receive the training signal in the conventional error retransmission method.

Here, NSF is non-standard equipment, C8■ is the called station identification, Dis is a digital identification signal.

NSS is a non-standard device setting, TSI is transmitting terminal identification, DC8 is a digital command signal, TCF is training check, CFR confirms reception preparation, EOP has completed the procedure, Mouth CN ordered amputation, (see CCITT Recommendation T, 30).

The waveform diagrams shown in FIGS. 6(1) to 6(3) show the state when the receiving side device receives the training signal and succeeds in receiving the training signal.

In this figure, (1) indicates a signal on the line. This figure (B) shows the presence or absence of a signal (SED: Signal Energy), which indicates whether there is a signal on one line.
Figure (C) indicates whether or not valid data transmitted at a predetermined transmission speed has been detected.
(Cal), and exhibits a high level when valid data is detected at a predetermined transmission speed.

As is clear from these Figures 6 (1) to (3), the SED
is at a high level and CD is at a low level (Tr
) , ) This means that the laning signal is being received (Tr=1158+ at 2400 bit/S)
++S.

Tr=923m5 at 4800bit/S).

The flowchart shown in FIG. 7 shows a control procedure for receiving a training signal/image signal in a conventional device.

Here, step 5100O represents receiving the training signal/image signal.

In Stella 7'51002, a timer T2 for determining that the reception of the training signal has failed is set to 10 seconds.

In step 5IO04, 5E is executed continuously for 20 milliseconds while determining whether T2 times out or not.
Detect whether D=1. At this time, timer T2
If it times out, proceed to step 51012, and if it is 5ED-1 continuously for 20 milliseconds (ie, when the beginning of the training signal is received), proceed to step 2 5100B.

In step 5tooe, while determining whether or not timer T2 times out, a millisecond (2400b
/5 (7) is 700 milliseconds, 4800b/517)
It is determined whether or not C0-0 is continuously maintained for a period of 500 milliseconds. At this time, if the timer T2 times out, the process proceeds to step 51012, and if CD=0 continues for a milliseconds (that is, when the training signal is received), the process proceeds to step 91008.

In step 5IQO8, it is determined whether CD=1 for 20 milliseconds continuously while determining whether timer T2 times out. At this time, if timer 〒2 times out, the process proceeds to step 51012. Also, if CD=1 for 20 milliseconds continuously (
That is, when the beginning of the image signal is received), the process proceeds to step 5IOIO.

Step 51010 represents receiving the image signal.

Stay 2bu! 1lilo12 represents a reception error.

As shown in Fig. 7, when the training signal reception fails (that is, when the SED and CD do not operate correctly), the system starts for about 10 seconds after entering the training signal/image signal reception mode. A drawback was that the process ended with an error.

fi 4.3 Processing when EOL cannot be detected In conventional facsimile machines, when the training signal is successfully received and the image signal reception mode is entered, the EOL (End of Line) signal is not detected for more than 5 seconds. When it could not be received, it was immediately marked as an error.

This also applies when error retransmission mode is used.

In this way, if the demodulated data is not correctly demodulated even though the training signal has been successfully received, it is immediately recognized as an error, so there is a drawback that error retransmissions are not effectively utilized.

54.4 Processing when the transmission of the image signal is completed In conventional facsimile machines, when the transmission of the image signal is completed, the procedure signal is immediately transmitted, so if the receiving device makes an error in the last block, an error occurs. The drawback was that retransmission was not possible.

94.5 Processing after sending an instruction signal such as a retransmission start line In conventional facsimile machines, when the receiving side detects an error, it sends a NACK signal, and then sends an instruction signal such as a retransmission start line. Next, the receiving side? The eM was about to receive an image signal sent from the transmitting device (that is, an image signal from the specified retransmission phase start line).

However, if the transmitting side cannot correctly receive an instruction signal such as a retransmission start line sent from the receiving side, an error may occur.

94.6 Regarding the selection of the error retransmission mode, in general, the error retransmission mode has the advantage of being able to reliably transmit image information, but it also takes more time than normal transmission when there are no errors. There is the inconvenience of putting it away. Therefore, it is desirable to leave it to the operator's choice whether or not to perform transmission in error retransmission mode.

However, conventional facsimile machines have a drawback in that the error retransmission mode cannot be arbitrarily selected by the operator.

(Hereinafter, blank spaces) [Object 1] In view of the above-mentioned points, the first object of the present invention is to provide an image communication device configured to efficiently and accurately retransmit error image data.

A second object of the present invention is to retransmit erroneous data when an EOL (end of line code) cannot be detected, in order to eliminate the conventional problems associated with processing when an end of line code (EOL) cannot be detected. An object of the present invention is to provide an image communication device configured as follows.

In order to achieve such an object, the present invention provides an image communication apparatus that divides one stroke information into a plurality of line information and transmits the information, in which a communication partner is unable to detect a line end code within a predetermined period. The method includes means for determining, and means for controlling retransmission of data in response to the result of the determination.

〔Example〕

A facsimile machine will be described as an example to which the present invention is applied.

First, an outline of this embodiment will be described.

(i) When transmitting image information (on the transmitting side), an encoded line number is attached to each line and transmitted together with the image information. Data subsequent to the code corresponding to a certain line number can be retransmitted.

On the receiver side, the line number is checked while image information is being received, thereby determining whether there is a reception error. When the data is received correctly, the line number is removed and the data is decoded.On the other hand, when the receiver side recognizes that a reception error has occurred, the receiving side device sends a control signal and displays the image of the sending side device. Interrupt information transmission. Thereafter, the receiving device notifies the transmitting device of the retransmission request start line number. As a result, the transmitting device resumes transmission from the retransmission request starting line number.

(ii) When transmitting image information, the line number inserted for each line has the following characteristics. (a) The line number is incremented every l line.

The line number is a signal indicating the end of the code of one line, for example, EOL'' (End or Line;
(Used when Modified Huffman encoding or Modified Read encoding is performed based on CITT Recommendation 4). This allows the receiving device to distinguish between the image information and the line number.

C) The length of the line number is constant.

Therefore, a line number representing a small number and a line number representing a large number have the same code length.

Thereby, the receiving device can recognize that the predetermined byte of the signal representing the end of the code of the l line is the line number. In this way, the image information and line number can be easily identified on the receiving side.

2) Line numbers are signals with special meanings, e.g.
A signal representing the end of one line and a signal having a different code structure. Therefore, when an error occurs on the receiving side, it is possible to search again for a signal with special meaning (representing the end of the l line) and establish line synchronization in response to the detection of this signal.

The facsimile apparatus according to this embodiment will be described in detail below in accordance with the following items.

91 An example of the procedure for error retransmission (use Figure 8) 92 Explanation of line numbers (use Figure 8) 93 Specific example of storing encoded data in a FIFO memory (use Figure 10)! 34 Explanation of FIFO memory and pointers that control the FIFO memory 95 Configuration for selecting error retransmission mode from the sending device (used in Figures 11 and 12) 9B Management of FIFO memory in the sending device (Figures 13 to 34) (Used in Figure 15) 97 Validity of the memory capacity for storing the retransmission start address 98 Control after sending all image information from the sending device 99 Conditions for making a retransmission request from the receiving device and conditions for making a fallback request ( (Use Figure 16)! 510 FISF signal configuration (use Figure 17)! 3
11 Operation of the transmitting side device when receiving a NACK signal (used in Figure 18) 512 Explanation of the block diagram of the transmitting side device (used in Figures 19 and 20) 913 Schematic explanation of the operation of the control circuit in the transmitting side device (
614 Detailed explanation of the operation of the control circuit in the transmitting device (using FIG. 22 and 23) 915 Block configuration of the receiving device (using FIG. 24) 16 Operation of the control circuit in the receiving device Explanation (second
(Used in Figures 5 and 26) 17 Other Examples (Hereafter, blank space) 91 Example of error retransmission procedure (Used in Figure 8) When mode selection is made to perform image transmission in error retransmission mode (i.e. (If the start button is pressed continuously for more than 2.5 seconds on the sending device, or if the error retransmission mode is selected on the sending device using a switch, etc.), please refer to Figure 8. I will explain. ' In FIG. 8, a case is considered in which impulse noise occurs once during transmission of 5-picture information, and as a result, errors occur in 3 or more lines in the receiving device. When such an error occurs, the receiving device
CK signal (PrS signal in this embodiment;
re Interrupt Signal). By detecting this PrS signal, the transmitting side device interrupts the transmission of image information.

The receiving device transmits information such as a retransmission start line/fallback to the transmitting device following the PrS signal.
In this embodiment, which uses a V21 modulated NSF signal, the NS
The F signal notifies the sending device of the last correctly received line number.

Based on such a signal, the transmitting side device retransmits the image information from the line next to the line specified by the receiving side. At this time, the transmitting side device performs fallback if there is a fallback instruction. Additionally, if fallback cannot be performed beyond the current level (i.e., if image transmission is currently being performed at 2400 b/s and three erroneous retransmissions have been performed), an error will occur and the line will be disconnected (
DON).

Note that the abbreviations such as NSF/C5I101S shown in FIG. 8 are as described above with respect to FIG.

92 Explanation of line numbers (use of Figure 9) Figure 9 is as follows:
FIG. 3 is a bit configuration diagram showing a specific example of a line number. This line number is inserted after the EOL (end of line code).

Note that in this embodiment, a modified Huffman code is used as the encoding method.

The line number is the 2 bytes (18 bits) following the line termination code EOL.The line number is the LSB (Least Significant Significant Significant Significant Significant Significant Significant Significant Significant Significant Significant Significant Significant Significant Significant Significant Bit) of the high byte in the line number so that it can be distinguished from the EOL signal).
ant Bit) and line number low byte L
SB is each fixed to l. When decoded by the receiving device, the number of beats per line is 1728 bits (
If it is not (when receiving A4 size), EOL again
Executes a search and synchronizes the line. For this reason, the line number needs to be a different signal from EOL.

For example, line number 〇 is OIH (line number high byte), QIH (line number low byte),
Line number l is OIH (line number high byte) 03H (line number low byte), line number 2 is OIH (line number high byte) 05
H (line number low bite), line number 3
is 01H (line number A-(7) ha(/l) 07
H (line number low bite), line number 1
0 is 01H (line number high bite) + 5H (line number low bite), line number 10
0 becomes 01H (high byte of line number) and C9H (low byte of line number). These line numbers are specified to be incremented every three lines.

133 Specific example of storing encoded data in FIFO memory (Used in Figure 10) Figure 10 illustrates a state in which encoded data and retransmission start addresses corresponding to each line number are stored in memory. be. In this figure, TFIFS is the memory area from 8400H to AFFFH, which is the start address of the memory for storing encoded data (in this embodiment, 8400H), as a memory area for storing encoded data in the sending device. think. In addition, as a memory area for storing the retransmission start address, for example, COO
Consider from OH to C3FFH.

Now, as the conditions for the sending device, the minimum transmission time when one line is completely white is 1OSec, the minimum transmission time when one line is black is 20m Sea, and the transmission speed is 4.
A4 size original (all white) when set to 800b/S
The procedure for transmitting the data will be explained based on FIG. At this time, the minimum number of bytes for the l line is six. Furthermore, when transmitting the byte data stored in the memory, it is assumed that the LSB is transmitted first.

For example, when transmitting data at address 8401H, first 7 bits of 0 information are transmitted, and then 1 information is transmitted.

In Fig. 1θ, addresses 8400H, 84011 (
An EOL is formed by the data stored in (1
1 information is sent after 5 consecutive 0 information).

High byte data of the line number is stored at address 8402H, and low byte data of the line number is stored at address 8403H. Address 8402H.

The data stored in 8403H is OIH, OIH
and represents line number 〇.

Addresses 8404)1 to 8406H store modified Huffman encoded data when 1728 bits are all white. In other words, the modified Huffman encoded data when it is 1728 bits completely white is 01001101100110101(
If the data is sent out to the line in order starting from the left side),
Here, 010011011 is the makeup code when the white run length is 1728 bits, and 001
10101 is a terminating code when the length is O bit white run length. When the modified Huffman encoded data when the data is 1728 bits completely white is stored in the memory, it becomes 82H, 59H, and OIH.

When data is sent to the line, it is sent in the following order: B2O LSH data to MSH data, 59H LSB data to MSH data, OIH LSH data to ASB data. That is, 01001
Data is sent to the line in the order of 101 (82H data) 10011010 (59H data) 10000000 (OIH data) (when the data is sent to the line sequentially starting from the left side). Thereafter, similarly, the encoded data is stored in the memory of the sending device.

On the other hand, a retransmission start address is stored in memory in correspondence with each line number. The memory area in which the retransmission start address is stored is from address cooon to address 03FFH. The first seven addresses of the memory area where retransmission start addresses are stored are called LINO. Two bytes of memory area are required to specify one retransmission start address. Since the memory area from address cooou to address C3FFH is 1024 bytes,
It is possible to store 512 retransmission start addresses. Also, as mentioned above, the line number is incremented for each line, so when the line number changes (that is, it is incremented by l), the encoded data is stored in the memory that stores the retransmission start address. Stores the start address of the line number of the memory where the data is stored. A specific example is
As shown in FIG.

Addresses C00QH and C00IH contain OOH and 84H.
is stored. The data stored at address COOOH is the low data at the retransmission start address of line number 〇, and the data stored at address C00IH is the high data at the retransmission start address of line number 0, which is the stored data of line number 〇. The start address (with respect to the memory where encoded data is stored) is 8400)1.

Also, are addresses COO2H and CQO3H O? H, 8
4H is stored. The data stored at address 0002H is the low data at the retransmission start address of line number 1, and the data stored at address CQQ3H is the high data at the retransmission start address of line number 1. The starting address (with respect to the memory where the encoded data is stored) is 8407H. Similarly,
Line number 2゜Line number 3. The starting address where line number 4 is stored (with respect to the memory where encoded data is stored) is 840EH, 8
415H.

It is 841CI.

Furthermore, as described above, since the memory area for storing the retransmission start address is 1024 bytes, 51241 retransmission start line numbers can be stored.

The 513th line number is LINO (address C
OOOH). In this way, the past 5!2 line numbers are stored.

fi4 Description of FIFO memory and pointer controlling FIFO memory In the transmitting side device, the data encoded according to this embodiment is stored in FIFO (First-In First-O
ut) stored in memory. The capacity of the FIFO memory is as described above (from 840QH to AFFFH. Here, the starting address of the FIFO memory of the sending device is ↑
FIFS (TRI FIFO5TART; 8400H in this example).

The high byte at the start address of the FIFO memory of the sending device is TPIFSH (TRI FIFO5TART
HIGH; 84H in this embodiment), the final address in the FIFO memory of the sending device is TFIFE (
TRI FIFOEND; AFF in this example
FH), the high byte at the final address of the FIFO memory of the sending device is ↑F I FE) I (↑R11F
IFOEND HIGH, AFH in this example)
It is called.

In the sending device, the data read by the reading means is encoded and then stored in the FIFO memory of the sending device, and a pointer is used to control the FIFO memory. The pointer used for this purpose is TRI Ml! POINTER
), and the data stored in the FTFO memory on the transmitter side is modulated by a modulator and then transmitted sequentially to one line, but a pointer is also required here to control the FIFO memory. The pointer used for this is the TM port PTR (00EX POINTER in TRN).
It is called.

On the other hand, the receiving device stores the data sent from the transmitting device in its memory. This memory, like the sending device, is a FIFO (First-In First
-Out) memory. The capacity of the FIFO memory of the receiving side device (7) is also the same as that of the sending side device, from 8400)1 to AFFF)I.

Here, the first address in the FIFO memory of the receiving device is RFIFS (REC: FIFO5TART; 8400H in this example), and the FIFO memory of the receiving device is
The previous 117 degrees in memory / Snow Hight < Itot
*RFTFSId(RECFIFOSTART HI
GH; 84H in this embodiment), FI of the receiving side device
The final address in the FO memory is RFIFE (REC
FIFOEND; AFFFH in this example),
The high byte of the final address in the FIFO memory of the receiving device is RFIFEH(RECFIFOEN[l H
IGH; referred to as AF)I) in this embodiment.

In the receiving device, the data sent from the transmitting device is demodulated by a demodulator, and then stored in a FIFO memory. A pointer is used when storing demodulated data in the FIFD memory, but this pointer is
It is called TR (RECMODEM POINTER). Furthermore, the data stored in the FIFO memory is sequentially read, decoded, and recorded. A pointer is also used when sequentially reading and decoding the data stored in the FIFO memory.
CMHPOINTER).

95 Configuration for Selecting Error Retransmission Mode from Sending Device (Used in FIGS. 11 and 12) Two methods are used to select the error retransmission mode from the sending device. $1 is a method of selecting an error retransmission mode using a switch or the like. That is, it is assumed that the error retransmission mode is selected when a certain specific switch is in the on state.

A second way to select the error retransmission mode is to press the start button on the sending device successively. That is, the error retransmission mode is selected by continuously pressing the start button for 2.5 seconds or more, and the operator knows that the error retransmission mode has been selected by the generation of a "beep" sound.

Also, if you press the start button on the sending device for more than 5 seconds continuously, G2 mode will be selected and the "beep" will be heard.
The operator will know that the G2 mode has been selected by the beep sound.

In this embodiment, image transmission in the error retransmission mode is performed at a transmission speed of 4800b/s. Therefore, when the error retransmission mode is selected by the transmitting device, the receiving device is equipped with the error retransmission mode function. If so, transmission is performed in error retransmission mode. However, if the receiving device is not equipped with an error retransmission mode,
Transmission speed is 4800b/s instead of 9800b/s
and start transmission.

FIG. 11 is a block diagram showing the configuration of the transmitting side of the facsimile apparatus according to this embodiment. In this figure, 67 is a network control unit (N(:U)) which uses the telephone network for data communication etc. 87a is a telephone line that connects to the terminal of the line to control the connection of the telephone exchange network, switch to a data communication path, and maintain the loop.

88 is a hybrid circuit that separates a transmission system signal and a reception system signal. Signal line? The transmission signal on la is transmitted to telephone line 11i8 via signal line 87b and network control unit 67.
? sent to a. Further, signals sent from the other party's facsimile machine are transmitted via the network control unit 67 to the signal line 8.
8a.

69 is a binary signal sending circuit, and when a pulse is generated on the signal m7Bb, the signal line ? Data on Ba is input, and data modulated by V21 is output to signal line Ha.

Reference numeral 70 denotes a tonal signal sending circuit, which inputs the signal on the signal line 76c when the data on the signal line 78d is at the signal level rlJ. If the input data is "1", then 46
2+(If the tonal signal of z is "2", it is 1080Hz
If it is "3", it will be a 1850Hz tonal signal; if it is "4", it will be a 1850Hz tonal signal; if it is "5", it will be a 21QOHz tonal signal.
Output to 0a.

71 is an adder circuit, which combines the signal of the signal line 89a and the signal Mi
170a and the added result is sent to the signal line 71.
Output to a.

72 is a tonal signal detection circuit, and when the signal of the signal line 88a is input and a signal of 482 Hz is detected, the signal line ? When detecting the rlJ signal on 2a and the 1080Hz signal, the signal line? Signal “2” to 2a, 165
When a 0Hz signal is detected, is the signal line connected? ``3'' in 2a
When a signal of 1850 Hz is detected, a signal of "4" is output to the signal line 72a, and when a signal of 2100 Hz is detected, a signal of "5" is output to the signal line 72a.

73 is a binary signal detection circuit, which generates a pulse in the signal 1173a when a binary signal is detected, and sends the demodulated binary data to the signal line? Output to 3b.

Reference numeral 74 denotes a start button, and when this start button is pressed, a signal of signal level rlJ on the signal line 74a is output.

75 is an error retransmission mode selection switch, and when transmission in the error retransmission mode is selected, the signal 1i? 5a
outputs a signal with signal level "1".

76 is a control circuit.

77 is a mode change notification sound generation circuit, and a signal line 76e
A "beep" sound is generated when a pulse is generated.

FIG. 12 is a flowchart showing the control procedure of the control circuit 76 shown in FIG.

In step S+014, it is determined whether the start button 74 has been pressed. Is this a signal line? 4a
This is determined by inputting the signal.

When the start button 74 is pressed, step 3101
Proceed to B.

In step 5tolB, it is determined whether the start button 74 has been pressed continuously for 2.5 seconds or more.

This is determined by inputting the signal on the signal line 74a. If the start button 74 is continuously pressed for 2.5 seconds or more, the process advances to step 91028, and if the start button 74 is not continuously pressed for 2.5 seconds, the process advances to step 5O18.

In step 51018, it is determined whether the error retransmission mode is selected. This is the signal line 75a
This is determined by inputting the signal. Then, when the error retransmission mode is selected, step 51G
On the other hand, if the error retransmission mode is not selected, the process proceeds to step 51020.

Step 51020 shows the transmission of image information by 91110Qb/;.

In step 51022, it is determined whether the other party's facsimile device (receiving device) has an error retransmission function. Information indicating whether the receiving side device has an error retransmission function is communicated to the transmitting side by the FIF of the NSF signal. That is, by inputting the signals on the signal lines 73a and 73b, it is determined whether or not the receiving side device has an error retransmission function. If the receiving device has the error retransmission function, the process advances to step 3102B; on the other hand, if the receiving device does not have the error retransmission function 1171, the process advances to step 51024.

In step 51024, image information in 4800b/S is transmitted.

In step 81028, image information is transmitted in error retransmission mode.

In step 91028, a "beep" sound is generated (sending a pulse on signal 1Q78e) to inform the operator that the error retransmission mode is selected.

(Hereafter, blank space) In step S+030, it is subsequently determined whether the start button 74 has been pressed continuously for 2.5 seconds or more. This is determined by inputting the signal on the signal line 74a. If the start button is continuously pressed for 2.5 seconds or more, step S+032
On the other hand, press the start button twice in succession.
．． If the button is not pressed for 5 seconds or more, the process advances to step 5IQ22.

In step 51032, a "beep" sound is generated (a pulse is sent twice to the signal line 78e) to inform the operator that the G2 mode has been selected.

In step 51034, transmission is performed in G2 mode.

96 Management of FIFO memory in sending device (first
(Used in Figures 3 to 15) Regarding the management of the FIFO memory included in the sending device,
This will be explained below.

FIGS. 13(1) and 13(2) are diagrams for explaining the relationship between the FIFO memory and various pointers. TMHPTR is F
TMDPT indicates up to which address in the IFO memory space encoded data is stored.
R indicates at which address in the FIFO memory space the data was modulated and sent to the line.The encoder is
Store encoded data from TF I FS address,
When the encoded data up to address TFIFE is stored, the next encoded data is stored at address TFIFS II. At this time, a flag called REVRS (reverse) is set to 1, and the encoded data is stored to the final address of the FIFO to the modem side, and TMHPTR is set to F.
Notifies you that you have returned to the top of the IFO.

On the other hand, as processing on the modem side, the encoded data from the ↑FIFS address is sequentially read out, modulated, and then sent to the line, and the data stored at the TFIFE address is read out, modulated, and sent to the line. After sending to
Read the data stored at TPIFS address,
Modulate it and send it out to the line.

At this time, REVl? A flag called S (reverse) is set to 0 to notify the encoding side that modulation of data at the final address of the FIFO and transmission to the line have been completed and that TMDPTR has returned to the beginning of the FIFO.

The main effects of FIFO management in the sending device are as follows.

(2) When the line number changes, the address where the encoded data corresponding to that line number is stored is stored in the memory that stores the retransmission start line number.

(2) Prevent the modem pointer, ie, TMDPTR, from overtaking the encoder pointer TMHPTR.

■The encoder pointer TMHPTR goes around the FIFO memory so that it does not get too close to the modem pointer TMDPTR (retransmission is performed when a reception error occurs on the receiving side, but the data for this retransmission is stored in the FIFO
(to keep it in memory).

As for item L (2), it has already been explained using FIG. 1O, so the explanation will be omitted here.

Next, the modem pointer T will be explained regarding the above ■.
MDPTR is the encoder pointer TI'l)! PTR
In order to avoid overtaking the modem's pointer T
When the M port PTR approaches the encoder pointer ↑NHPTR, a fill is sent out. Here, when encoding the read data, EOL consists of 2 bytes and 00H
, 80H (see FIG. 10). As an example of the control of item (2), the following example can be considered.

If the modem pointer MDPTR detects OOH, 80H data while sending data from the FIFO memory,
Check the REVHS (reverse) flag.

When the REVRS (reverse) flag is O, it is determined whether (high address in encoder pointer TMHPTR) - (high address in modem pointer TMDPTR) < 2, and if the above conditions are satisfied, the fill If the above conditions are not met after sending,
That is, when (address in encoder pointer TNHPTR) - (high address in modem pointer TMDPTR)≧2, modem pointer TM[)PTR
is sequentially incremented to send out the data stored in the FIFO memory.

On the other hand, when the REVRS (reverse) flag is 1, it is first determined whether the high 7 address in the modem's pointer TMDPTR is equal to TFIFEH (the byte at the final address of the FIFO). The high address in the modem pointer MOP is TFTP.
If it is not equal to EH, the modem pointer is sequentially incremented and the data stored in the FIFO memory is sent out.

When the modem pointer TNDPTR is equal to TFIFEH, it is determined whether (high address in the encoder pointer TMHPTR) -TPIFSH< 1, and if the above conditions are met, a fill is sent, and the above conditions are met. If not satisfied, i.e. (encoder pointer ↑M) high address in IPTH) -TFIFSH≧1, increment DPTR to modem pointer T sequentially and send out data stored in FIFO memory. .

In the above case, even in the case of transmitting a fill, all encoding is completed (actually, when encoding is completed on the encoding side, the flag MHEND is set to 1, so the modem side sets this flag to 1. You can check whether all encoding has been completed by checking the modem pointer T.
The data stored in the FIFO memory is sent out by sequentially incrementing NDPTR.

Furthermore, when all encoded data has been sent out, an RTC (Return To Control) signal is sent out. This RTC also includes the last transmitted line number after EOL. The number of EOLs is 103.

Next, the above item (2) will be explained. FIG. 14 shows the number of bits and bytes transmitted in 3 seconds at each transmission speed. In other words, i for 3 seconds round trip
l! In order to be able to retransmit up to the end, the encoder's pointer TMHPTR must be
Must be more than 3[100 bytes away from PTH.

FIG. 15 shows the relationship between the FIFO memory and various pointers. In this embodiment, when the high address in the encoder pointer TMHPTR is incremented, it is compared with the modem pointer 7M port PTR.

The encoder pointer TMHPTR is controlled to be separated from the modem pointer TMDPTR by 4096 bytes or more. A specific example of this control is shown below.

When incrementing the high address in the encoder pointer TNHPTR, REVRS (reverse)
Check the flag, REVRS (reverse)
When the flag is O, (TFIFEH-(encoder pointer ↑MHPTR
)) + ((modem pointer TM
High address in DPTR) -TPIFSH)
It is determined whether or not <16, and if the above condition is satisfied, encoding is interrupted and a wait state is entered. Also, when the above conditions are not met, ie.

(TFIFEH-(encoder pointer TMHPTR
)) + ((modem pointer TM
High address in DPTR) -TPIFSH)
When ≧16, perform encoding and convert the encoded data to F
Store in IFO memory.

On the other hand, when the REVRS (reverse) flag is 1, it is determined whether (modem pointer TM [high address in 1PTR) - (encoder pointer T to high address in HPTR) < 16, and the above When the following conditions are met, encoding is interrupted and the process enters a wait state.

- when the above conditions are not met, i.e.

When (high address in modem pointer TMDPTR) - (high address in encoder pointer TMHPTR)≧16, encoding is performed and the encoded data is transferred to FIF
Store in O memory.

97 Validity of memory capacity for storing retransmission start address The memory area for storing retransmission start address is considered to be 1024 bytes in this embodiment. Therefore, 512 retransmission start addresses can be stored. That is, it is possible to retransmit one minute of the past 512 line numbers.

Here, when encoding an l line, the shortest data is when the l line is a blank space.As mentioned above, when encoding an all-white line, the number of bytes is 7 bytes. .

Since the l line number is incremented for each line, the minimum number of bytes for the l line number is 7.

Considering retransmission for one line number of 512, a minimum of 3584 bytes is required. At this time, if the transmission speed is 4800b/S, 3584 (bytes) ÷
600 (bytes 7 seconds), M = 8 (seconds), and as mentioned earlier, 3 seconds is considered as the time to allow for delay on the line, so the retransmission start address is a memory with a capacity of 512 pieces. It is sufficient to store it in .

9th: Control after all image information has been sent from the sending device When all encoding of the transmission document is completed, a return to control (RTC) signal is written to the FIFO memory. This RTC is
OL 103 bonds. And following EOL,
Finally, add the line number sent out later. E here
OL is 11 rQ Js followed by rl Js.
Consists of 2 bits.

The above-mentioned RTC transmission time is 0 at 4800b/s.
．． 6 seconds, and 1.2 seconds at 2400b/S.

Generally, when performing error retransmission, the line quality is often poor, so RTC signals are
If the number is set to 8, it is expected that RTC detection will not be possible. Therefore, the RTC signal is set to EOL 103 so that the receiving device can always detect the RTC signal.

In fact, even when the modem finishes transmitting the RTC signal, it does not immediately start transmitting the procedure signal. 1 second is considered as the detection time of the signal). Then, after 1.5 seconds have elapsed after the sending of the RTC signal is completed, a 5ED-0 signal is sent from the receiving side.
■It is determined that the S signal is not being sent, and the procedure signal is sent. Specifically, the EOM/
MPS/EOP/PRI-EON/PRI-MPS
/ρRI-EOP is used.

Furthermore, if 5ED=1 after 1.5 seconds have passed after the sending of the RTG signal is finished, the process proceeds to search for the PIS signal.

If a PIS signal is detected within 2 seconds, error retransmission is performed, and if a PIS signal is not detected even after 2 seconds, the process proceeds to transmit a procedure signal.

99 Conditions for making a retransmission request from the receiving side device and conditions for making a fallback request (Used in Figure 1B) There are three cases in which the receiving side device makes a retransmission request as described below.

■ When an image error occurs in 3 or more consecutive lines, ■ When training signal reception fails.

■ When the EOL signal cannot be detected for a certain period of time (for example, 4.5 seconds for 2400b/S, 3.5 seconds for 4800b/S) after entering image reception mode.

Also, "While one document is being transmitted, it will be retransmitted three times."
However, if error-free data is received over a certain number of bytes (for example, 127 bytes), the counter that counts the number of retransmissions is reset.

The flowchart shown in FIG. 16 represents the image reception control procedure focusing on the case of making a retransmission request and the case of making a fallback request. Explain in detail.

Step 9103B represents 1 image reception status 0
Before image reception, a counter that counts the number of times the NJF signal has been sent and a retransmission counter that indicates how many times one document has been retransmitted during reception are cleared.

In step 9103B, it is determined whether training reception was successful. Successful training reception means that 5ED=1, CD-0 (about half the training time), and C0-t were correctly confirmed. If training reception is successful within 3.5 seconds, proceed to step 5104G; on the other hand,
If the training reception is not successful within 3.5 seconds,
Proceed to step S10?8.

Normally, training reception ends within 3.5 seconds.

Therefore, if training is not completed within 3.5 seconds after starting training reception, it is determined that training reception has failed. In this way, in the unimplemented example, it became possible to immediately determine that training reception had failed. Therefore, subsequent error retransmission or sending of an NSF signal (which may also be a DON signal) becomes possible.

The selection of whether to perform error retransmission or to send the NSF signal (when the NSF signal has been sent three times, the DCN signal is sent) will be described later.

In step 7, 5IQ4Q, since the training reception was successful, the counter that counts the number of times the NSF signal is sent is cleared. When performing error retransmission, the receiving device sends out the NSF signal following the PLS signal. This NSF signal includes information such as the retransmission start line and the presence or absence of fallback. When the transmitting device correctly receives this NSF signal, it performs fallback control and then retransmits from the retransmission start line.

However, when the transmitting device cannot correctly receive the NSF signal, it goes back to receiving the NSF signal.On the other hand, after transmitting the NSF signal, the receiving device goes to receive the training signal. Since no data has been transmitted, training reception will be unsuccessful. At this time, the receiving device receives 5ED= within 3.5 seconds.
1 is detected (step 51078).
), in this case, the training signal is not sent out, so SHO is "0", and the receiving device goes back to sending out the NSF signal, and the above counter is for counting this number of times.

If the training signal is not sent from the sending side even after sending the NSF signal three times, the DCN @ signal is sent and the line is disconnected.

Step 2 51042 to step 5104B represent the image reception state.

In step 51042, it is determined whether or not consecutive errors have occurred in three or more lines. These three lines are just one example, and can be set to any other value. It is also possible to automatically change the number of lines depending on the fineness of the received image.

If a continuous error occurs in three or more lines, the process proceeds to step 91052 and retransmits the error.

If no consecutive errors occur on 3 or more lines,
Proceed to step 5IQ44.

In step 91044, between a (2400b/S
17), it is determined whether or not the EOL signal is detected over a period of a=4.5 seconds, and a=3.5 seconds when the signal is 4800b/S. If no EOL signal is detected for 3 seconds, step 910
Proceeds to 5B and retransmits the error, and also returns E within 3 seconds.
If the OL signal is detected, the process advances to step 3104B.

These three seconds are determined based on the longest transmission time of one line at each transmission speed. This makes it possible to perform error retransmission even when training reception is successful but correct data is not demodulated.

In step 9104B, RTC (Return)
t.

Control) signal is detected.

If the RTG signal is detected, the process proceeds to step 91048.

On the other hand, if no RTC signal is detected, the process advances to step 51042.

Step 51048 represents a post-procedure.

Step 5I050 occurs when a timeout occurs while receiving one document (T=113 minutes), and represents an error.

In step 2 51052, it is determined whether or not correct data of a certain number of bytes or more has been received. When the line characteristics are in a steady state, image reception is good, but if an error occurs due to impulsive noise that occurs infrequently, it means that more than a certain number of bytes of correct data have already been received. Become.

In such a line situation, even if a fallback is performed on the sending side, an error will occur again.

Therefore, in such a case, it is better not to use the useless faller 2. That is, if correct data of a certain number of bytes or more has been received first, the process advances to step 51054 and the one-way sending counter is cleared. If correct data beyond a certain number of bytes has not yet been received, the process advances to step 9105B and the retransmission counter is not cleared.

In step 3105G, a P/S signal is sent to interrupt transmission on the transmitting side.

In step 51058, the retransmission counter is incremented by one.

In step 5106G, it is determined whether the signal has arrived (ie, 5ED=1). When 5ED=1, the process advances to step 510B2.

This case is a case where the transmitting device does not correctly receive the PIs signal sent in step 9105B.

On the other hand, when 5ED=0, the process advances to step 31084.

In step 51082, the ρ■s signal is sent again.

In step 51084, it is determined whether the count value of the retransmission counter is 3 or more (that is, whether fallback is to be performed). If the count value of the retransmission counter is 3 or more (i.e.

If fallback is performed), step 5IQ813
If the count value of the retransmission counter is less than 3 (that is, if fall pack is not performed), the process advances to STEP 51074.

In step 9106B, it is determined whether the current transmission speed is 2400 b/s. When the current transmission speed is 2400b/s, no further fall pack can be performed, so after sending the DON signal (step 51068), the process ends with an error (step 5107Q).On the other hand, when the current transmission speed is 24θ
If not Ob/S, step 91G? Proceed to step 2 and specify fallback.

In step 51074, an NSF signal containing information on whether or not there is a retransmission start line/fallback is sent.

In step 51078, the counter that counts the number of times the NSF signal is sent is incremented by 1, and then the process proceeds to receive the image signal.

Step 9107B is a block that branches when training reception fails. If training signal reception fails after sending CFRm,
Perform error retransmission.However, if the training signal reception fails after performing error retransmission once and transmitting the NSF signal, there are two cases: error retransmission and NSF/CN signal transmission. .

That is, if the transmitting device is not correctly receiving the NSF signal (the transmitting device is not transmitting the training signal; YES in step 91078,
Sufu/Bu5108G Nioiite YES Throat) is N
On the other hand, if the reception is unsuccessful in the receiving side device (step 91078 and N
O), error retransmission is performed, here step 91
5ED-1 in step 078 indicates that it is determined that the training signal has arrived, and if 5ED=1 is detected in step 51078 (that is, if the training signal has arrived), step On the other hand, in step 91078, if 5ED=1 cannot be detected (i.e., the training signal has not arrived), proceed to step 5
Proceed to 1080.

In step 91080, it is determined whether an NSF signal for retransmission was sent immediately before. If the NSF signal for retransmission was sent immediately before, step 5108
If the NSF signal for retransmission has not been sent immediately before, the process proceeds to step 3105B.

In step 31082, it is determined whether the NSF signal has already been retransmitted three times. If the NSF signal is retransferred three times, the process ends with an error (step 5L0) after sending the DCN signal (step 51084).
8B) If the NSF signal has not been retransmitted three times, the process proceeds to step 91084 and the NSF signal is retransmitted.

j310 NSF Signal Structure (Used in Figure 17) The receiving side device is provided with a memory area to store the latest received line number. And at the time of initialization, 0! Store OIH data.

Each time the decoder detects EOL, it checks the next two bytes of data, ie, the line number. Then, if the line number received this time is compared with the line number correctly received last time and the increment is 3, the received image is judged to be 1 good.In other words, the image with less than 3 lines The error is that the reception is "good"
It is determined that This line number is stored in memory and updated each time it is detected.

On the other hand, if the line number received this time is incremented by three or more from the line number correctly received last time, a NACK signal will be sent.Kimio's side will send a PIS signal (a 462Hz signal continuous for 3 seconds). In other words, if an image error of 3 or more lines occurs, it is determined that the received image is defective and a request is made to retransmit the error.Therefore, after sending the PIS signal, the 300b/S signal is sent. A signal is used to notify the transmitting device of the retransmission start line number and the presence or absence of fallback.

Figure 17 shows an example of a 300b/S signal sent from the receiving device to the transmitting device. In this figure, the preamble is a roll 1110 J pattern that is continuously transmitted for about 1 second, FFH is address data, and 13H is Control data (sent to the line in the order of LSH data to MSH data), 20H is the NSF FCF (Facsimile Control Field), and
The line numbers to be transmitted thereafter are data focused on the last nine digits of the line numbers, from line number 0 to line number 511. Regarding the line number sent at this time, the LSB of each byte data
For example, line number 0 is 00H, OQH.

The next byte data indicates the presence or absence of fallback. Specifically, when OOH, fallback is not specified and F
When FH, fallback is specified.

FC9 is frame check sequence, FLAG is ro
lll 1110J There is.

When decoding when receiving images, 2 following EOL
Byte data (ie, line number) is ignored.

611 Operation of the transmitting device when receiving a NACK signal (see Figure 18) The transmitting device reads the information on the document using the reading means, encodes the data using the encoder, and transmits the encoded data using the modem. It is modulated and sent to the line. At this time, NACK signal (PIS signal on Kinomio side)
is being monitored. Then, if the NAGK signal is not detected, the image information is transmitted, and if the NACK signal is detected, the image information transmission is interrupted. And 300b/
As described above, the line number (lower 9 digits) at which retransmission is to be started and information on the presence or absence of fallback are stored in this 300b/S heading for reception of the S signal.

When the sending device detects the retransmission start line number, the address in the encoder pointer TMHPTH in the sending device and the modem pointer T in the sending device
The following three cases can be considered as examples of this control in which the NDP address, REVHS (reverse) flag, and retransmission start address are checked and various controls are performed based on the results.

The first case is when the REVRS flag is O and the encoder pointer TMHPTR in the transmitting device is greater than the modem pointer TMDPTR in the device, the modem pointer TMDPTR in the transmitting device
is larger than the retransmission start address. Figure 18 (
1) to (3) illustrate three cases in which a retransmission start address is recognized and retransmission is performed. The first case described here is illustrated in FIG. 18(1). In this case, the modem pointer TMDPT!
? Set the retransmission start address to , and retransmit from that line number.

The second case is illustrated in FIG. 18(2).

That is, this is the case when the REVRS (reverse) flag is 1 and the modem pointer TMDPTR in the transmitting device is larger than the encoder pointer TMHPTR in the device. In this case, the retransmission start address is set in the modem pointer TMDPTR in the sending device, and retransmission is performed from that line number.Here, the encoder pointer TMHP in the sending device is set.
If TR is larger than the retransmission start address, it is determined that an error has occurred, and the line is opened by sending out, for example, a double CM signal (according to 300b/S) without transmitting image information.

The third case is illustrated in FIG. 18(3).

That is, the REVHS (reverse) flag is 0, and the HPT
When R is larger than the modem pointer TMDPTR in the device, the retransmission start address pointer is larger than the modem pointer TMDPTR in the sending device. In this case, set the retransmission start address to the modem pointer TNDPTR in the sending device and retransmit from that line number.
Set the RS flag to 1. Here, if the encoder pointer TM) IPTR in the transmitting side device is larger than the retransmission start address, it is judged as an error, and the image information is not transmitted, for example, the DCN signal (300b/S), etc.
to open the line.

When receiving an instruction to perform fallback, it falls back and transmits image information.

Furthermore, if a DCN signal is detected following a PIS signal, the line is released and the process ends with an error.

912 Explanation of the flow chart of the transmitting side device (using FIGS. 19 and 20) FIG. 18 is a block diagram showing the configuration of the transmitting side of a facsimile apparatus to which the present invention is applied.

In FIG. 19, 2 is a network control unit NC■ (Network Control Unit) that maintains the loop.
) In order to use the telephone network for data communication, etc., it connects to the terminal of the line and controls the connection of the telephone exchange network, or switches to the data communication path.

2a is a telephone line.

4 is a hybrid circuit that separates a transmission system signal and a reception system signal. The transmission signal of the signal line 28a is transmitted to the signal line 2b.
is transmitted to the telephone line 2a via the network control unit W2. Further, a signal sent from the other party's facsimile machine is output to the signal line 4a after passing through the network control device 2.

6 is a circuit that detects a retransmission request signal (in this embodiment, a PIs signal is used) sent from the receiver. That is, a signal on the signal line 4a is introduced, and when a retransmission request signal (PIS signal in this embodiment) is detected, a signal of signal level rlJ is outputted on the signal line 8a. On the other hand, when the signal on the signal line 4a is introduced and no retransmission request signal (P■S signal in this embodiment) is detected, a signal of signal level rQJ is outputted on the signal line 6a.

8 is a 300b/S signal (in this embodiment, an NSF signal is used: 17th ) and a disconnection command (DC
This is a circuit that receives a signal (300b/S signal).

When the binary signal receiving circuit 8 detects the NSF signal, it generates a pulse on the signal line 8a and outputs a retransmission start line number on the signal line 8b. and,
Information on the presence or absence of fall pack (0→no fallback, l→fall par 2) is output to the signal line 8d.

Furthermore, when the binary signal receiving circuit 8 detects the DC11 signal, it generates a pulse on the signal line 8c.

Reference numeral 10 denotes a reading device Z that reads image signals corresponding to 1 life in the main scanning line direction from the transmitted original and creates a signal string representing a binary value of white or black. This reading device 10 is (Ill:D
It consists of an imaging device such as a charge-coupled device (charge-coupled device) and an optical system. When a pulse occurs on the signal line 12a, that is, l
When there is a request to read a line of image signals, one line of image signals is read and binarized data is output to the signal line 10a.

Reference numeral 12 denotes a double buffer circuit so that while the image signal in one buffer memory is being encoded, the image signal of the next line is written into the other buffer memory. 2 tree buffer 4fBUFO (bar/ )
y O), called BUFI (bar/771),
When the BUFQ buffer is full of image data, the signal level "1" is applied to the signal line 12b (buffer all full).
” signal is output. When the buffer of BtlFO is not full of image data, a signal of signal level rQJ is output to the signal line 12b (buffer all full). Furthermore, when the buffer of BUF 1 is full of image data, a signal of signal level rlJ is output to the signal line 12c (buffer l full). When the buffer of BUFI is not full of image data, a signal of signal level rQJ is output to the signal line 12c (buffer l full).

After confirming that the buffer is full, the control circuit 30 (described later) transfers the buffer to be read next to the signal line 30.
When the signal level of the signal line 30b is "0" as specified by the signal output to the signal line 30b, the data in the buffer 0 is read:
When the signal line 30b is at signal level "l", the buffer l
data is read out), and then a pulse (read pulse) is generated on the signal line 30a.

This double buffer circuit 12 outputs the data of the designated buffer to the signal line 12d. Then, when the data of the designated buffer is output to the signal line 12d, the buffer full state of the designated buffer is dropped, that is, the signal level output to the signal line 30b becomes rQ4 (z<
buffer 0 (specified) and to the signal line 30a (lead)
A pulse is generated.

When all the data in the buffer is output, the signal level 0 is dropped (that is, a signal with a signal level "0" is output to the signal line 12b), and the signal level output to the signal line 30b becomes rlJ ( buffer l specification), and a (read) pulse is generated on the signal line 30a and all the data in the buffer is output, the buffer is full l.
(In other words, the signal level “0” is applied to the signal line 12c.
signal).

Furthermore, when the buffer becomes empty, the double buffer circuit 12 generates a pulse on the signal line 12a, and inputs data for one life in the main scanning direction from the reading device 1G. In this case, the data is stored in an empty buffer, but at the same time, the buffer full in which the data was stored is set to 1. The read data is sent to buffer Q, A buffer 1. /< buffer 0 and buffer l are stored alternately.

14 is a counter that counts the line number inserted after the end-of-line code (EOL).

When a pulse is generated on the signal line 30c, the line number is set to 0 (OIOIH). And signal line 30
The value of the line number is incremented every time a pulse occurs at d. In other words, if the line number is 0 (OI
When a pulse is generated on signal 30d in the state of OIH),
The line number is 1 (0103H).

The same applies below. Further, 2-byte data indicating the line number is output to the signal line 14a.

16 inputs the binarized data of the l line output to the signal line 30e, and sends the encoded data (modified Huffman encoding in this embodiment) to the signal line 1.
This is a circuit that outputs to 8c. When the binary data of the l line is input and the number of encoded bits becomes 8, that is, when 1 byte of encoded data is complete, a pulse is generated on the signal line 113a. . on the other hand,
When the encoding of all l lines is completed, the signal line tab
(end) pulse is generated. If the last data is less than 8 bits when encoding of l line is finished,
The remaining data is set to 0, and processing is performed assuming that all 8 bits of data are present.

18 is a FIFO memory used to read line data and store encoded data. On the other hand, the modem side reads the data stored in this FIFO memory, modulates it, and sends it out to the line. The encoded data is written to the Fl''FO memory using the three signal lines from the signal line 30f to the signal line 30h. When a (write) pulse is generated on the signal !a30f, the address output to the signal line 30g is , the byte data output to the signal line 30h is stored.Furthermore, three signal lines, the signal line 3O1, the signal line 30j, and the signal line 18a,
Signal line 3 reads data stored in memory
When a (read) pulse occurs on 0i, the signal line 30j
In this embodiment, the FIFO memory has 8400
It has an address of H to AFFF)I.

Reference numeral 20 denotes a retransmission start address storage memory, whereby when a reception error occurs on the receiving side, the transmitting side device retransmits from the line number where the error occurred. In this case, it is necessary to recognize from which address in the FIFO memory the data of the line number is stored, and this data is stored in this memory. To the signal line 30, using the signal line 3 (111° signal line 30m), write information such as 'from which address in the FIFO memory the data of a certain line number is stored' into the main memory 20, @
When a (light) pulse occurs on the edge line 30m, the signal line 3
The byte data of signal line 30 is stored at the address output to 0k. In addition, the signal line 30n is connected to the signal line 30.
, information such as "from which address in the FIFO memory the data from a certain line number is stored" is read from the main memory 20 using the signal line 20a.

When a (read) pulse is generated on the signal line 30n, the data at the address being output on the signal line 30k is output on the signal line 20a. The retransmission start address storage memory is
It has an address of C0QOH to C3FF)I. The memory configuration for storing the retransmission start address is as shown in FIG.

As shown in FIG. 20, the address COOOH, C00
IH stores the address of line number 0.512..., address CQO2H,0003)1 stores the address of line number 1, 513...,
Address COO4H, GOO5H has line number 2
, 514... are stored, and similarly,
The address (:3FGH, G3FDH stores the address of the line number 510.IQ22..., and the address G3FEH, C3FFH stores the line number 511.
Addresses 1023... are stored.

22 is a parallel-serial conversion circuit (hereinafter abbreviated as P/S conversion circuit) that converts parallel data into serial data. When this P/S conversion circuit 22 becomes empty, the signal line 22a is Generates byte data request pulse. The control circuit 30 outputs byte data to the signal line 300 when a pulse is generated on the signal line 22a. On the other hand, the byte data output to the signal line 300 of the P/S conversion circuit 22 is input, and after performing parallel-to-serial conversion, the serial data is output to the signal line 22b.

24 is a modulator that performs modulation based on the well-known CGIT↑ recommendation V27ter (differential phase modulation). This modulator 24 inputs the signal of the signal line 22b and performs modulation,
The modulated data is output to the signal line 24a.

26 indicates the signal 1 when a pulse is generated on the signal line 30p.
This is a circuit that sends a DCM signal (300b/S signal) to the i28a. This DCN signal sending circuit 2B is a DC
When the sending of the N signal is completed, a pulse is generated on the signal line 26b.

Reference numeral 28 denotes an adder circuit that inputs the signal on the signal line 24a and the signal on the signal line 28a, and outputs the added result to the signal line 28a.

Reference numeral 30 denotes a control circuit, which will be explained in detail in the following items 912 and P113.

913 General operation explanation of the control circuit in the transmitting side device
(Used in FIG. 21) The control circuit 30 shown in FIG. 19 performs the control described below. However, encoding is processed according to the main routine, and signal transmission is processed according to the interwoven routine.

The encoding by the control circuit 30, ie, the control process in the main routine, is as shown in FIG. First, the modem pointer ↑MDPTR and the encoder pointer TMHPTR are set to the start address of the FIFO memory that stores the encoded data (step 5100), and reading of the image information of one main scanning line is completed. In other words, it is determined whether the line buffer is full (Step 2 5102).

When reading the image information of the main scanning line for one line is completed (that is, when the line buffer becomes full),
Proceeding to step 5104, one line of data is read (step 5104).As mentioned above, the buffer has a double buffer configuration with buffer O and buffer l, and these two buffers are alternately read. Read data.

After reading data from each buffer, it is encoded and the encoded data is written to the FIFO memory (step 910B).The main controls during encoding are listed below.

1. Write encoded data to FIFO memory.

2. Write the line end code (EOL signal) (the data to be written to the FIFO memory are Go)I, 80H) and the line number to the FIFO memory.

3. If a reception error occurs in the receiving device, the transmitting device retransmits the data from the line number where the error occurred. The following control is performed to enable this retransmission.

That is, when incrementing the byte in the encoder pointer τN) IPTH, the encoder pointer TMHPTR changes to the modem pointer TMDPTR.
It goes around the IFO memory and controls it so that it does not get too close. Specifically, the encoder's pointer T)I)IP
When TR approaches the modem pointer TMDPTH by 6 or more, encoding is interrupted and a wait state is entered.

Then, while waiting, it is checked whether or not a PIS signal is detected, and if a PIS signal is detected, an NSF signal is received.

Then, the pointer of the modem is set to the retransmission start address, and the data is retransmitted from that data. When performing this retransmission, training is performed again. This is the same as the control in step 5t (18 to step 5112, which will be described later). .

4. When retransmitting data from a certain line number, it is necessary to recognize from which address in the FIFO memory the data of that line number is stored. This information is stored in the retransmission start address storage memory.

And when the encoding of a certain line is finished.

It is determined whether a retransmission request signal, that is, a PIS signal is detected (step 5108). When a retransmission request signal, that is, a PIS signal is detected, the transmission of one-picture information is interrupted,
The NSF signal is received (step 5IIG). If there is a fall pack instruction here, the modem transmission speed is lowered and fallback is performed. Also, D.C.
If the N signal is received, the process ends with an error.

Next, the modem's pointer NDPTR is set to the retransmission start address (this information is included in the NSF signal), and the data is retransmitted from that point (step 5112).
.

After that, it is determined whether the encoding of one page of the manuscript is completed (
Step 5114) If the encoding of one document has not yet been completed, the process returns to step 5102. In addition, when encoding of one document is completed, step S
! Proceed to step 16.

When the encoding of one document sheet is completed, it is determined whether or not there remains unencoded data in the double buffer memory (step 5tte).

If unencoded data remains in the double buffer memory, the process returns to step 5102. Also,
If there is no unencoded data remaining in the double buffer memory, the process advances to step 5118 and a control return signal RTC (Return page) is sent.

Control) is written to the FIFO memory.

Thereafter, it waits for the data stored in the FIFO memory to be sent out by the modem. After the sending of the data stored in the FIFO memory is completed, 1.5
Wait for only seconds. At that time, if it is 5ED-O, proceed to the post-procedure (step 5122). On the other hand, if it is 5ED-1, it means that a PIS signal is being sent from the receiving side device, so the process goes to detect the PIS signal and correct the error retransmission. Execute (Stave 2 5120).

On the other hand, the transmission processing (that is, interwoven processing) consists of (a) modulating the data stored in the modem's pointer NDPTH and sending it to the line, (b) sequentially incrementing the modem's pointer TMDPTR, and (h) ) The main content is to control the modem pointer TMDPTR so that it does not overtake the encoder pointer TMHPTR.

914 Detailed operation explanation of the control circuit in the transmitting side device (using FIGS. 22 and 23) The control procedure performed by the control circuit 30 (main processing, i.e., Encoding processing procedure) will be explained.

First, various initialization processes are performed in steps 5128 to 5144.

In step 8128, a flag TRNEND indicating whether all encoded data stored in the FIFO memory has been sent out is set to O.

In step 513G, the pointer AGAP-R that controls the memory that stores the retransmission start address is set to
Set H.

In step 5132, the encoder pointer T
Set 8400H to MHPTR.

Step S! 34, the modem pointer TMD
Set 84008 in PTR.

The line number is incremented every certain number of lines (1 line in this embodiment), and this control is controlled by a counter called L I HCNT. In step 513B, this counter LINCNT is set to 1.

In step 513B, the above-mentioned REVRS flag is set to 0.6 In step 5140, 0 is set in HEMD as a flag indicating whether or not encoding has been completed.

In step 5142, the flag BAF indicating which buffer is currently reading data is set to 0.
Set. When flag BAF is 0, buffer 0
Reading data from. Also, flag BAF is 1
When , data is being read from buffer l.

In step 5144, the line number is initialized.

In step 5148 to step 5154.

Determine whether the buffer is full, that is, whether reading of l line has finished, and if the buffer is full,
Proceed to step 815B, where the data in the buffers is read alternately from buffer O and buffer 1.

In steps 8156 to 3160, l
Read the line data from the double buffer and output it to the encoder.

In steps 8182 to 5182 shown in FIG. 22(2), data of a specific line number/(- is
The IFO memory address from which the data is stored and the I/% is stored in the retransmission start address storage memory.

Here, when the line number changes, the retransmission start address is stored in the retransmission start address storage memory.

Step! In EIB2, control is performed to increment the line number for each line. Step 51
In steps 84 to 916B, the low byte data at the forwarding start address is stored in the retransmission start address storage memory.

In step 5170, the retransmission start address pointer AGNPTR is incremented.
In step 317B, the high byte data at the retransmission start address is stored in the retransmission start address storage memory. In step 8178,
In step 3180, the retransmission start address pointer AGAPTR is incremented, it is determined whether the retransmission pointer AGAPTR has advanced to the end of the retransmission start address storage memory, and the retransmission pointer AG is incremented.
When APTR reaches the end of the retransmission start address storage memory, C000)1 is set in the retransmission pointer AGAPTR (step 5182).

Step 5I84 to stay 7 shown in FIG. 22(3)
In block 5188, OOH is stored in FIFO memory.

In step 5190, the encoder pointer T
M) Increment IPTR. This TMHPTR
The no increment will be described later.

In steps 5182 to 5196, F
Store 800H in IFO memory.

In step 5198, the encoder pointer T
M) Increment IPTR.

7. In steps 97' 5200 to 5216, input the line number and input the line number.
Store in FO memory. That is, step 5200
Input the line number. Step 52
02 to STAVE 2 5206 store the high byte data of the line number in the FIFO memory. In step 5208, the encoder pointer TMHPTR is incremented.

In steps 5210 to 5214 shown in FIG. 22(4), the low byte data of the line number is stored in the FIFO memory. In step 521B, the encoder pointer TMHPTR is incremented.

In steps 921B to 5230,
Store encoded data in FIFO memory.

First, in step 5218, it is determined whether 1 byte of data has been encoded. 1 /< Once the data is encoded, the data is input (step 52
20) Store L, 1 byte of encoded data in the FIFO memory (steps 5222 to !1l)
i22B).

In step 5228, the encoder pointer T
Increment HPTR. In step 5230, it is determined whether encoding of one line is completed, and ■
If the encoding of the line is not completed, step 5
The process proceeds to 218, and when the encoding of one line is completed,
Step 11. Proceed to block 5232.

In steps 5232 to 5238 shown in FIG. 22(5), it is checked whether or not the line number should be incremented. If it is necessary to increment, the line number is incremented. Here, the line number is incremented for each line.

In steps 5240 to 8248,
It is determined whether a retransmission request signal, that is, a PIS signal has been received. When a PIS signal is received, an NSF signal is received and a retransmission start line number is input.

Then, a retransmission start address is set in the modem pointer TMDPTH, and data is transmitted starting from that address. If there is a fallback instruction, the transmission speed is reduced.

Also, if a DCN signal is received, the line is disconnected.

Furthermore, even after a certain period of time (for example, 30 seconds), the NS
If the F signal cannot be detected, the line is also considered disconnected.

In step 5250, it is determined whether encoding of one document sheet has been completed. If encoding of one document is completed, the process advances to step 5252.

If the encoding of one document sheet has not yet been completed, the process advances to step 5146.

In step 5252 and step 5254,
Determine whether either buffer is full. If either buffer O1 or buffer l is full, the process advances to step 514B. If neither packer O nor buffer 1 is full, the process advances to step 5256.

Step 525 shown in FIG. 22 (8) and FIG. 22 (7)
B to step 5300, a control return signal RTC (Return To Cont) is sent to the FIFO memory.
rol) signal.

First, in steps 5256 to 5260, data of 00H is stored in the FIFO memory.

In step 8262, the encoder pointer T
Increment MHPTR.

In steps 5264 to 5288,
Store 80H data in FIFO memory.

In step 5270, the encoder pointer T
Increment MHPTR.

In steps 5274 to 5304 (see FIG. 22 (7)) and steps 51088 to 91128 (see FIG. 22 (8) and (9)), only 103 signals with line numbers added to the EOL are stored in the FIFO memory. Stored at. The EOL in this embodiment is a signal consisting of 11 consecutive 0's and one 1.

In step 51130, since encoding has been completed, the flag MHEND is set to 1.

In steps 51132 to Stella 7'51170 shown in FIG. 22 (10), all data stored in the memory is waited for to be sent out by the modem.

When a PIS signal is detected, an NSF signal is received and a retransmission start line number is input. Then, it sets the retransmission start address to the modem pointer TMDPTH, and then transmits data from that address. here,
If there is a fallback instruction, the transmission speed will be reduced, and if a DCN signal is received, the process will end with an error. Furthermore, if the NSF signal cannot be detected even after 30 seconds have elapsed, the process ends with an error.

If 5ED-0 after sending RTC from the modem, that is, 1.5 seconds after TRNEND becomes 1,
It determines that the image transmission is complete and proceeds to send the procedure signal.Conversely, if it is 5ED-1 after 1.5 seconds, it proceeds to search for the PIS signal, and within 2 seconds, the PIS signal is sent. When a signal is detected, error retransmission is performed, and if no PIS signal is detected after 2 seconds,
It is determined that the image transmission has been completed, and the process proceeds to transmit the procedure signal.

Steps 930B to 832B shown in FIG.
This is a subroutine when detecting the signal) and setting the modem pointer TMHPTR to the retransmission start address (
Step 5248, Step 5348, Step 5
11813).

The set of retransmission start addresses is 1) R as described above.
If EVR97 lag is 0 (7) 1-1) TMHPTR
>TMDPTR and retransmission address <TMDP
When TR 1-2) TM) IPTR>TMDPTR1 and retransmission address>TM) IPTR1 and retransmission address>TMH
When PTH (in this case, set REVH5 to 1) 2) REVR975 Hook 1 (1) If TMDPTR>
TMHPTR, and retransmission address>TMHP
If TR, set the retransmission address to the modem pointer TMDPTR (step 5318) and return (
Step 9320), otherwise it is treated as an error.

From step 8328 to step 5354 shown in FIG. 22 (12), the encoder pointer TMHPTR
is incremented.

Here, in step 5330, the encoder pointer TMHPTR is incremented. and,
If the high byte of TMHPTR is not incremented, the process returns immediately, but if the high byte of TMHPTR is incremented, the process advances to step 5334.

In steps 5334 to 5338,
The encoder pointer TM)IPTR is controlled so that it does not come too close to the modem pointer TMDρTR during one cycle. That is, the encoder pointer TMHP
If TR is 4086 or more away from the modem pointer TMOPTH, return. At this time, it is checked whether the encoder pointer TM) IPTR has reached the end of the FIFO memory, and if it has reached the end of the FIFO memory, the encoder pointer TM)
Set 8400H to IPTR.

If the encoder pointer TMHPTR is not more than 4098 points away from the modem pointer TMDPH, encoding is interrupted and a wait state is entered. While waiting, it is determined whether a retransmission request signal (ie, PIS signal) is detected (step 5340).

If a PIS signal is detected, the transmission is interrupted (step 5342), the NSF signal is received (step 9344), and the line number to start retransmission is entered (step 934B), and the modem pointer is set to THHP. Set retransmission address.

Here, if there is a fallback instruction, the transmission speed is reduced. Also, if a DCN signal is received,
The line will be disconnected. Furthermore, if the NSF signal cannot be detected even after a certain period of time (for example, 30 seconds) has elapsed,
The line will be disconnected.

The flowchart shown in FIG. 23 shows a detailed control process regarding encoded data transmission processing (i.e., interwoven processing). In this embodiment, a pulse (i.e., byte data request pulse) is generated on the signal line 22a. Then, this interwoven processing is executed.

The main control here is to sequentially read data stored in the FIFO memory from step 5370 to step 5.
37B), output to the P/S conversion circuit 22 (step 5380 to step 538B, step 53
90 to step 939B). At this time, control is performed so that the modem pointer TMDPTR does not overtake the encoder pointer. That is, when OOH, 80H data is detected while transmitting encoded data, if the encoder pointer TMHPTR is less than the modem pointer by a certain amount of light, as described above, a fill is transmitted and encoded. (Steps 5380 to 53i32, Step 5)
404 to step 9410), where MHEN
This is not the case when D is 1 (that is, when encoding of one sheet of original is completed).

When the modem pointer reaches the end of the FIFO memory, the modem pointer TMDPTR is moved to the first address 8400H of the FIFO memory (step 53).
98.

5400).

Also, all encoding is completed (MHEND=1) L
, sends all the data encoded by the modem (TMHPTR
=TMDPTR) (step 5384), set TRNEN[l to 1 in step 53Et6.
), notifies the main processing routine (encoding processing routine) that transmission of all encoded data has been completed.

915 Block Configuration of Receiving Side Apparatus (Used in FIG. 24) FIG. 24 is a block diagram showing the configuration of the receiving side of a facsimile apparatus to which the present invention is applied.

The conditions for performing error retransmission and the conditions for performing fall pack have already been described in detail, so we will not discuss them here; only the processing after actual image signal reception will be described below. .

In FIG. 24, 40 is the same network control unit (ICU) as 2 shown in FIG. Further, 4oa indicates a telephone line.

42 is a hybrid circuit similar to 4 shown in FIG. The signal sent to signal line 54a is transmitted to signal line 40b.
is transmitted to the telephone line 40a via the network control device 4o. Further, the signal sent from the other party's facsimile device is transmitted via the network control device 40 and then sent to the signal line 42a.
is output to.

44 is a circuit that receives the signal ff142a and detects whether or not the signal is present. When receiving a signal of −43 dB m or higher, the signal level [
When receiving a signal of less than -43 dBm, it outputs a signal of signal level "0" to the signal line 44a.

46 is a demodulator that performs demodulation based on the publicly known 17) GCITT recommendation V27ter (differential phase modulation). The demodulator 46 inputs the signal on the signal line 42a, performs demodulation,
The demodulated data is output to the signal line 48a.

48 is a serial-parallel conversion circuit that converts serial data into parallel data (hereinafter referred to as "parallel conversion circuit").

(abbreviated as S/P conversion circuit), this S/P conversion circuit 48 is
When the parallel data of 8 pins is completed, a pulse is generated on the signal line 48a, and the received data is outputted on the signal line 48b. The control circuit 86 connects this signal line 48 . By detecting the occurrence of a pulse at a, it is recognized that 1 byte of data has been received.

50 indicates the signal line 5 when a pulse is generated on the signal line 66b.
This is a circuit that sends an NSF signal (see FIG. 17) to 0a. The NSF signal includes a line number. This line number is set to the value output to the signal line 86a. The NSF signal includes fall pack information. Information about this fall pack is
When the signal line 86b is at the "0" level, the fall pack is not instructed, and when the signal line B6h is at the "1" level, the fall pack is instructed. When the NSF signal sending circuit 50 finishes sending out the NSF signal, the NSF signal sending circuit 50 sends a signal! ! A pulse is generated at 50b.

52 is a circuit that sends out a retransmission request signal (that is, a monthly S signal in this embodiment). In other words, when a pulse is generated on the signal line 88c, a PIS signal is generated on the signal line 52a.
This is a circuit that sends out a signal (462Hz signal for 3 seconds). When the transmission of the PIS signal is completed, a pulse is generated on the signal line 52b.

Reference numeral 54 denotes an adder circuit that inputs the signal on the signal line 50a and the signal on the signal line 52a, and outputs the added result to the signal line 54a.

56 is an F used to demodulate data sent from the other party's facsimile machine and store the demodulated data.
This is IFO memory. This FIFO memory is the F
It is the same as the IFO memory (see 18 in FIG. 19).

On the other hand, the decoder reads the data stored in the FIFO memory, decodes it, records it through the double buffer circuit 82, and writes the demodulated data into the FIFO memory using the signal line 68c or signal line 68e. . When a (write) pulse is generated on the signal line 68c, the signal line 6
The byte data outputted to signal 168e is stored at the address outputted to signal 8d.

In addition, three of the signal lines 66r, 68g, and 58a are
The data stored in the FIFO memory is read using the main signal line. When a (read) pulse is generated on the signal line 86f, the data at the address that is output on the signal line Beg is output on the signal line 58a. In the example, F
IFO memory address is 840QH to AFFF
It is H.

58 is a line number storage memory that stores the latest correctly received line number. When reading the line number into the line number storage memory 58, the line number is output to the signal 168h, and the line number is output to the signal line 66.
Generate a (write) pulse at i. On the other hand, if you want to read the latest correctly received line number, use the signal line 88.
When a (read) pulse is generated on j, the latest correctly received line number is output to the signal line 68h.

60 is a decoder that reads demodulated data from the FIFO memory and outputs the decoded data to the signal line 80c. When preparations for decoding the demodulated 1-byte data are completed, a byte data request pulse is generated on the signal line 80a. When that pulse is generated, tense m circuit 66
reads 1 byte of demodulated data from the FIFO memory and outputs it to the signal line 13Eik. The decoder 60 is
When the decoding of the l line is completed, a pulse is generated on the signal line Bob. Then, one line of decoded data is sent to the signal line 80.
Output to c.

821 is a double buffer 7 circuit for writing the image signal of the next line into the other puffer memory while the image signal in one buffer is being recorded. This buffer is the transmitter's double buffer (12th buffer).
(see 12 in the figure). 2 trees (7) /< -/
7yhaBUFO(/<-/770),BUF1(
When this buffer BUFO, called buffer I), is full of image data, a signal of signal level rlJ is output to signal line 62a (buffer full). BUF
When O's buffer is not full of image data,
Signal level “O” on signal 1182a (buffer 0 full)
Outputs the signal.

Furthermore, when the buffer of BUF 1 is full of image data, a signal of signal level "1" is output to the signal line 62b (buffer 1 full). When the BUFI buffer is not full of image data, the signal 182
A signal with a signal level of "0" is output to b (bar 2 fa 1 full).

A control circuit 68, which will be described later, recognizes that the buffer is empty and specifies which buffer to write data in. That is, when the signal line Hm is at the signal level "0", it writes data into the buffer O; When the signal line 88m is at the signal level rlJ.

After that, the recording data is output to the signal line 88n, and a (write) pulse is generated on the signal line 66.

The double buffer circuit 62 sets the buffer full of the designated /header to 1.

On the other hand, when the recording device 64 finishes recording the line data stored in a certain buffer, it generates a recording request pulse on the signal line 64a.

Furthermore, when the double buffer circuit 82 detects the recording request pulse, if the buffer is full of data,
Record data is output to the signal line 82c. When all the data in the buffer 7 is output to the recording device 64, the buffer full corresponding to that buffer is dropped. Here, the buffers used are buffer o9, buffer 1. Buffer O and buffer 1 alternate.

A recording device 64 generates a recording request pulse on a signal line 84a when preparation for recording is completed. Then, the recording data outputted to the signal line 82c is input, and recording is performed.

66 is a control circuit, and its operation will be explained in detail in item 91B described below.

61θ Explanation of operation of control circuit in receiving side device (used in FIGS. 25 and 28) The control circuit B6 shown in FIG. 24 performs the following control.

Reception of transmission data is processed by the previously described interwoven routine, and decoding is processed by the main routine.

In order to receive data, one byte of data is input every time a pulse is generated on the signal line 48a and stored in the FIFO memory. At this time, the modem pointer RM port PTR
Increment sequentially. On the other hand, the modem pointer R
When NDPTR reaches the end of the FIFO memory, it sets the modem's pointer to the beginning of the FIFO memory. At this time, the REVRS flag is set to 1.

FIG. 25 is a flowchart showing detailed control procedures regarding reception of demodulated data (ie, interwoven processing).

When a pulse is generated on the signal line 48a, interwoven processing starts (step 5600) - step 58
In steps 02 to 5608, demodulated data is input and stored in the FIFO memory.

In step 8608, the modem pointer RMO
Increment PTR.

In step se to, the modem pointer is
Determine whether it has reached the end of the IFO memory, and
When it reaches the end of O, the modem pointer RM
DPTR4: 8400H'It Set/To L, So L
TEREVRS ;y Set lag to 1.

The main processing content of the main processing (decoding processing) process is first to search for the line end code EOL. E
The two bytes following OL indicate the line number. If the line number is incremented by less than 3 compared to the previous time, it is determined that image reception is good. At this time, the line number is updated every time a new line number is received. Therefore, if the line number is three or more higher than the previous one, it is determined that the image reception is not good. Then, the PIS signal and the NSF signal containing the retransmission start line number are sent to the transmitting device. At this time, as mentioned above, the fall pack etc. are controlled, and the receiving device receives from that line number.

When image data is being received correctly, each line of image data is output to the double buffer and recorded. Output to the double buffer is performed using buffer 0. Alternate with buffer 1.

When the encoder pointer reaches the end of the FIFO, the encoder pointer is set to the beginning of the FIFO. At this time, the REVRS flag is set to 0.

Figure 26 (1) to (4) are decoding process (main process)
2 is a flowchart showing details.

Steps 5620 to 5830 shown in FIG. 26(1) represent various initializations.

In step 5820, the modem pointer RMD
Set 8400H to PTR.

In step 5822, the encoder pointer R
Set 8400H to MHPTR.

In step 5624, flag BAF (a flag indicating which buffer the recording data is to be stored in now) is set to 1.

In step 562B, the modem's pointer is
Flag REVR indicating returning from the end of FO to the beginning
Set O to 5.

In steps 5628 to 5830.

Initialize the line number (0) 01) 1).

In steps 5632 to 584G, E
Determine whether or not the office lady has been found. If EOL is found, proceed to step 5642.

In steps 5634 to 5838, one byte of demodulated data is input from the FIFO memory.

In step 5640, the encode pointer is incremented. This will be discussed later (see steps 5720 to 5734).

In steps 5642 to 5854,
It is determined whether the control return signal RTG signal is detected.

In step 5642, it is determined whether there is a possibility of an RTC signal, that is, whether the data after ignoring the 2-byte data following EOL is EOL. If there is a possibility of an RTG signal, step 564
4 or STEP 2 5652 to determine whether an RTC signal has been detected. When the RTC signal is detected, the two-image reception ends (step 5564).

Here, for detection of the RTC signal, for example, rEO
This is assumed to be the case when "l" is detected twice after 11 "O"s have been controlled following LJ. In this case as well, each time EOL is detected, the following 2 bytes of data are ignored.

In steps 5644 to 8648, one byte of demodulated data is input from the FIFQ memory.

In step 5650, the encoder pointer R
Increment 1'1HPTR. Here, RT
If there is no possibility of detecting the C signal, i.e. EOL
The data after ignoring the 2/hate data following is EO
When a value other than L is detected, the process advances to step 385B.

In step 565B, the 2-byte data following the EOL signal, ie, the line number received this time, is input. In step 5858 and step 8860, the latest correctly received line number is input.

In step 5662, it is determined whether the currently received line number is 3 or more larger than the latest correctly received line number, that is, whether an image reception error has occurred. If the line number received this time is 3 or more larger than the latest correctly received line number, that is, if an image reception error has occurred, step 86
Proceed to 98.

If the currently received line number is less than 3 greater than the latest correctly received line number, or if the image reception is good, the process proceeds to step 5664.

In step 5664 and step 5666,
The line number received this time is stored in the line number storage memory 58.

In steps 5668 to 5880 shown in FIG. 26(2), demodulated data is input and decoded to create l-line recording data.

In steps 5688 to 5672,
Input 1 byte of demodulated data from FIFO memory.

In step 5674, the encoder pointer R
Increment MHPTR.

When the decoder requests byte data (step 2 587
B), 1 byte of data is sent to the decoder (
Stella 7'5678) Then, in step 3680, it is determined whether or not the decoding of the l line has been completed. If the decoding of one line has not yet been completed, the process proceeds to step 5668. On the other hand, if the decoding of one line has been completed, the process proceeds to step 5882.

In step 5682, decoded data of 1 line is input, the corresponding buffer is selected, and output to that buffer (step 5684 to step S[f9
B) When writing one line of data to the buffer, buffer 0. Buffer l is selected alternately. and,
Proceeding to step 5632, the next line is decoded.

If the image reception is not good, the process proceeds to step 5688 shown in FIG. 26(3). First, a PIS signal is transmitted (steps S69 to 5700), and transmission by the transmitting device is interrupted. Then, add 1 to the latest correctly received line number and send it to the NSF.
signal, and transmits the NSF signal (steps 5702 to 970B). At this time, as described above, fallback calculation is also controlled.
Then, set the modem pointer RMDPTR to 8400H,
8400H, BA to encoder pointer RMHPTR
F to 1. Set REVR9 to O, perform various initializations, and perform image reception again.

Steps 5720 to 5734 shown in FIG. 28(4) are a subroutine for incrementing the encoder pointer RMHPTR by 1. When incrementing the encoder pointer RMHPTR, it is necessary to control it so that it does not overtake the modem pointer RMDPTR (steps 5722 to 5724).
.

In step 572B, the encoder pointer R
Increment MHPTR. When the encoder pointer reaches the end of the FIFO memory, the start address of the FIFO memory is set in the encoder pointer and O is set in the REVRS flag (step 872).
8 to step 5732) - Also, various timers are operating while the control is being performed, and for example, if the timer expires, the line will be disconnected.

61? Other Embodiments When configuring a facsimile apparatus with an automatic call function, it is also possible to control the facsimile apparatus to select another line and perform automatic call when image transmission fails.

[Effects] As discussed above, according to the present invention, the end-of-line code (EOL) is detected within a predetermined period after entering the image receiving mode.
Since error retransmission can be performed if the error cannot be detected, error retransmission is now possible even when training reception is successful but the demodulated data is not correctly demodulated.

Thus, the item r! mentioned regarding [prior art]! 54
．． 3 Regarding processing when EOL cannot be detected, it has become possible to eliminate the drawbacks.

(Margin below)

[Brief explanation of drawings]

FIG. 1 is a diagram showing an HDLC frame formatter. Figure 2 is a diagram showing a specific example of error retransmission using the HDL (: frame data) shown in Figure 1. Figure 5 is a schematic diagram showing the state when the receiving device fails to receive the training signal in the conventional error retransmission method; Figures 6 (1) to (3) ) is a waveform diagram explaining the reception of training signals and image signals, FIG. 7 is a flowchart showing a conventionally known control procedure for training reception/image signal reception, and FIG. 8 is an embodiment of the present invention. Fig. 9 (1) to (7) are bit configuration diagrams showing specific examples of line numbers, and Fig. 10 shows encoded data and retransmission start addresses corresponding to each line number. FIG. 11 is a block diagram showing the configuration of the sending side of the facsimile machine according to this embodiment. FIG. 12 is a flowchart showing the control procedure to be executed by the control circuit 78 shown in FIG. 11. , Figures 13 (1) and (2) are diagrams explaining the relationship between the FIFO memory and various pointers. Figure 14 is a diagram showing the number of bits and bytes sent in 3 seconds at each transmission speed. Figures (1) and (2) are diagrams showing the relationship between the FIFO memory and various pointers, Figure 16 is a flowchart showing an example of image reception control focusing on error retransmission with fallback, and Figure 17. 30 for the receiving side to communicate the retransmission start address and fall pack presence/absence information to the sending side.
A diagram showing an example of the 0b/S signal, Fig. 18 (1) to (3)
) is a diagram illustrating a method of setting a retransmission start address; FIG. 13 is a block diagram showing an embodiment of the sending side of a facsimile apparatus to which the present invention is applied; FIG. 20 is a configuration diagram showing a retransmission start address storage memory. FIG. 21 is a flowchart showing a general encoding process (ie, main process) of the control circuit 30 shown in FIG. 18. 22 (+) to (12) are detailed encoding processing (i.e. details of main processing) of the control circuit 30 shown in FIG. 19.
23 is a flowchart showing the encoded data transmission procedure (i.e., interwoven processing) controlled by the control circuit 30 shown in FIG. 19.
FIG. 24 is a block diagram showing an embodiment of the receiving side in a facsimile machine to which the present invention is applied, and FIG.
26 (1) to (4) are flowcharts showing demodulated data reception processing (i.e. included processing) controlled by the control circuit 6B shown in FIG.
6 is a flowchart showing a decoding process (ie, main process) controlled by the computer 6. 2...NCu, 4...High print circuit, 6...Retransmission request signal detection circuit, 8...Binary signal receiving circuit, lO...Reading device, 12...Tuple 4F2F Circuit, 14...Line number counter circuit, 16...
Encoding circuit, 18... FIFO memory, 20... Retransmission start address storage memory, 22...P
/S conversion circuit, 24...modulator. 26... DCN signal sending circuit, 28... Adding circuit, 30... Control circuit, 40... NCU, 42... High print circuit, 44... Signal presence/absence detection circuit, 46... Demodulator, 48... S/P conversion circuit, 50... NSF signal sending circuit, 52... Retransmission request signal sending circuit, 54... Adding circuit, 58... FIFO memory. 58... Line number storage memory, 60... Decoder, 62... Double buffer circuit, 64... Recording device, 6B... Control circuit, 67... NCU. 68... Hybrid circuit, 68... Binary signal sending circuit, 70... Tonal signal sending circuit, 71... Addition circuit, 72... Tonal signal detection circuit, 73... Binary signal detection circuit, 74...Start button, 75...Error retransmission mode selection switch 6...Control circuit, 77...Mode conversion notification sound generation circuit. Figure 1 Figure 2 Figure 1 Tf 1 - He - Figure 8 Figure 9 Figure 14 Beat I/Rhino Atsuno (-Rainer) High-ψ Line Cumber! Line number -2 (4) ooooooo+ooooo+or(7)
. 0OOOOOO+ 1loo! Qol Figure 10 TrIFSφφ18φNφ/H+61HB2ss°riH
φ/IIφφH (θdψφd) θφHφ/Hφ3Hβ2H59/l φ/〃Misaki/cI
'H (l141'pP〆)16tsφ5s82〃f9H
φ/HφdH6qbHφ/Hψ7Hβ2Hfell
φ／〃 国〃 8φHφN φ? 〃(842ψH)
β2HsqHφHφu 8dHφ/〃 φBHll2H
5W φ/〃 φ#/ 8φ〃 φys IIIty
y β2M 59H (θdL3PHJ 9I/Hφ
φ〃 8# φ/l〆 φfH82HfQ)〆 Melia. φφge8-〃φiHノ/Hθ2//sysφ//fφguVpu(θ44φM) 8pHφ/H/J//β2
MS'? Hφll gel 8 solutions ψ/H/6Hβ2Hf
Critical ψ／H16φ〃8φHPusζg45ψH) /7
/fB2v sys #ysφφ〃hWφ/N /
YHβ2Hf'7H#Hφ~ °゛. ljNφ l61w l? 4Hφ7〃leg〃φE
H14H/! ;Hz4H(CφφφH) /CHl? 4H・ Figure 13 (REVR, S= I) (REVR5=ψ) (REVR5=I) Figure 18 (1) Figure 18 (2) Figure 18 (3)

Claims (1)

[Scope of Claims] In an image communication device that divides image information into a plurality of line information and transmits them, means for determining that a communication partner has not been able to detect a line end code within a predetermined period; An image communication device comprising: means for controlling retransmission of data in response to a determination result.