JPS61195653U

JPS61195653U -

Info

Publication number: JPS61195653U
Application number: JP7791385U
Authority: JP
Priority date: 1985-05-25
Filing date: 1985-05-25
Publication date: 1986-12-05

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示す回路構成図、
第２図は同上の要部の回路構成図、第３図は同上
の要部の動作説明図である。１は２進カウンタ、２は１０進カウンタ、１０
は一致検出部、１２は表示部、１３はカウンタク
リア部、１５はクロツク制御部である。 FIG. 1 is a circuit diagram showing an embodiment of the present invention;
FIG. 2 is a circuit configuration diagram of the main parts of the same as above, and FIG. 3 is an operation explanatory diagram of the main parts of the same. 1 is a binary counter, 2 is a decimal counter, 10
12 is a display section, 13 is a counter clear section, and 15 is a clock control section.

Claims

[Scope of utility model registration request]

A plurality of switches that set addresses by turning them on and off, a binary counter and a decimal counter that count using the same clock, and a switch that clears the counting operation of both counters by turning on or off any of the above switches. The operation detection unit compares the address set by the switch with the count output of the binary counter and outputs a match signal when the address set by the switch and the count output of the binary counter match. a detection section; a clock control section that starts supplying clocks to both counters at the output of the switch operation detection section and stops supplying clocks to both counters when a coincidence signal is output from the coincidence detection section; and a display section that displays the output of a decimal counter when the coincidence detection section outputs a coincidence signal.