JPS61195614U - - Google Patents

Info

Publication number
JPS61195614U
JPS61195614U JP7894085U JP7894085U JPS61195614U JP S61195614 U JPS61195614 U JP S61195614U JP 7894085 U JP7894085 U JP 7894085U JP 7894085 U JP7894085 U JP 7894085U JP S61195614 U JPS61195614 U JP S61195614U
Authority
JP
Japan
Prior art keywords
inductor
inverter
capacitor
resonant circuit
cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7894085U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7894085U priority Critical patent/JPS61195614U/ja
Publication of JPS61195614U publication Critical patent/JPS61195614U/ja
Pending legal-status Critical Current

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  • Oscillators With Electromechanical Resonators (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a、第2図aは、本考案のCMOS I
Cの圧電発振回路。第1図b、第2図bは、帰還
回路の周波数特性。第3図は、一般のCMOS
ICの圧電発振回路。 11……インバーター、141,241……コ
ンデンサー、142,242……インダクター。
Figures 1a and 2a show the CMOS I of the present invention.
C piezoelectric oscillation circuit. Figures 1b and 2b show the frequency characteristics of the feedback circuit. Figure 3 shows a general CMOS
IC piezoelectric oscillation circuit. 11...Inverter, 141,241...Capacitor, 142,242...Inductor.

補正 昭60.5.31 図面の簡単な説明を次のように補正する。 明細書第6頁第6行目の「第1図a、第2図a
は、」とあるを「第1図a、第2図a、第4図は
、」と補正する。
Amendment May 31, 1980 The brief description of the drawing is amended as follows. “Figure 1 a, Figure 2 a” on page 6, line 6 of the specification
” is corrected to ``Figure 1a, Figure 2a, and Figure 4 are''.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] CMOS ICのインバーターを用いた圧電発
振解路において、該インバーターの入力または出
力との接地間にインダクターとコンデンサーの直
列共振回路またはインダクターとコンデンサーの
並列共振回路を設けたことを特徴とする圧電発振
回路。
A piezoelectric oscillation circuit using a CMOS IC inverter, characterized in that a series resonant circuit of an inductor and a capacitor or a parallel resonant circuit of an inductor and a capacitor is provided between the input or output of the inverter and ground. .
JP7894085U 1985-05-27 1985-05-27 Pending JPS61195614U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7894085U JPS61195614U (en) 1985-05-27 1985-05-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7894085U JPS61195614U (en) 1985-05-27 1985-05-27

Publications (1)

Publication Number Publication Date
JPS61195614U true JPS61195614U (en) 1986-12-05

Family

ID=30623385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7894085U Pending JPS61195614U (en) 1985-05-27 1985-05-27

Country Status (1)

Country Link
JP (1) JPS61195614U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008199568A (en) * 2007-01-18 2008-08-28 Nippon Dempa Kogyo Co Ltd Third overtone crystal oscillator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008199568A (en) * 2007-01-18 2008-08-28 Nippon Dempa Kogyo Co Ltd Third overtone crystal oscillator

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